[ar71xx] update flash locking code
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / include / asm / mach-ar71xx / ar71xx.h
1 /*
2 * Atheros AR71xx SoC specific definitions
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __ASM_MACH_AR71XX_H
15 #define __ASM_MACH_AR71XX_H
16
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/bitops.h>
21
22 #ifndef __ASSEMBLER__
23
24 #define AR71XX_PCI_MEM_BASE 0x10000000
25 #define AR71XX_PCI_MEM_SIZE 0x08000000
26 #define AR71XX_APB_BASE 0x18000000
27 #define AR71XX_GE0_BASE 0x19000000
28 #define AR71XX_GE0_SIZE 0x01000000
29 #define AR71XX_GE1_BASE 0x1a000000
30 #define AR71XX_GE1_SIZE 0x01000000
31 #define AR71XX_EHCI_BASE 0x1b000000
32 #define AR71XX_EHCI_SIZE 0x01000000
33 #define AR71XX_OHCI_BASE 0x1c000000
34 #define AR71XX_OHCI_SIZE 0x01000000
35 #define AR71XX_SPI_BASE 0x1f000000
36 #define AR71XX_SPI_SIZE 0x01000000
37
38 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
39 #define AR71XX_DDR_CTRL_SIZE 0x10000
40 #define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000)
41 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
42 #define AR71XX_UART_SIZE 0x10000
43 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
44 #define AR71XX_USB_CTRL_SIZE 0x10000
45 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
46 #define AR71XX_GPIO_SIZE 0x10000
47 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
48 #define AR71XX_PLL_SIZE 0x10000
49 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
50 #define AR71XX_RESET_SIZE 0x10000
51 #define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
52 #define AR71XX_MII_SIZE 0x10000
53 #define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000)
54 #define AR71XX_SLIC_SIZE 0x10000
55 #define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000)
56 #define AR71XX_DMA_SIZE 0x10000
57 #define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
58 #define AR71XX_STEREO_SIZE 0x10000
59 #define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
60 #define AR91XX_WMAC_SIZE 0x30000
61
62 #define AR71XX_MEM_SIZE_MIN 0x0200000
63 #define AR71XX_MEM_SIZE_MAX 0x10000000
64
65 #define AR71XX_CPU_IRQ_BASE 0
66 #define AR71XX_MISC_IRQ_BASE 8
67 #define AR71XX_MISC_IRQ_COUNT 8
68 #define AR71XX_GPIO_IRQ_BASE 16
69 #define AR71XX_GPIO_IRQ_COUNT 16
70 #define AR71XX_PCI_IRQ_BASE 32
71 #define AR71XX_PCI_IRQ_COUNT 4
72
73 #define AR71XX_CPU_IRQ_PCI (AR71XX_CPU_IRQ_BASE + 2)
74 #define AR71XX_CPU_IRQ_WMAC (AR71XX_CPU_IRQ_BASE + 2)
75 #define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
76 #define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
77 #define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
78 #define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6)
79 #define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7)
80
81 #define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0)
82 #define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1)
83 #define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2)
84 #define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3)
85 #define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4)
86 #define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
87 #define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
88 #define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
89
90 #define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
91
92 #define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0)
93 #define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1)
94 #define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
95 #define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 3)
96
97 extern u32 ar71xx_ahb_freq;
98 extern u32 ar71xx_cpu_freq;
99 extern u32 ar71xx_ddr_freq;
100
101 enum ar71xx_soc_type {
102 AR71XX_SOC_UNKNOWN,
103 AR71XX_SOC_AR7130,
104 AR71XX_SOC_AR7141,
105 AR71XX_SOC_AR7161,
106 AR71XX_SOC_AR9130,
107 AR71XX_SOC_AR9132
108 };
109
110 extern enum ar71xx_soc_type ar71xx_soc;
111
112 extern unsigned long ar71xx_mach_type;
113
114 #define AR71XX_MACH_GENERIC 0
115 #define AR71XX_MACH_WP543 1 /* Compex WP543 */
116 #define AR71XX_MACH_RB_411 2 /* MikroTik RouterBOARD 411/411A/411AH */
117 #define AR71XX_MACH_RB_433 3 /* MikroTik RouterBOARD 433/433AH */
118 #define AR71XX_MACH_RB_450 4 /* MikroTik RouterBOARD 450 */
119 #define AR71XX_MACH_RB_493 5 /* Mikrotik RouterBOARD 493/493AH */
120 #define AR71XX_MACH_AW_NR580 6 /* AzureWave AW-NR580 */
121 #define AR71XX_MACH_AP83 7 /* Atheros AP83 */
122 #define AR71XX_MACH_TEW_632BRP 8 /* TRENDnet TEW-632BRP */
123 #define AR71XX_MACH_UBNT_RS 9 /* Ubiquiti RouterStation */
124 #define AR71XX_MACH_UBNT_LSX 10 /* Ubiquiti LSX */
125 #define AR71XX_MACH_WNR2000 11 /* NETGEAR WNR2000 */
126 #define AR71XX_MACH_PB42 12 /* Atheros PB42 */
127 #define AR71XX_MACH_MZK_W300NH 13 /* Planex MZK-W300NH */
128 #define AR71XX_MACH_MZK_W04NU 14 /* Planex MZK-W04NU */
129 #define AR71XX_MACH_UBNT_LSSR71 15 /* Ubiquiti LS-SR71 */
130 #define AR71XX_MACH_TL_WR941ND 16 /* TP-LINK TL-WR941ND */
131 #define AR71XX_MACH_UBNT_RSPRO 17 /* Ubiquiti RouterStation Pro */
132 #define AR71XX_MACH_AP81 18 /* Atheros AP81 */
133 #define AR71XX_MACH_WRT400N 19 /* Linksys WRT400N */
134 #define AR71XX_MACH_PB44 20 /* Atheros PB44 */
135 #define AR71XX_MACH_WRT160NL 21 /* Linksys WRT160NL */
136
137 /*
138 * PLL block
139 */
140 #define AR71XX_PLL_REG_CPU_CONFIG 0x00
141 #define AR71XX_PLL_REG_SEC_CONFIG 0x04
142 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
143 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
144
145 #define AR71XX_PLL_DIV_SHIFT 3
146 #define AR71XX_PLL_DIV_MASK 0x1f
147 #define AR71XX_CPU_DIV_SHIFT 16
148 #define AR71XX_CPU_DIV_MASK 0x3
149 #define AR71XX_DDR_DIV_SHIFT 18
150 #define AR71XX_DDR_DIV_MASK 0x3
151 #define AR71XX_AHB_DIV_SHIFT 20
152 #define AR71XX_AHB_DIV_MASK 0x7
153
154 #define AR71XX_ETH0_PLL_SHIFT 17
155 #define AR71XX_ETH1_PLL_SHIFT 19
156
157 #define AR91XX_PLL_REG_CPU_CONFIG 0x00
158 #define AR91XX_PLL_REG_ETH_CONFIG 0x04
159 #define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
160 #define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
161
162 #define AR91XX_PLL_DIV_SHIFT 0
163 #define AR91XX_PLL_DIV_MASK 0x3ff
164 #define AR91XX_DDR_DIV_SHIFT 22
165 #define AR91XX_DDR_DIV_MASK 0x3
166 #define AR91XX_AHB_DIV_SHIFT 19
167 #define AR91XX_AHB_DIV_MASK 0x1
168
169 #define AR91XX_ETH0_PLL_SHIFT 20
170 #define AR91XX_ETH1_PLL_SHIFT 22
171
172 extern void __iomem *ar71xx_pll_base;
173
174 static inline void ar71xx_pll_wr(unsigned reg, u32 val)
175 {
176 __raw_writel(val, ar71xx_pll_base + reg);
177 }
178
179 static inline u32 ar71xx_pll_rr(unsigned reg)
180 {
181 return __raw_readl(ar71xx_pll_base + reg);
182 }
183
184 /*
185 * USB_CONFIG block
186 */
187 #define USB_CTRL_REG_FLADJ 0x00
188 #define USB_CTRL_REG_CONFIG 0x04
189
190 extern void __iomem *ar71xx_usb_ctrl_base;
191
192 static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
193 {
194 __raw_writel(val, ar71xx_usb_ctrl_base + reg);
195 }
196
197 static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
198 {
199 return __raw_readl(ar71xx_usb_ctrl_base + reg);
200 }
201
202 /*
203 * GPIO block
204 */
205 #define GPIO_REG_OE 0x00
206 #define GPIO_REG_IN 0x04
207 #define GPIO_REG_OUT 0x08
208 #define GPIO_REG_SET 0x0c
209 #define GPIO_REG_CLEAR 0x10
210 #define GPIO_REG_INT_MODE 0x14
211 #define GPIO_REG_INT_TYPE 0x18
212 #define GPIO_REG_INT_POLARITY 0x1c
213 #define GPIO_REG_INT_PENDING 0x20
214 #define GPIO_REG_INT_ENABLE 0x24
215 #define GPIO_REG_FUNC 0x28
216
217 #define GPIO_FUNC_STEREO_EN BIT(17)
218 #define GPIO_FUNC_SLIC_EN BIT(16)
219 #define GPIO_FUNC_SPI_CS2_EN BIT(13)
220 #define GPIO_FUNC_SPI_CS1_EN BIT(12)
221 #define GPIO_FUNC_UART_EN BIT(8)
222 #define GPIO_FUNC_USB_OC_EN BIT(4)
223 #define GPIO_FUNC_USB_CLK_EN BIT(0)
224
225 #define AR71XX_GPIO_COUNT 16
226 #define AR91XX_GPIO_COUNT 22
227
228 extern void __iomem *ar71xx_gpio_base;
229
230 static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
231 {
232 __raw_writel(value, ar71xx_gpio_base + reg);
233 }
234
235 static inline u32 ar71xx_gpio_rr(unsigned reg)
236 {
237 return __raw_readl(ar71xx_gpio_base + reg);
238 }
239
240 void ar71xx_gpio_init(void) __init;
241 void ar71xx_gpio_function_enable(u32 mask);
242 void ar71xx_gpio_function_disable(u32 mask);
243
244 /*
245 * DDR_CTRL block
246 */
247 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
248 #define AR71XX_DDR_REG_PCI_WIN1 0x80
249 #define AR71XX_DDR_REG_PCI_WIN2 0x84
250 #define AR71XX_DDR_REG_PCI_WIN3 0x88
251 #define AR71XX_DDR_REG_PCI_WIN4 0x8c
252 #define AR71XX_DDR_REG_PCI_WIN5 0x90
253 #define AR71XX_DDR_REG_PCI_WIN6 0x94
254 #define AR71XX_DDR_REG_PCI_WIN7 0x98
255 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c
256 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0
257 #define AR71XX_DDR_REG_FLUSH_USB 0xa4
258 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8
259
260 #define AR91XX_DDR_REG_FLUSH_GE0 0x7c
261 #define AR91XX_DDR_REG_FLUSH_GE1 0x80
262 #define AR91XX_DDR_REG_FLUSH_USB 0x84
263 #define AR91XX_DDR_REG_FLUSH_WMAC 0x88
264
265 #define PCI_WIN0_OFFS 0x10000000
266 #define PCI_WIN1_OFFS 0x11000000
267 #define PCI_WIN2_OFFS 0x12000000
268 #define PCI_WIN3_OFFS 0x13000000
269 #define PCI_WIN4_OFFS 0x14000000
270 #define PCI_WIN5_OFFS 0x15000000
271 #define PCI_WIN6_OFFS 0x16000000
272 #define PCI_WIN7_OFFS 0x07000000
273
274 extern void __iomem *ar71xx_ddr_base;
275
276 static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
277 {
278 __raw_writel(val, ar71xx_ddr_base + reg);
279 }
280
281 static inline u32 ar71xx_ddr_rr(unsigned reg)
282 {
283 return __raw_readl(ar71xx_ddr_base + reg);
284 }
285
286 void ar71xx_ddr_flush(u32 reg);
287
288 /*
289 * PCI block
290 */
291 #define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
292 #define AR71XX_PCI_CFG_SIZE 0x100
293
294 #define PCI_REG_CRP_AD_CBE 0x00
295 #define PCI_REG_CRP_WRDATA 0x04
296 #define PCI_REG_CRP_RDDATA 0x08
297 #define PCI_REG_CFG_AD 0x0c
298 #define PCI_REG_CFG_CBE 0x10
299 #define PCI_REG_CFG_WRDATA 0x14
300 #define PCI_REG_CFG_RDDATA 0x18
301 #define PCI_REG_PCI_ERR 0x1c
302 #define PCI_REG_PCI_ERR_ADDR 0x20
303 #define PCI_REG_AHB_ERR 0x24
304 #define PCI_REG_AHB_ERR_ADDR 0x28
305
306 #define PCI_CRP_CMD_WRITE 0x00010000
307 #define PCI_CRP_CMD_READ 0x00000000
308 #define PCI_CFG_CMD_READ 0x0000000a
309 #define PCI_CFG_CMD_WRITE 0x0000000b
310
311 #define PCI_IDSEL_ADL_START 17
312
313 /*
314 * RESET block
315 */
316 #define AR71XX_RESET_REG_TIMER 0x00
317 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04
318 #define AR71XX_RESET_REG_WDOG_CTRL 0x08
319 #define AR71XX_RESET_REG_WDOG 0x0c
320 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
321 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
322 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
323 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
324 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
325 #define AR71XX_RESET_REG_RESET_MODULE 0x24
326 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c
327 #define AR71XX_RESET_REG_PERFC0 0x30
328 #define AR71XX_RESET_REG_PERFC1 0x34
329 #define AR71XX_RESET_REG_REV_ID 0x90
330
331 #define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18
332 #define AR91XX_RESET_REG_RESET_MODULE 0x1c
333 #define AR91XX_RESET_REG_PERF_CTRL 0x20
334 #define AR91XX_RESET_REG_PERFC0 0x24
335 #define AR91XX_RESET_REG_PERFC1 0x28
336
337 #define WDOG_CTRL_LAST_RESET BIT(31)
338 #define WDOG_CTRL_ACTION_MASK 3
339 #define WDOG_CTRL_ACTION_NONE 0 /* no action */
340 #define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
341 #define WDOG_CTRL_ACTION_NMI 2 /* NMI */
342 #define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
343
344 #define MISC_INT_DMA BIT(7)
345 #define MISC_INT_OHCI BIT(6)
346 #define MISC_INT_PERFC BIT(5)
347 #define MISC_INT_WDOG BIT(4)
348 #define MISC_INT_UART BIT(3)
349 #define MISC_INT_GPIO BIT(2)
350 #define MISC_INT_ERROR BIT(1)
351 #define MISC_INT_TIMER BIT(0)
352
353 #define PCI_INT_CORE BIT(4)
354 #define PCI_INT_DEV2 BIT(2)
355 #define PCI_INT_DEV1 BIT(1)
356 #define PCI_INT_DEV0 BIT(0)
357
358 #define RESET_MODULE_EXTERNAL BIT(28)
359 #define RESET_MODULE_FULL_CHIP BIT(24)
360 #define RESET_MODULE_AMBA2WMAC BIT(22)
361 #define RESET_MODULE_CPU_NMI BIT(21)
362 #define RESET_MODULE_CPU_COLD BIT(20)
363 #define RESET_MODULE_DMA BIT(19)
364 #define RESET_MODULE_SLIC BIT(18)
365 #define RESET_MODULE_STEREO BIT(17)
366 #define RESET_MODULE_DDR BIT(16)
367 #define RESET_MODULE_GE1_MAC BIT(13)
368 #define RESET_MODULE_GE1_PHY BIT(12)
369 #define RESET_MODULE_USBSUS_OVERRIDE BIT(10)
370 #define RESET_MODULE_GE0_MAC BIT(9)
371 #define RESET_MODULE_GE0_PHY BIT(8)
372 #define RESET_MODULE_USB_OHCI_DLL BIT(6)
373 #define RESET_MODULE_USB_HOST BIT(5)
374 #define RESET_MODULE_USB_PHY BIT(4)
375 #define RESET_MODULE_PCI_BUS BIT(1)
376 #define RESET_MODULE_PCI_CORE BIT(0)
377
378 #define REV_ID_MASK 0xff
379 #define REV_ID_CHIP_MASK 0xf3
380 #define REV_ID_CHIP_AR7130 0xa0
381 #define REV_ID_CHIP_AR7141 0xa1
382 #define REV_ID_CHIP_AR7161 0xa2
383 #define REV_ID_CHIP_AR9130 0xb0
384 #define REV_ID_CHIP_AR9132 0xb1
385
386 #define REV_ID_REVISION_MASK 0x3
387 #define REV_ID_REVISION_SHIFT 2
388
389 extern void __iomem *ar71xx_reset_base;
390
391 static inline void ar71xx_reset_wr(unsigned reg, u32 val)
392 {
393 __raw_writel(val, ar71xx_reset_base + reg);
394 }
395
396 static inline u32 ar71xx_reset_rr(unsigned reg)
397 {
398 return __raw_readl(ar71xx_reset_base + reg);
399 }
400
401 void ar71xx_device_stop(u32 mask);
402 void ar71xx_device_start(u32 mask);
403
404 /*
405 * SPI block
406 */
407 #define SPI_REG_FS 0x00 /* Function Select */
408 #define SPI_REG_CTRL 0x04 /* SPI Control */
409 #define SPI_REG_IOC 0x08 /* SPI I/O Control */
410 #define SPI_REG_RDS 0x0c /* Read Data Shift */
411
412 #define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
413
414 #define SPI_CTRL_RD BIT(6) /* Remap Disable */
415 #define SPI_CTRL_DIV_MASK 0x3f
416
417 #define SPI_IOC_DO BIT(0) /* Data Out pin */
418 #define SPI_IOC_CLK BIT(8) /* CLK pin */
419 #define SPI_IOC_CS(n) BIT(16 + (n))
420 #define SPI_IOC_CS0 SPI_IOC_CS(0)
421 #define SPI_IOC_CS1 SPI_IOC_CS(1)
422 #define SPI_IOC_CS2 SPI_IOC_CS(2)
423 #define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
424
425 void ar71xx_flash_acquire(void);
426 void ar71xx_flash_release(void);
427
428 /*
429 * MII_CTRL block
430 */
431 #define MII_REG_MII0_CTRL 0x00
432 #define MII_REG_MII1_CTRL 0x04
433
434 #define MII0_CTRL_IF_GMII 0
435 #define MII0_CTRL_IF_MII 1
436 #define MII0_CTRL_IF_RGMII 2
437 #define MII0_CTRL_IF_RMII 3
438
439 #define MII1_CTRL_IF_RGMII 0
440 #define MII1_CTRL_IF_RMII 1
441
442 #endif /* __ASSEMBLER__ */
443
444 #endif /* __ASM_MACH_AR71XX_H */