575d1819cfc144c2de56796939402c9cee06a19a
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / include / asm / mach-ar71xx / ar71xx.h
1 /*
2 * Atheros AR71xx SoC specific definitions
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __ASM_MACH_AR71XX_H
15 #define __ASM_MACH_AR71XX_H
16
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/bitops.h>
21
22 #ifndef __ASSEMBLER__
23
24 #define AR71XX_PCI_MEM_BASE 0x10000000
25 #define AR71XX_PCI_MEM_SIZE 0x08000000
26 #define AR71XX_APB_BASE 0x18000000
27 #define AR71XX_GE0_BASE 0x19000000
28 #define AR71XX_GE0_SIZE 0x01000000
29 #define AR71XX_GE1_BASE 0x1a000000
30 #define AR71XX_GE1_SIZE 0x01000000
31 #define AR71XX_EHCI_BASE 0x1b000000
32 #define AR71XX_EHCI_SIZE 0x01000000
33 #define AR71XX_OHCI_BASE 0x1c000000
34 #define AR71XX_OHCI_SIZE 0x01000000
35 #define AR7240_OHCI_BASE 0x1b000000
36 #define AR7240_OHCI_SIZE 0x01000000
37 #define AR71XX_SPI_BASE 0x1f000000
38 #define AR71XX_SPI_SIZE 0x01000000
39
40 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
41 #define AR71XX_DDR_CTRL_SIZE 0x10000
42 #define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000)
43 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
44 #define AR71XX_UART_SIZE 0x10000
45 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
46 #define AR71XX_USB_CTRL_SIZE 0x10000
47 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
48 #define AR71XX_GPIO_SIZE 0x10000
49 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
50 #define AR71XX_PLL_SIZE 0x10000
51 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
52 #define AR71XX_RESET_SIZE 0x10000
53 #define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
54 #define AR71XX_MII_SIZE 0x10000
55 #define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000)
56 #define AR71XX_SLIC_SIZE 0x10000
57 #define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000)
58 #define AR71XX_DMA_SIZE 0x10000
59 #define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
60 #define AR71XX_STEREO_SIZE 0x10000
61
62 #define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000)
63 #define AR724X_PCI_CRP_SIZE 0x100
64
65 #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000)
66 #define AR724X_PCI_CTRL_SIZE 0x100
67
68 #define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
69 #define AR91XX_WMAC_SIZE 0x30000
70
71 #define AR71XX_MEM_SIZE_MIN 0x0200000
72 #define AR71XX_MEM_SIZE_MAX 0x10000000
73
74 #define AR71XX_CPU_IRQ_BASE 0
75 #define AR71XX_MISC_IRQ_BASE 8
76 #define AR71XX_MISC_IRQ_COUNT 8
77 #define AR71XX_GPIO_IRQ_BASE 16
78 #define AR71XX_GPIO_IRQ_COUNT 32
79 #define AR71XX_PCI_IRQ_BASE 48
80 #define AR71XX_PCI_IRQ_COUNT 8
81
82 #define AR71XX_CPU_IRQ_PCI (AR71XX_CPU_IRQ_BASE + 2)
83 #define AR71XX_CPU_IRQ_WMAC (AR71XX_CPU_IRQ_BASE + 2)
84 #define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
85 #define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
86 #define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
87 #define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6)
88 #define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7)
89
90 #define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0)
91 #define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1)
92 #define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2)
93 #define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3)
94 #define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4)
95 #define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
96 #define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
97 #define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
98
99 #define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
100
101 #define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0)
102 #define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1)
103 #define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
104 #define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4)
105
106 extern u32 ar71xx_ahb_freq;
107 extern u32 ar71xx_cpu_freq;
108 extern u32 ar71xx_ddr_freq;
109
110 enum ar71xx_soc_type {
111 AR71XX_SOC_UNKNOWN,
112 AR71XX_SOC_AR7130,
113 AR71XX_SOC_AR7141,
114 AR71XX_SOC_AR7161,
115 AR71XX_SOC_AR7240,
116 AR71XX_SOC_AR9130,
117 AR71XX_SOC_AR9132
118 };
119
120 extern enum ar71xx_soc_type ar71xx_soc;
121
122 enum ar71xx_mach_type {
123 AR71XX_MACH_GENERIC = 0,
124 AR71XX_MACH_AP81, /* Atheros AP81 */
125 AR71XX_MACH_AP83, /* Atheros AP83 */
126 AR71XX_MACH_AW_NR580, /* AzureWave AW-NR580 */
127 AR71XX_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */
128 AR71XX_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */
129 AR71XX_MACH_RB_411U, /* MikroTik RouterBOARD 411U */
130 AR71XX_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */
131 AR71XX_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */
132 AR71XX_MACH_RB_450, /* MikroTik RouterBOARD 450 */
133 AR71XX_MACH_RB_450G, /* MikroTik RouterBOARD 450G */
134 AR71XX_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */
135 AR71XX_MACH_PB42, /* Atheros PB42 */
136 AR71XX_MACH_PB44, /* Atheros PB44 */
137 AR71XX_MACH_MZK_W04NU, /* Planex MZK-W04NU */
138 AR71XX_MACH_MZK_W300NH, /* Planex MZK-W300NH */
139 AR71XX_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */
140 AR71XX_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */
141 AR71XX_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */
142 AR71XX_MACH_TL_WR1043ND,/* TP-LINK TL-WR1041ND */
143 AR71XX_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */
144 AR71XX_MACH_UBNT_LSX, /* Ubiquiti LSX */
145 AR71XX_MACH_UBNT_RS, /* Ubiquiti RouterStation */
146 AR71XX_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */
147 AR71XX_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */
148 AR71XX_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */
149 AR71XX_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */
150 AR71XX_MACH_WNR2000, /* NETGEAR WNR2000 */
151 AR71XX_MACH_WNDR3700, /* NETGEAR WNDR3700 */
152 AR71XX_MACH_WP543, /* Compex WP543 */
153 AR71XX_MACH_WRT160NL, /* Linksys WRT160NL */
154 AR71XX_MACH_WRT400N, /* Linksys WRT400N */
155 };
156
157 extern enum ar71xx_mach_type ar71xx_mach;
158
159 /*
160 * PLL block
161 */
162 #define AR71XX_PLL_REG_CPU_CONFIG 0x00
163 #define AR71XX_PLL_REG_SEC_CONFIG 0x04
164 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
165 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
166
167 #define AR71XX_PLL_DIV_SHIFT 3
168 #define AR71XX_PLL_DIV_MASK 0x1f
169 #define AR71XX_CPU_DIV_SHIFT 16
170 #define AR71XX_CPU_DIV_MASK 0x3
171 #define AR71XX_DDR_DIV_SHIFT 18
172 #define AR71XX_DDR_DIV_MASK 0x3
173 #define AR71XX_AHB_DIV_SHIFT 20
174 #define AR71XX_AHB_DIV_MASK 0x7
175
176 #define AR71XX_ETH0_PLL_SHIFT 17
177 #define AR71XX_ETH1_PLL_SHIFT 19
178
179 #define AR724X_PLL_REG_CPU_CONFIG 0x00
180
181 #define AR724X_PLL_DIV_SHIFT 0
182 #define AR724X_PLL_DIV_MASK 0x3ff
183 #define AR724X_PLL_REF_DIV_SHIFT 10
184 #define AR724X_PLL_REF_DIV_MASK 0xf
185 #define AR724X_AHB_DIV_SHIFT 19
186 #define AR724X_AHB_DIV_MASK 0x1
187 #define AR724X_DDR_DIV_SHIFT 22
188 #define AR724X_DDR_DIV_MASK 0x3
189
190 #define AR91XX_PLL_REG_CPU_CONFIG 0x00
191 #define AR91XX_PLL_REG_ETH_CONFIG 0x04
192 #define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
193 #define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
194
195 #define AR91XX_PLL_DIV_SHIFT 0
196 #define AR91XX_PLL_DIV_MASK 0x3ff
197 #define AR91XX_DDR_DIV_SHIFT 22
198 #define AR91XX_DDR_DIV_MASK 0x3
199 #define AR91XX_AHB_DIV_SHIFT 19
200 #define AR91XX_AHB_DIV_MASK 0x1
201
202 #define AR91XX_ETH0_PLL_SHIFT 20
203 #define AR91XX_ETH1_PLL_SHIFT 22
204
205 extern void __iomem *ar71xx_pll_base;
206
207 static inline void ar71xx_pll_wr(unsigned reg, u32 val)
208 {
209 __raw_writel(val, ar71xx_pll_base + reg);
210 }
211
212 static inline u32 ar71xx_pll_rr(unsigned reg)
213 {
214 return __raw_readl(ar71xx_pll_base + reg);
215 }
216
217 /*
218 * USB_CONFIG block
219 */
220 #define USB_CTRL_REG_FLADJ 0x00
221 #define USB_CTRL_REG_CONFIG 0x04
222
223 extern void __iomem *ar71xx_usb_ctrl_base;
224
225 static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
226 {
227 __raw_writel(val, ar71xx_usb_ctrl_base + reg);
228 }
229
230 static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
231 {
232 return __raw_readl(ar71xx_usb_ctrl_base + reg);
233 }
234
235 /*
236 * GPIO block
237 */
238 #define GPIO_REG_OE 0x00
239 #define GPIO_REG_IN 0x04
240 #define GPIO_REG_OUT 0x08
241 #define GPIO_REG_SET 0x0c
242 #define GPIO_REG_CLEAR 0x10
243 #define GPIO_REG_INT_MODE 0x14
244 #define GPIO_REG_INT_TYPE 0x18
245 #define GPIO_REG_INT_POLARITY 0x1c
246 #define GPIO_REG_INT_PENDING 0x20
247 #define GPIO_REG_INT_ENABLE 0x24
248 #define GPIO_REG_FUNC 0x28
249
250 #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
251 #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
252 #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
253 #define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
254 #define AR71XX_GPIO_FUNC_UART_EN BIT(8)
255 #define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
256 #define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
257
258 #define AR71XX_GPIO_COUNT 16
259
260 #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
261 #define AR724X_GPIO_FUNC_SPI_EN BIT(18)
262 #define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
263 #define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
264 #define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
265 #define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
266 #define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
267 #define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
268 #define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
269 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
270 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
271 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
272 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
273 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
274 #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
275 #define AR724X_GPIO_FUNC_UART_EN BIT(1)
276 #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
277
278 #define AR724X_GPIO_COUNT 18
279
280 #define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22)
281 #define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
282 #define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20)
283 #define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19)
284 #define AR91XX_GPIO_FUNC_I2S1_EN BIT(18)
285 #define AR91XX_GPIO_FUNC_I2S0_EN BIT(17)
286 #define AR91XX_GPIO_FUNC_SLIC_EN BIT(16)
287 #define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
288 #define AR91XX_GPIO_FUNC_UART_EN BIT(8)
289 #define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4)
290
291 #define AR91XX_GPIO_COUNT 22
292
293 extern void __iomem *ar71xx_gpio_base;
294
295 static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
296 {
297 __raw_writel(value, ar71xx_gpio_base + reg);
298 }
299
300 static inline u32 ar71xx_gpio_rr(unsigned reg)
301 {
302 return __raw_readl(ar71xx_gpio_base + reg);
303 }
304
305 void ar71xx_gpio_init(void) __init;
306 void ar71xx_gpio_function_enable(u32 mask);
307 void ar71xx_gpio_function_disable(u32 mask);
308
309 /*
310 * DDR_CTRL block
311 */
312 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
313 #define AR71XX_DDR_REG_PCI_WIN1 0x80
314 #define AR71XX_DDR_REG_PCI_WIN2 0x84
315 #define AR71XX_DDR_REG_PCI_WIN3 0x88
316 #define AR71XX_DDR_REG_PCI_WIN4 0x8c
317 #define AR71XX_DDR_REG_PCI_WIN5 0x90
318 #define AR71XX_DDR_REG_PCI_WIN6 0x94
319 #define AR71XX_DDR_REG_PCI_WIN7 0x98
320 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c
321 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0
322 #define AR71XX_DDR_REG_FLUSH_USB 0xa4
323 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8
324
325 #define AR724X_DDR_REG_FLUSH_GE0 0x7c
326 #define AR724X_DDR_REG_FLUSH_GE1 0x80
327 #define AR724X_DDR_REG_FLUSH_USB 0x84
328 #define AR724X_DDR_REG_FLUSH_PCIE 0x88
329
330 #define AR91XX_DDR_REG_FLUSH_GE0 0x7c
331 #define AR91XX_DDR_REG_FLUSH_GE1 0x80
332 #define AR91XX_DDR_REG_FLUSH_USB 0x84
333 #define AR91XX_DDR_REG_FLUSH_WMAC 0x88
334
335 #define PCI_WIN0_OFFS 0x10000000
336 #define PCI_WIN1_OFFS 0x11000000
337 #define PCI_WIN2_OFFS 0x12000000
338 #define PCI_WIN3_OFFS 0x13000000
339 #define PCI_WIN4_OFFS 0x14000000
340 #define PCI_WIN5_OFFS 0x15000000
341 #define PCI_WIN6_OFFS 0x16000000
342 #define PCI_WIN7_OFFS 0x07000000
343
344 extern void __iomem *ar71xx_ddr_base;
345
346 static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
347 {
348 __raw_writel(val, ar71xx_ddr_base + reg);
349 }
350
351 static inline u32 ar71xx_ddr_rr(unsigned reg)
352 {
353 return __raw_readl(ar71xx_ddr_base + reg);
354 }
355
356 void ar71xx_ddr_flush(u32 reg);
357
358 /*
359 * PCI block
360 */
361 #define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
362 #define AR71XX_PCI_CFG_SIZE 0x100
363
364 #define PCI_REG_CRP_AD_CBE 0x00
365 #define PCI_REG_CRP_WRDATA 0x04
366 #define PCI_REG_CRP_RDDATA 0x08
367 #define PCI_REG_CFG_AD 0x0c
368 #define PCI_REG_CFG_CBE 0x10
369 #define PCI_REG_CFG_WRDATA 0x14
370 #define PCI_REG_CFG_RDDATA 0x18
371 #define PCI_REG_PCI_ERR 0x1c
372 #define PCI_REG_PCI_ERR_ADDR 0x20
373 #define PCI_REG_AHB_ERR 0x24
374 #define PCI_REG_AHB_ERR_ADDR 0x28
375
376 #define PCI_CRP_CMD_WRITE 0x00010000
377 #define PCI_CRP_CMD_READ 0x00000000
378 #define PCI_CFG_CMD_READ 0x0000000a
379 #define PCI_CFG_CMD_WRITE 0x0000000b
380
381 #define PCI_IDSEL_ADL_START 17
382
383 #define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000)
384 #define AR724X_PCI_CFG_SIZE 0x1000
385
386 #define AR724X_PCI_REG_INT_STATUS 0x4c
387 #define AR724X_PCI_REG_INT_MASK 0x50
388
389 #define AR724X_PCI_INT_DEV0 BIT(14)
390
391 static inline void ar724x_pci_wr(unsigned reg, u32 val)
392 {
393 void __iomem *base;
394
395 base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
396 __raw_writel(val, base + reg);
397 iounmap(base);
398 }
399
400 static inline u32 ar724x_pci_rr(unsigned reg)
401 {
402 void __iomem *base;
403 u32 ret;
404
405 base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
406 ret = __raw_readl(base + reg);
407 iounmap(base);
408 return ret;
409 }
410
411 /*
412 * RESET block
413 */
414 #define AR71XX_RESET_REG_TIMER 0x00
415 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04
416 #define AR71XX_RESET_REG_WDOG_CTRL 0x08
417 #define AR71XX_RESET_REG_WDOG 0x0c
418 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
419 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
420 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
421 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
422 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
423 #define AR71XX_RESET_REG_RESET_MODULE 0x24
424 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c
425 #define AR71XX_RESET_REG_PERFC0 0x30
426 #define AR71XX_RESET_REG_PERFC1 0x34
427 #define AR71XX_RESET_REG_REV_ID 0x90
428
429 #define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18
430 #define AR91XX_RESET_REG_RESET_MODULE 0x1c
431 #define AR91XX_RESET_REG_PERF_CTRL 0x20
432 #define AR91XX_RESET_REG_PERFC0 0x24
433 #define AR91XX_RESET_REG_PERFC1 0x28
434
435 #define AR724X_RESET_REG_RESET_MODULE 0x1c
436
437 #define WDOG_CTRL_LAST_RESET BIT(31)
438 #define WDOG_CTRL_ACTION_MASK 3
439 #define WDOG_CTRL_ACTION_NONE 0 /* no action */
440 #define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
441 #define WDOG_CTRL_ACTION_NMI 2 /* NMI */
442 #define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
443
444 #define MISC_INT_DMA BIT(7)
445 #define MISC_INT_OHCI BIT(6)
446 #define MISC_INT_PERFC BIT(5)
447 #define MISC_INT_WDOG BIT(4)
448 #define MISC_INT_UART BIT(3)
449 #define MISC_INT_GPIO BIT(2)
450 #define MISC_INT_ERROR BIT(1)
451 #define MISC_INT_TIMER BIT(0)
452
453 #define PCI_INT_CORE BIT(4)
454 #define PCI_INT_DEV2 BIT(2)
455 #define PCI_INT_DEV1 BIT(1)
456 #define PCI_INT_DEV0 BIT(0)
457
458 #define RESET_MODULE_EXTERNAL BIT(28)
459 #define RESET_MODULE_FULL_CHIP BIT(24)
460 #define RESET_MODULE_AMBA2WMAC BIT(22)
461 #define RESET_MODULE_CPU_NMI BIT(21)
462 #define RESET_MODULE_CPU_COLD BIT(20)
463 #define RESET_MODULE_DMA BIT(19)
464 #define RESET_MODULE_SLIC BIT(18)
465 #define RESET_MODULE_STEREO BIT(17)
466 #define RESET_MODULE_DDR BIT(16)
467 #define RESET_MODULE_GE1_MAC BIT(13)
468 #define RESET_MODULE_GE1_PHY BIT(12)
469 #define RESET_MODULE_USBSUS_OVERRIDE BIT(10)
470 #define RESET_MODULE_GE0_MAC BIT(9)
471 #define RESET_MODULE_GE0_PHY BIT(8)
472 #define RESET_MODULE_USB_OHCI_DLL BIT(6)
473 #define RESET_MODULE_USB_HOST BIT(5)
474 #define RESET_MODULE_USB_PHY BIT(4)
475 #define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3)
476 #define RESET_MODULE_PCI_BUS BIT(1)
477 #define RESET_MODULE_PCI_CORE BIT(0)
478
479 #define REV_ID_MAJOR_MASK 0xf0
480 #define REV_ID_MAJOR_AR71XX 0xa0
481 #define REV_ID_MAJOR_AR913X 0xb0
482 #define REV_ID_MAJOR_AR724X 0xc0
483
484 #define AR71XX_REV_ID_MINOR_MASK 0x3
485 #define AR71XX_REV_ID_MINOR_AR7130 0x0
486 #define AR71XX_REV_ID_MINOR_AR7141 0x1
487 #define AR71XX_REV_ID_MINOR_AR7161 0x2
488 #define AR71XX_REV_ID_REVISION_MASK 0x3
489 #define AR71XX_REV_ID_REVISION_SHIFT 2
490
491 #define AR91XX_REV_ID_MINOR_MASK 0x3
492 #define AR91XX_REV_ID_MINOR_AR9130 0x0
493 #define AR91XX_REV_ID_MINOR_AR9132 0x1
494 #define AR91XX_REV_ID_REVISION_MASK 0x3
495 #define AR91XX_REV_ID_REVISION_SHIFT 2
496
497 #define AR724X_REV_ID_REVISION_MASK 0x3
498
499 extern void __iomem *ar71xx_reset_base;
500
501 static inline void ar71xx_reset_wr(unsigned reg, u32 val)
502 {
503 __raw_writel(val, ar71xx_reset_base + reg);
504 }
505
506 static inline u32 ar71xx_reset_rr(unsigned reg)
507 {
508 return __raw_readl(ar71xx_reset_base + reg);
509 }
510
511 void ar71xx_device_stop(u32 mask);
512 void ar71xx_device_start(u32 mask);
513
514 /*
515 * SPI block
516 */
517 #define SPI_REG_FS 0x00 /* Function Select */
518 #define SPI_REG_CTRL 0x04 /* SPI Control */
519 #define SPI_REG_IOC 0x08 /* SPI I/O Control */
520 #define SPI_REG_RDS 0x0c /* Read Data Shift */
521
522 #define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
523
524 #define SPI_CTRL_RD BIT(6) /* Remap Disable */
525 #define SPI_CTRL_DIV_MASK 0x3f
526
527 #define SPI_IOC_DO BIT(0) /* Data Out pin */
528 #define SPI_IOC_CLK BIT(8) /* CLK pin */
529 #define SPI_IOC_CS(n) BIT(16 + (n))
530 #define SPI_IOC_CS0 SPI_IOC_CS(0)
531 #define SPI_IOC_CS1 SPI_IOC_CS(1)
532 #define SPI_IOC_CS2 SPI_IOC_CS(2)
533 #define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
534
535 void ar71xx_flash_acquire(void);
536 void ar71xx_flash_release(void);
537
538 /*
539 * MII_CTRL block
540 */
541 #define MII_REG_MII0_CTRL 0x00
542 #define MII_REG_MII1_CTRL 0x04
543
544 #define MII0_CTRL_IF_GMII 0
545 #define MII0_CTRL_IF_MII 1
546 #define MII0_CTRL_IF_RGMII 2
547 #define MII0_CTRL_IF_RMII 3
548
549 #define MII1_CTRL_IF_RGMII 0
550 #define MII1_CTRL_IF_RMII 1
551
552 #endif /* __ASSEMBLER__ */
553
554 #endif /* __ASM_MACH_AR71XX_H */