ar71xx: merge AR71XX_IRQ_CPU_{PCI,WMAC} into AR71XX_IRQ_CPU_IP2
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / include / asm / mach-ar71xx / ar71xx.h
1 /*
2 * Atheros AR71xx SoC specific definitions
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __ASM_MACH_AR71XX_H
15 #define __ASM_MACH_AR71XX_H
16
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/bitops.h>
21
22 #ifndef __ASSEMBLER__
23
24 #define AR71XX_PCI_MEM_BASE 0x10000000
25 #define AR71XX_PCI_MEM_SIZE 0x08000000
26 #define AR71XX_APB_BASE 0x18000000
27 #define AR71XX_GE0_BASE 0x19000000
28 #define AR71XX_GE0_SIZE 0x01000000
29 #define AR71XX_GE1_BASE 0x1a000000
30 #define AR71XX_GE1_SIZE 0x01000000
31 #define AR71XX_EHCI_BASE 0x1b000000
32 #define AR71XX_EHCI_SIZE 0x01000000
33 #define AR71XX_OHCI_BASE 0x1c000000
34 #define AR71XX_OHCI_SIZE 0x01000000
35 #define AR7240_OHCI_BASE 0x1b000000
36 #define AR7240_OHCI_SIZE 0x01000000
37 #define AR71XX_SPI_BASE 0x1f000000
38 #define AR71XX_SPI_SIZE 0x01000000
39
40 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
41 #define AR71XX_DDR_CTRL_SIZE 0x10000
42 #define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000)
43 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
44 #define AR71XX_UART_SIZE 0x10000
45 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
46 #define AR71XX_USB_CTRL_SIZE 0x10000
47 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
48 #define AR71XX_GPIO_SIZE 0x10000
49 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
50 #define AR71XX_PLL_SIZE 0x10000
51 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
52 #define AR71XX_RESET_SIZE 0x10000
53 #define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
54 #define AR71XX_MII_SIZE 0x10000
55 #define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000)
56 #define AR71XX_SLIC_SIZE 0x10000
57 #define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000)
58 #define AR71XX_DMA_SIZE 0x10000
59 #define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
60 #define AR71XX_STEREO_SIZE 0x10000
61
62 #define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000)
63 #define AR724X_PCI_CRP_SIZE 0x100
64
65 #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000)
66 #define AR724X_PCI_CTRL_SIZE 0x100
67
68 #define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
69 #define AR91XX_WMAC_SIZE 0x30000
70
71 #define AR71XX_MEM_SIZE_MIN 0x0200000
72 #define AR71XX_MEM_SIZE_MAX 0x10000000
73
74 #define AR71XX_CPU_IRQ_BASE 0
75 #define AR71XX_MISC_IRQ_BASE 8
76 #define AR71XX_MISC_IRQ_COUNT 8
77 #define AR71XX_GPIO_IRQ_BASE 16
78 #define AR71XX_GPIO_IRQ_COUNT 32
79 #define AR71XX_PCI_IRQ_BASE 48
80 #define AR71XX_PCI_IRQ_COUNT 8
81
82 #define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2)
83 #define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
84 #define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
85 #define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
86 #define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6)
87 #define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7)
88
89 #define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0)
90 #define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1)
91 #define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2)
92 #define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3)
93 #define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4)
94 #define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
95 #define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
96 #define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
97
98 #define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
99
100 #define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0)
101 #define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1)
102 #define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
103 #define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4)
104
105 extern u32 ar71xx_ahb_freq;
106 extern u32 ar71xx_cpu_freq;
107 extern u32 ar71xx_ddr_freq;
108
109 enum ar71xx_soc_type {
110 AR71XX_SOC_UNKNOWN,
111 AR71XX_SOC_AR7130,
112 AR71XX_SOC_AR7141,
113 AR71XX_SOC_AR7161,
114 AR71XX_SOC_AR7240,
115 AR71XX_SOC_AR9130,
116 AR71XX_SOC_AR9132
117 };
118
119 extern enum ar71xx_soc_type ar71xx_soc;
120
121 /*
122 * PLL block
123 */
124 #define AR71XX_PLL_REG_CPU_CONFIG 0x00
125 #define AR71XX_PLL_REG_SEC_CONFIG 0x04
126 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
127 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
128
129 #define AR71XX_PLL_DIV_SHIFT 3
130 #define AR71XX_PLL_DIV_MASK 0x1f
131 #define AR71XX_CPU_DIV_SHIFT 16
132 #define AR71XX_CPU_DIV_MASK 0x3
133 #define AR71XX_DDR_DIV_SHIFT 18
134 #define AR71XX_DDR_DIV_MASK 0x3
135 #define AR71XX_AHB_DIV_SHIFT 20
136 #define AR71XX_AHB_DIV_MASK 0x7
137
138 #define AR71XX_ETH0_PLL_SHIFT 17
139 #define AR71XX_ETH1_PLL_SHIFT 19
140
141 #define AR724X_PLL_REG_CPU_CONFIG 0x00
142 #define AR724X_PLL_REG_PCIE_CONFIG 0x18
143
144 #define AR724X_PLL_DIV_SHIFT 0
145 #define AR724X_PLL_DIV_MASK 0x3ff
146 #define AR724X_PLL_REF_DIV_SHIFT 10
147 #define AR724X_PLL_REF_DIV_MASK 0xf
148 #define AR724X_AHB_DIV_SHIFT 19
149 #define AR724X_AHB_DIV_MASK 0x1
150 #define AR724X_DDR_DIV_SHIFT 22
151 #define AR724X_DDR_DIV_MASK 0x3
152
153 #define AR91XX_PLL_REG_CPU_CONFIG 0x00
154 #define AR91XX_PLL_REG_ETH_CONFIG 0x04
155 #define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
156 #define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
157
158 #define AR91XX_PLL_DIV_SHIFT 0
159 #define AR91XX_PLL_DIV_MASK 0x3ff
160 #define AR91XX_DDR_DIV_SHIFT 22
161 #define AR91XX_DDR_DIV_MASK 0x3
162 #define AR91XX_AHB_DIV_SHIFT 19
163 #define AR91XX_AHB_DIV_MASK 0x1
164
165 #define AR91XX_ETH0_PLL_SHIFT 20
166 #define AR91XX_ETH1_PLL_SHIFT 22
167
168 extern void __iomem *ar71xx_pll_base;
169
170 static inline void ar71xx_pll_wr(unsigned reg, u32 val)
171 {
172 __raw_writel(val, ar71xx_pll_base + reg);
173 }
174
175 static inline u32 ar71xx_pll_rr(unsigned reg)
176 {
177 return __raw_readl(ar71xx_pll_base + reg);
178 }
179
180 /*
181 * USB_CONFIG block
182 */
183 #define USB_CTRL_REG_FLADJ 0x00
184 #define USB_CTRL_REG_CONFIG 0x04
185
186 extern void __iomem *ar71xx_usb_ctrl_base;
187
188 static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
189 {
190 __raw_writel(val, ar71xx_usb_ctrl_base + reg);
191 }
192
193 static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
194 {
195 return __raw_readl(ar71xx_usb_ctrl_base + reg);
196 }
197
198 /*
199 * GPIO block
200 */
201 #define GPIO_REG_OE 0x00
202 #define GPIO_REG_IN 0x04
203 #define GPIO_REG_OUT 0x08
204 #define GPIO_REG_SET 0x0c
205 #define GPIO_REG_CLEAR 0x10
206 #define GPIO_REG_INT_MODE 0x14
207 #define GPIO_REG_INT_TYPE 0x18
208 #define GPIO_REG_INT_POLARITY 0x1c
209 #define GPIO_REG_INT_PENDING 0x20
210 #define GPIO_REG_INT_ENABLE 0x24
211 #define GPIO_REG_FUNC 0x28
212
213 #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
214 #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
215 #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
216 #define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
217 #define AR71XX_GPIO_FUNC_UART_EN BIT(8)
218 #define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
219 #define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
220
221 #define AR71XX_GPIO_COUNT 16
222
223 #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
224 #define AR724X_GPIO_FUNC_SPI_EN BIT(18)
225 #define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
226 #define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
227 #define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
228 #define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
229 #define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
230 #define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
231 #define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
232 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
233 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
234 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
235 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
236 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
237 #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
238 #define AR724X_GPIO_FUNC_UART_EN BIT(1)
239 #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
240
241 #define AR724X_GPIO_COUNT 18
242
243 #define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22)
244 #define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
245 #define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20)
246 #define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19)
247 #define AR91XX_GPIO_FUNC_I2S1_EN BIT(18)
248 #define AR91XX_GPIO_FUNC_I2S0_EN BIT(17)
249 #define AR91XX_GPIO_FUNC_SLIC_EN BIT(16)
250 #define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
251 #define AR91XX_GPIO_FUNC_UART_EN BIT(8)
252 #define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4)
253
254 #define AR91XX_GPIO_COUNT 22
255
256 extern void __iomem *ar71xx_gpio_base;
257
258 static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
259 {
260 __raw_writel(value, ar71xx_gpio_base + reg);
261 }
262
263 static inline u32 ar71xx_gpio_rr(unsigned reg)
264 {
265 return __raw_readl(ar71xx_gpio_base + reg);
266 }
267
268 void ar71xx_gpio_init(void) __init;
269 void ar71xx_gpio_function_enable(u32 mask);
270 void ar71xx_gpio_function_disable(u32 mask);
271 void ar71xx_gpio_function_setup(u32 set, u32 clear);
272
273 /*
274 * DDR_CTRL block
275 */
276 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
277 #define AR71XX_DDR_REG_PCI_WIN1 0x80
278 #define AR71XX_DDR_REG_PCI_WIN2 0x84
279 #define AR71XX_DDR_REG_PCI_WIN3 0x88
280 #define AR71XX_DDR_REG_PCI_WIN4 0x8c
281 #define AR71XX_DDR_REG_PCI_WIN5 0x90
282 #define AR71XX_DDR_REG_PCI_WIN6 0x94
283 #define AR71XX_DDR_REG_PCI_WIN7 0x98
284 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c
285 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0
286 #define AR71XX_DDR_REG_FLUSH_USB 0xa4
287 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8
288
289 #define AR724X_DDR_REG_FLUSH_GE0 0x7c
290 #define AR724X_DDR_REG_FLUSH_GE1 0x80
291 #define AR724X_DDR_REG_FLUSH_USB 0x84
292 #define AR724X_DDR_REG_FLUSH_PCIE 0x88
293
294 #define AR91XX_DDR_REG_FLUSH_GE0 0x7c
295 #define AR91XX_DDR_REG_FLUSH_GE1 0x80
296 #define AR91XX_DDR_REG_FLUSH_USB 0x84
297 #define AR91XX_DDR_REG_FLUSH_WMAC 0x88
298
299 #define PCI_WIN0_OFFS 0x10000000
300 #define PCI_WIN1_OFFS 0x11000000
301 #define PCI_WIN2_OFFS 0x12000000
302 #define PCI_WIN3_OFFS 0x13000000
303 #define PCI_WIN4_OFFS 0x14000000
304 #define PCI_WIN5_OFFS 0x15000000
305 #define PCI_WIN6_OFFS 0x16000000
306 #define PCI_WIN7_OFFS 0x07000000
307
308 extern void __iomem *ar71xx_ddr_base;
309
310 static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
311 {
312 __raw_writel(val, ar71xx_ddr_base + reg);
313 }
314
315 static inline u32 ar71xx_ddr_rr(unsigned reg)
316 {
317 return __raw_readl(ar71xx_ddr_base + reg);
318 }
319
320 void ar71xx_ddr_flush(u32 reg);
321
322 /*
323 * PCI block
324 */
325 #define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
326 #define AR71XX_PCI_CFG_SIZE 0x100
327
328 #define PCI_REG_CRP_AD_CBE 0x00
329 #define PCI_REG_CRP_WRDATA 0x04
330 #define PCI_REG_CRP_RDDATA 0x08
331 #define PCI_REG_CFG_AD 0x0c
332 #define PCI_REG_CFG_CBE 0x10
333 #define PCI_REG_CFG_WRDATA 0x14
334 #define PCI_REG_CFG_RDDATA 0x18
335 #define PCI_REG_PCI_ERR 0x1c
336 #define PCI_REG_PCI_ERR_ADDR 0x20
337 #define PCI_REG_AHB_ERR 0x24
338 #define PCI_REG_AHB_ERR_ADDR 0x28
339
340 #define PCI_CRP_CMD_WRITE 0x00010000
341 #define PCI_CRP_CMD_READ 0x00000000
342 #define PCI_CFG_CMD_READ 0x0000000a
343 #define PCI_CFG_CMD_WRITE 0x0000000b
344
345 #define PCI_IDSEL_ADL_START 17
346
347 #define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000)
348 #define AR724X_PCI_CFG_SIZE 0x1000
349
350 #define AR724X_PCI_REG_APP 0x00
351 #define AR724X_PCI_REG_RESET 0x18
352 #define AR724X_PCI_REG_INT_STATUS 0x4c
353 #define AR724X_PCI_REG_INT_MASK 0x50
354
355 #define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
356
357 #define AR724X_PCI_INT_DEV0 BIT(14)
358
359 static inline void ar724x_pci_wr(unsigned reg, u32 val)
360 {
361 void __iomem *base;
362
363 base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
364 __raw_writel(val, base + reg);
365 (void) __raw_readl(base + reg);
366 iounmap(base);
367 }
368
369 static inline void ar724x_pci_wr_nf(unsigned reg, u32 val)
370 {
371 void __iomem *base;
372
373 base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
374 __raw_writel(val, base + reg);
375 iounmap(base);
376 }
377
378 static inline u32 ar724x_pci_rr(unsigned reg)
379 {
380 void __iomem *base;
381 u32 ret;
382
383 base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
384 ret = __raw_readl(base + reg);
385 iounmap(base);
386 return ret;
387 }
388
389 /*
390 * RESET block
391 */
392 #define AR71XX_RESET_REG_TIMER 0x00
393 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04
394 #define AR71XX_RESET_REG_WDOG_CTRL 0x08
395 #define AR71XX_RESET_REG_WDOG 0x0c
396 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
397 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
398 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
399 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
400 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
401 #define AR71XX_RESET_REG_RESET_MODULE 0x24
402 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c
403 #define AR71XX_RESET_REG_PERFC0 0x30
404 #define AR71XX_RESET_REG_PERFC1 0x34
405 #define AR71XX_RESET_REG_REV_ID 0x90
406
407 #define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18
408 #define AR91XX_RESET_REG_RESET_MODULE 0x1c
409 #define AR91XX_RESET_REG_PERF_CTRL 0x20
410 #define AR91XX_RESET_REG_PERFC0 0x24
411 #define AR91XX_RESET_REG_PERFC1 0x28
412
413 #define AR724X_RESET_REG_RESET_MODULE 0x1c
414
415 #define WDOG_CTRL_LAST_RESET BIT(31)
416 #define WDOG_CTRL_ACTION_MASK 3
417 #define WDOG_CTRL_ACTION_NONE 0 /* no action */
418 #define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
419 #define WDOG_CTRL_ACTION_NMI 2 /* NMI */
420 #define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
421
422 #define MISC_INT_DMA BIT(7)
423 #define MISC_INT_OHCI BIT(6)
424 #define MISC_INT_PERFC BIT(5)
425 #define MISC_INT_WDOG BIT(4)
426 #define MISC_INT_UART BIT(3)
427 #define MISC_INT_GPIO BIT(2)
428 #define MISC_INT_ERROR BIT(1)
429 #define MISC_INT_TIMER BIT(0)
430
431 #define PCI_INT_CORE BIT(4)
432 #define PCI_INT_DEV2 BIT(2)
433 #define PCI_INT_DEV1 BIT(1)
434 #define PCI_INT_DEV0 BIT(0)
435
436 #define RESET_MODULE_EXTERNAL BIT(28)
437 #define RESET_MODULE_FULL_CHIP BIT(24)
438 #define RESET_MODULE_AMBA2WMAC BIT(22)
439 #define RESET_MODULE_CPU_NMI BIT(21)
440 #define RESET_MODULE_CPU_COLD BIT(20)
441 #define RESET_MODULE_DMA BIT(19)
442 #define RESET_MODULE_SLIC BIT(18)
443 #define RESET_MODULE_STEREO BIT(17)
444 #define RESET_MODULE_DDR BIT(16)
445 #define RESET_MODULE_GE1_MAC BIT(13)
446 #define RESET_MODULE_GE1_PHY BIT(12)
447 #define RESET_MODULE_USBSUS_OVERRIDE BIT(10)
448 #define RESET_MODULE_GE0_MAC BIT(9)
449 #define RESET_MODULE_GE0_PHY BIT(8)
450 #define RESET_MODULE_USB_OHCI_DLL BIT(6)
451 #define RESET_MODULE_USB_HOST BIT(5)
452 #define RESET_MODULE_USB_PHY BIT(4)
453 #define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3)
454 #define RESET_MODULE_PCI_BUS BIT(1)
455 #define RESET_MODULE_PCI_CORE BIT(0)
456
457 #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
458 #define AR724X_RESET_PCIE_PHY BIT(7)
459 #define AR724X_RESET_PCIE BIT(6)
460
461 #define REV_ID_MAJOR_MASK 0xf0
462 #define REV_ID_MAJOR_AR71XX 0xa0
463 #define REV_ID_MAJOR_AR913X 0xb0
464 #define REV_ID_MAJOR_AR724X 0xc0
465
466 #define AR71XX_REV_ID_MINOR_MASK 0x3
467 #define AR71XX_REV_ID_MINOR_AR7130 0x0
468 #define AR71XX_REV_ID_MINOR_AR7141 0x1
469 #define AR71XX_REV_ID_MINOR_AR7161 0x2
470 #define AR71XX_REV_ID_REVISION_MASK 0x3
471 #define AR71XX_REV_ID_REVISION_SHIFT 2
472
473 #define AR91XX_REV_ID_MINOR_MASK 0x3
474 #define AR91XX_REV_ID_MINOR_AR9130 0x0
475 #define AR91XX_REV_ID_MINOR_AR9132 0x1
476 #define AR91XX_REV_ID_REVISION_MASK 0x3
477 #define AR91XX_REV_ID_REVISION_SHIFT 2
478
479 #define AR724X_REV_ID_REVISION_MASK 0x3
480
481 extern void __iomem *ar71xx_reset_base;
482
483 static inline void ar71xx_reset_wr(unsigned reg, u32 val)
484 {
485 __raw_writel(val, ar71xx_reset_base + reg);
486 }
487
488 static inline u32 ar71xx_reset_rr(unsigned reg)
489 {
490 return __raw_readl(ar71xx_reset_base + reg);
491 }
492
493 void ar71xx_device_stop(u32 mask);
494 void ar71xx_device_start(u32 mask);
495 int ar71xx_device_stopped(u32 mask);
496
497 /*
498 * SPI block
499 */
500 #define SPI_REG_FS 0x00 /* Function Select */
501 #define SPI_REG_CTRL 0x04 /* SPI Control */
502 #define SPI_REG_IOC 0x08 /* SPI I/O Control */
503 #define SPI_REG_RDS 0x0c /* Read Data Shift */
504
505 #define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
506
507 #define SPI_CTRL_RD BIT(6) /* Remap Disable */
508 #define SPI_CTRL_DIV_MASK 0x3f
509
510 #define SPI_IOC_DO BIT(0) /* Data Out pin */
511 #define SPI_IOC_CLK BIT(8) /* CLK pin */
512 #define SPI_IOC_CS(n) BIT(16 + (n))
513 #define SPI_IOC_CS0 SPI_IOC_CS(0)
514 #define SPI_IOC_CS1 SPI_IOC_CS(1)
515 #define SPI_IOC_CS2 SPI_IOC_CS(2)
516 #define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
517
518 void ar71xx_flash_acquire(void);
519 void ar71xx_flash_release(void);
520
521 /*
522 * MII_CTRL block
523 */
524 #define MII_REG_MII0_CTRL 0x00
525 #define MII_REG_MII1_CTRL 0x04
526
527 #define MII0_CTRL_IF_GMII 0
528 #define MII0_CTRL_IF_MII 1
529 #define MII0_CTRL_IF_RGMII 2
530 #define MII0_CTRL_IF_RMII 3
531
532 #define MII1_CTRL_IF_RGMII 0
533 #define MII1_CTRL_IF_RMII 1
534
535 #endif /* __ASSEMBLER__ */
536
537 #endif /* __ASM_MACH_AR71XX_H */