ar71xx: AR724[12] requires different USB setup
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / include / asm / mach-ar71xx / ar71xx.h
1 /*
2 * Atheros AR71xx SoC specific definitions
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __ASM_MACH_AR71XX_H
15 #define __ASM_MACH_AR71XX_H
16
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/bitops.h>
21
22 #ifndef __ASSEMBLER__
23
24 #define AR71XX_PCI_MEM_BASE 0x10000000
25 #define AR71XX_PCI_MEM_SIZE 0x08000000
26 #define AR71XX_APB_BASE 0x18000000
27 #define AR71XX_GE0_BASE 0x19000000
28 #define AR71XX_GE0_SIZE 0x01000000
29 #define AR71XX_GE1_BASE 0x1a000000
30 #define AR71XX_GE1_SIZE 0x01000000
31 #define AR71XX_EHCI_BASE 0x1b000000
32 #define AR71XX_EHCI_SIZE 0x01000000
33 #define AR71XX_OHCI_BASE 0x1c000000
34 #define AR71XX_OHCI_SIZE 0x01000000
35 #define AR7240_OHCI_BASE 0x1b000000
36 #define AR7240_OHCI_SIZE 0x01000000
37 #define AR71XX_SPI_BASE 0x1f000000
38 #define AR71XX_SPI_SIZE 0x01000000
39
40 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
41 #define AR71XX_DDR_CTRL_SIZE 0x10000
42 #define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000)
43 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
44 #define AR71XX_UART_SIZE 0x10000
45 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
46 #define AR71XX_USB_CTRL_SIZE 0x10000
47 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
48 #define AR71XX_GPIO_SIZE 0x10000
49 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
50 #define AR71XX_PLL_SIZE 0x10000
51 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
52 #define AR71XX_RESET_SIZE 0x10000
53 #define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
54 #define AR71XX_MII_SIZE 0x10000
55 #define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000)
56 #define AR71XX_SLIC_SIZE 0x10000
57 #define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000)
58 #define AR71XX_DMA_SIZE 0x10000
59 #define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
60 #define AR71XX_STEREO_SIZE 0x10000
61
62 #define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000)
63 #define AR724X_PCI_CRP_SIZE 0x100
64
65 #define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000)
66 #define AR724X_PCI_CTRL_SIZE 0x100
67
68 #define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000)
69 #define AR91XX_WMAC_SIZE 0x30000
70
71 #define AR71XX_MEM_SIZE_MIN 0x0200000
72 #define AR71XX_MEM_SIZE_MAX 0x10000000
73
74 #define AR71XX_CPU_IRQ_BASE 0
75 #define AR71XX_MISC_IRQ_BASE 8
76 #define AR71XX_MISC_IRQ_COUNT 8
77 #define AR71XX_GPIO_IRQ_BASE 16
78 #define AR71XX_GPIO_IRQ_COUNT 32
79 #define AR71XX_PCI_IRQ_BASE 48
80 #define AR71XX_PCI_IRQ_COUNT 8
81
82 #define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2)
83 #define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
84 #define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
85 #define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
86 #define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6)
87 #define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7)
88
89 #define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0)
90 #define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1)
91 #define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2)
92 #define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3)
93 #define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4)
94 #define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
95 #define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
96 #define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
97
98 #define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
99
100 #define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0)
101 #define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1)
102 #define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
103 #define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4)
104
105 extern u32 ar71xx_ahb_freq;
106 extern u32 ar71xx_cpu_freq;
107 extern u32 ar71xx_ddr_freq;
108
109 enum ar71xx_soc_type {
110 AR71XX_SOC_UNKNOWN,
111 AR71XX_SOC_AR7130,
112 AR71XX_SOC_AR7141,
113 AR71XX_SOC_AR7161,
114 AR71XX_SOC_AR7240,
115 AR71XX_SOC_AR7241,
116 AR71XX_SOC_AR7242,
117 AR71XX_SOC_AR9130,
118 AR71XX_SOC_AR9132
119 };
120
121 extern enum ar71xx_soc_type ar71xx_soc;
122
123 /*
124 * PLL block
125 */
126 #define AR71XX_PLL_REG_CPU_CONFIG 0x00
127 #define AR71XX_PLL_REG_SEC_CONFIG 0x04
128 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
129 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
130
131 #define AR71XX_PLL_DIV_SHIFT 3
132 #define AR71XX_PLL_DIV_MASK 0x1f
133 #define AR71XX_CPU_DIV_SHIFT 16
134 #define AR71XX_CPU_DIV_MASK 0x3
135 #define AR71XX_DDR_DIV_SHIFT 18
136 #define AR71XX_DDR_DIV_MASK 0x3
137 #define AR71XX_AHB_DIV_SHIFT 20
138 #define AR71XX_AHB_DIV_MASK 0x7
139
140 #define AR71XX_ETH0_PLL_SHIFT 17
141 #define AR71XX_ETH1_PLL_SHIFT 19
142
143 #define AR724X_PLL_REG_CPU_CONFIG 0x00
144 #define AR724X_PLL_REG_PCIE_CONFIG 0x18
145
146 #define AR724X_PLL_DIV_SHIFT 0
147 #define AR724X_PLL_DIV_MASK 0x3ff
148 #define AR724X_PLL_REF_DIV_SHIFT 10
149 #define AR724X_PLL_REF_DIV_MASK 0xf
150 #define AR724X_AHB_DIV_SHIFT 19
151 #define AR724X_AHB_DIV_MASK 0x1
152 #define AR724X_DDR_DIV_SHIFT 22
153 #define AR724X_DDR_DIV_MASK 0x3
154
155 #define AR91XX_PLL_REG_CPU_CONFIG 0x00
156 #define AR91XX_PLL_REG_ETH_CONFIG 0x04
157 #define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
158 #define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
159
160 #define AR91XX_PLL_DIV_SHIFT 0
161 #define AR91XX_PLL_DIV_MASK 0x3ff
162 #define AR91XX_DDR_DIV_SHIFT 22
163 #define AR91XX_DDR_DIV_MASK 0x3
164 #define AR91XX_AHB_DIV_SHIFT 19
165 #define AR91XX_AHB_DIV_MASK 0x1
166
167 #define AR91XX_ETH0_PLL_SHIFT 20
168 #define AR91XX_ETH1_PLL_SHIFT 22
169
170 extern void __iomem *ar71xx_pll_base;
171
172 static inline void ar71xx_pll_wr(unsigned reg, u32 val)
173 {
174 __raw_writel(val, ar71xx_pll_base + reg);
175 }
176
177 static inline u32 ar71xx_pll_rr(unsigned reg)
178 {
179 return __raw_readl(ar71xx_pll_base + reg);
180 }
181
182 /*
183 * USB_CONFIG block
184 */
185 #define USB_CTRL_REG_FLADJ 0x00
186 #define USB_CTRL_REG_CONFIG 0x04
187
188 extern void __iomem *ar71xx_usb_ctrl_base;
189
190 static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
191 {
192 __raw_writel(val, ar71xx_usb_ctrl_base + reg);
193 }
194
195 static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
196 {
197 return __raw_readl(ar71xx_usb_ctrl_base + reg);
198 }
199
200 /*
201 * GPIO block
202 */
203 #define GPIO_REG_OE 0x00
204 #define GPIO_REG_IN 0x04
205 #define GPIO_REG_OUT 0x08
206 #define GPIO_REG_SET 0x0c
207 #define GPIO_REG_CLEAR 0x10
208 #define GPIO_REG_INT_MODE 0x14
209 #define GPIO_REG_INT_TYPE 0x18
210 #define GPIO_REG_INT_POLARITY 0x1c
211 #define GPIO_REG_INT_PENDING 0x20
212 #define GPIO_REG_INT_ENABLE 0x24
213 #define GPIO_REG_FUNC 0x28
214
215 #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
216 #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
217 #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
218 #define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
219 #define AR71XX_GPIO_FUNC_UART_EN BIT(8)
220 #define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
221 #define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
222
223 #define AR71XX_GPIO_COUNT 16
224
225 #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
226 #define AR724X_GPIO_FUNC_SPI_EN BIT(18)
227 #define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
228 #define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
229 #define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
230 #define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
231 #define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
232 #define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
233 #define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
234 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
235 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
236 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
237 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
238 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
239 #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
240 #define AR724X_GPIO_FUNC_UART_EN BIT(1)
241 #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
242
243 #define AR724X_GPIO_COUNT 18
244
245 #define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22)
246 #define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
247 #define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20)
248 #define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19)
249 #define AR91XX_GPIO_FUNC_I2S1_EN BIT(18)
250 #define AR91XX_GPIO_FUNC_I2S0_EN BIT(17)
251 #define AR91XX_GPIO_FUNC_SLIC_EN BIT(16)
252 #define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
253 #define AR91XX_GPIO_FUNC_UART_EN BIT(8)
254 #define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4)
255
256 #define AR91XX_GPIO_COUNT 22
257
258 extern void __iomem *ar71xx_gpio_base;
259
260 static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
261 {
262 __raw_writel(value, ar71xx_gpio_base + reg);
263 }
264
265 static inline u32 ar71xx_gpio_rr(unsigned reg)
266 {
267 return __raw_readl(ar71xx_gpio_base + reg);
268 }
269
270 void ar71xx_gpio_init(void) __init;
271 void ar71xx_gpio_function_enable(u32 mask);
272 void ar71xx_gpio_function_disable(u32 mask);
273 void ar71xx_gpio_function_setup(u32 set, u32 clear);
274
275 /*
276 * DDR_CTRL block
277 */
278 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
279 #define AR71XX_DDR_REG_PCI_WIN1 0x80
280 #define AR71XX_DDR_REG_PCI_WIN2 0x84
281 #define AR71XX_DDR_REG_PCI_WIN3 0x88
282 #define AR71XX_DDR_REG_PCI_WIN4 0x8c
283 #define AR71XX_DDR_REG_PCI_WIN5 0x90
284 #define AR71XX_DDR_REG_PCI_WIN6 0x94
285 #define AR71XX_DDR_REG_PCI_WIN7 0x98
286 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c
287 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0
288 #define AR71XX_DDR_REG_FLUSH_USB 0xa4
289 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8
290
291 #define AR724X_DDR_REG_FLUSH_GE0 0x7c
292 #define AR724X_DDR_REG_FLUSH_GE1 0x80
293 #define AR724X_DDR_REG_FLUSH_USB 0x84
294 #define AR724X_DDR_REG_FLUSH_PCIE 0x88
295
296 #define AR91XX_DDR_REG_FLUSH_GE0 0x7c
297 #define AR91XX_DDR_REG_FLUSH_GE1 0x80
298 #define AR91XX_DDR_REG_FLUSH_USB 0x84
299 #define AR91XX_DDR_REG_FLUSH_WMAC 0x88
300
301 #define PCI_WIN0_OFFS 0x10000000
302 #define PCI_WIN1_OFFS 0x11000000
303 #define PCI_WIN2_OFFS 0x12000000
304 #define PCI_WIN3_OFFS 0x13000000
305 #define PCI_WIN4_OFFS 0x14000000
306 #define PCI_WIN5_OFFS 0x15000000
307 #define PCI_WIN6_OFFS 0x16000000
308 #define PCI_WIN7_OFFS 0x07000000
309
310 extern void __iomem *ar71xx_ddr_base;
311
312 static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
313 {
314 __raw_writel(val, ar71xx_ddr_base + reg);
315 }
316
317 static inline u32 ar71xx_ddr_rr(unsigned reg)
318 {
319 return __raw_readl(ar71xx_ddr_base + reg);
320 }
321
322 void ar71xx_ddr_flush(u32 reg);
323
324 /*
325 * PCI block
326 */
327 #define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
328 #define AR71XX_PCI_CFG_SIZE 0x100
329
330 #define PCI_REG_CRP_AD_CBE 0x00
331 #define PCI_REG_CRP_WRDATA 0x04
332 #define PCI_REG_CRP_RDDATA 0x08
333 #define PCI_REG_CFG_AD 0x0c
334 #define PCI_REG_CFG_CBE 0x10
335 #define PCI_REG_CFG_WRDATA 0x14
336 #define PCI_REG_CFG_RDDATA 0x18
337 #define PCI_REG_PCI_ERR 0x1c
338 #define PCI_REG_PCI_ERR_ADDR 0x20
339 #define PCI_REG_AHB_ERR 0x24
340 #define PCI_REG_AHB_ERR_ADDR 0x28
341
342 #define PCI_CRP_CMD_WRITE 0x00010000
343 #define PCI_CRP_CMD_READ 0x00000000
344 #define PCI_CFG_CMD_READ 0x0000000a
345 #define PCI_CFG_CMD_WRITE 0x0000000b
346
347 #define PCI_IDSEL_ADL_START 17
348
349 #define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000)
350 #define AR724X_PCI_CFG_SIZE 0x1000
351
352 #define AR724X_PCI_REG_APP 0x00
353 #define AR724X_PCI_REG_RESET 0x18
354 #define AR724X_PCI_REG_INT_STATUS 0x4c
355 #define AR724X_PCI_REG_INT_MASK 0x50
356
357 #define AR724X_PCI_APP_LTSSM_ENABLE BIT(0)
358 #define AR724X_PCI_RESET_LINK_UP BIT(0)
359
360 #define AR724X_PCI_INT_DEV0 BIT(14)
361
362 /*
363 * RESET block
364 */
365 #define AR71XX_RESET_REG_TIMER 0x00
366 #define AR71XX_RESET_REG_TIMER_RELOAD 0x04
367 #define AR71XX_RESET_REG_WDOG_CTRL 0x08
368 #define AR71XX_RESET_REG_WDOG 0x0c
369 #define AR71XX_RESET_REG_MISC_INT_STATUS 0x10
370 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14
371 #define AR71XX_RESET_REG_PCI_INT_STATUS 0x18
372 #define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c
373 #define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20
374 #define AR71XX_RESET_REG_RESET_MODULE 0x24
375 #define AR71XX_RESET_REG_PERFC_CTRL 0x2c
376 #define AR71XX_RESET_REG_PERFC0 0x30
377 #define AR71XX_RESET_REG_PERFC1 0x34
378 #define AR71XX_RESET_REG_REV_ID 0x90
379
380 #define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18
381 #define AR91XX_RESET_REG_RESET_MODULE 0x1c
382 #define AR91XX_RESET_REG_PERF_CTRL 0x20
383 #define AR91XX_RESET_REG_PERFC0 0x24
384 #define AR91XX_RESET_REG_PERFC1 0x28
385
386 #define AR724X_RESET_REG_RESET_MODULE 0x1c
387
388 #define WDOG_CTRL_LAST_RESET BIT(31)
389 #define WDOG_CTRL_ACTION_MASK 3
390 #define WDOG_CTRL_ACTION_NONE 0 /* no action */
391 #define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
392 #define WDOG_CTRL_ACTION_NMI 2 /* NMI */
393 #define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
394
395 #define MISC_INT_DMA BIT(7)
396 #define MISC_INT_OHCI BIT(6)
397 #define MISC_INT_PERFC BIT(5)
398 #define MISC_INT_WDOG BIT(4)
399 #define MISC_INT_UART BIT(3)
400 #define MISC_INT_GPIO BIT(2)
401 #define MISC_INT_ERROR BIT(1)
402 #define MISC_INT_TIMER BIT(0)
403
404 #define PCI_INT_CORE BIT(4)
405 #define PCI_INT_DEV2 BIT(2)
406 #define PCI_INT_DEV1 BIT(1)
407 #define PCI_INT_DEV0 BIT(0)
408
409 #define RESET_MODULE_EXTERNAL BIT(28)
410 #define RESET_MODULE_FULL_CHIP BIT(24)
411 #define RESET_MODULE_AMBA2WMAC BIT(22)
412 #define RESET_MODULE_CPU_NMI BIT(21)
413 #define RESET_MODULE_CPU_COLD BIT(20)
414 #define RESET_MODULE_DMA BIT(19)
415 #define RESET_MODULE_SLIC BIT(18)
416 #define RESET_MODULE_STEREO BIT(17)
417 #define RESET_MODULE_DDR BIT(16)
418 #define RESET_MODULE_GE1_MAC BIT(13)
419 #define RESET_MODULE_GE1_PHY BIT(12)
420 #define RESET_MODULE_USBSUS_OVERRIDE BIT(10)
421 #define RESET_MODULE_GE0_MAC BIT(9)
422 #define RESET_MODULE_GE0_PHY BIT(8)
423 #define RESET_MODULE_USB_OHCI_DLL BIT(6)
424 #define RESET_MODULE_USB_HOST BIT(5)
425 #define RESET_MODULE_USB_PHY BIT(4)
426 #define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3)
427 #define RESET_MODULE_PCI_BUS BIT(1)
428 #define RESET_MODULE_PCI_CORE BIT(0)
429
430 #define AR724X_RESET_GE1_MDIO BIT(23)
431 #define AR724X_RESET_GE0_MDIO BIT(22)
432 #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
433 #define AR724X_RESET_PCIE_PHY BIT(7)
434 #define AR724X_RESET_PCIE BIT(6)
435 #define AR724X_RESET_USB_HOST BIT(5)
436 #define AR724X_RESET_USB_PHY BIT(4)
437 #define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
438
439 #define REV_ID_MAJOR_MASK 0xfff0
440 #define REV_ID_MAJOR_AR71XX 0x00a0
441 #define REV_ID_MAJOR_AR913X 0x00b0
442 #define REV_ID_MAJOR_AR7240 0x00c0
443 #define REV_ID_MAJOR_AR7241 0x0100
444 #define REV_ID_MAJOR_AR7242 0x1100
445
446 #define AR71XX_REV_ID_MINOR_MASK 0x3
447 #define AR71XX_REV_ID_MINOR_AR7130 0x0
448 #define AR71XX_REV_ID_MINOR_AR7141 0x1
449 #define AR71XX_REV_ID_MINOR_AR7161 0x2
450 #define AR71XX_REV_ID_REVISION_MASK 0x3
451 #define AR71XX_REV_ID_REVISION_SHIFT 2
452
453 #define AR91XX_REV_ID_MINOR_MASK 0x3
454 #define AR91XX_REV_ID_MINOR_AR9130 0x0
455 #define AR91XX_REV_ID_MINOR_AR9132 0x1
456 #define AR91XX_REV_ID_REVISION_MASK 0x3
457 #define AR91XX_REV_ID_REVISION_SHIFT 2
458
459 #define AR724X_REV_ID_REVISION_MASK 0x3
460
461 extern void __iomem *ar71xx_reset_base;
462
463 static inline void ar71xx_reset_wr(unsigned reg, u32 val)
464 {
465 __raw_writel(val, ar71xx_reset_base + reg);
466 }
467
468 static inline u32 ar71xx_reset_rr(unsigned reg)
469 {
470 return __raw_readl(ar71xx_reset_base + reg);
471 }
472
473 void ar71xx_device_stop(u32 mask);
474 void ar71xx_device_start(u32 mask);
475 int ar71xx_device_stopped(u32 mask);
476
477 /*
478 * SPI block
479 */
480 #define SPI_REG_FS 0x00 /* Function Select */
481 #define SPI_REG_CTRL 0x04 /* SPI Control */
482 #define SPI_REG_IOC 0x08 /* SPI I/O Control */
483 #define SPI_REG_RDS 0x0c /* Read Data Shift */
484
485 #define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
486
487 #define SPI_CTRL_RD BIT(6) /* Remap Disable */
488 #define SPI_CTRL_DIV_MASK 0x3f
489
490 #define SPI_IOC_DO BIT(0) /* Data Out pin */
491 #define SPI_IOC_CLK BIT(8) /* CLK pin */
492 #define SPI_IOC_CS(n) BIT(16 + (n))
493 #define SPI_IOC_CS0 SPI_IOC_CS(0)
494 #define SPI_IOC_CS1 SPI_IOC_CS(1)
495 #define SPI_IOC_CS2 SPI_IOC_CS(2)
496 #define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
497
498 void ar71xx_flash_acquire(void);
499 void ar71xx_flash_release(void);
500
501 /*
502 * MII_CTRL block
503 */
504 #define MII_REG_MII0_CTRL 0x00
505 #define MII_REG_MII1_CTRL 0x04
506
507 #define MII0_CTRL_IF_GMII 0
508 #define MII0_CTRL_IF_MII 1
509 #define MII0_CTRL_IF_RGMII 2
510 #define MII0_CTRL_IF_RMII 3
511
512 #define MII1_CTRL_IF_RGMII 0
513 #define MII1_CTRL_IF_RMII 1
514
515 #endif /* __ASSEMBLER__ */
516
517 #endif /* __ASM_MACH_AR71XX_H */