surprise :p
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / pci / pci-ar71xx.c
1 /*
2 * Atheros AR71xx PCI host controller driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/resource.h>
15 #include <linux/types.h>
16 #include <linux/delay.h>
17 #include <linux/bitops.h>
18 #include <linux/pci.h>
19 #include <linux/pci_regs.h>
20
21 #include <asm/mach-ar71xx/ar71xx.h>
22 #include <asm/mach-ar71xx/pci.h>
23
24 #undef DEBUG
25 #ifdef DEBUG
26 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
27 #else
28 #define DBG(fmt, args...)
29 #endif
30
31 #define AR71XX_PCI_DELAY 100 /* msecs */
32
33 #if 0
34 #define PCI_IDSEL_BASE PCI_IDSEL_ADL_START
35 #else
36 #define PCI_IDSEL_BASE 0
37 #endif
38
39 static unsigned ar71xx_pci_nr_irqs;
40 static struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata;
41 static void __iomem *ar71xx_pcicfg_base;
42
43 static DEFINE_SPINLOCK(ar71xx_pci_lock);
44
45 static inline void ar71xx_pci_delay(void)
46 {
47 mdelay(AR71XX_PCI_DELAY);
48 }
49
50 static inline u32 ar71xx_pcicfg_rr(unsigned int reg)
51 {
52 return __raw_readl(ar71xx_pcicfg_base + reg);
53 }
54
55 static inline void ar71xx_pcicfg_wr(unsigned int reg, u32 val)
56 {
57 __raw_writel(val, ar71xx_pcicfg_base + reg);
58 }
59
60 /* Byte lane enable bits */
61 static u8 ble_table[4][4] = {
62 {0xf, 0xe, 0xd, 0xc},
63 {0xc, 0x9, 0x3, 0x1},
64 {0x0, 0x0, 0x0, 0x0},
65 {0x0, 0x0, 0x0, 0x0},
66 };
67
68 static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
69 {
70 u32 t;
71
72 t = ble_table[size][where & 3];
73 t <<= (local) ? 20 : 4;
74 return t;
75 }
76
77 static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
78 int where)
79 {
80 u32 ret;
81
82 if (!bus->number) {
83 /* type 0 */
84 ret = (1 << (PCI_IDSEL_BASE + PCI_SLOT(devfn)))
85 | (PCI_FUNC(devfn) << 8) | (where & ~3);
86 } else {
87 /* type 1 */
88 ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11)
89 | (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
90 }
91
92 return ret;
93 }
94
95 static int __ar71xx_pci_be_handler(int is_fixup)
96 {
97 u32 pci_err;
98 u32 ahb_err;
99
100 pci_err = ar71xx_pcicfg_rr(PCI_REG_PCI_ERR) & 3;
101 if (pci_err) {
102 if (!is_fixup)
103 printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n",
104 pci_err,
105 ar71xx_pcicfg_rr(PCI_REG_PCI_ERR_ADDR));
106
107 ar71xx_pcicfg_wr(PCI_REG_PCI_ERR, pci_err);
108 }
109
110 ahb_err = ar71xx_pcicfg_rr(PCI_REG_AHB_ERR) & 1;
111 if (ahb_err) {
112 if (!is_fixup)
113 printk(KERN_ALERT "AHB error at AHB address 0x%x\n",
114 ar71xx_pcicfg_rr(PCI_REG_AHB_ERR_ADDR));
115
116 ar71xx_pcicfg_wr(PCI_REG_AHB_ERR, ahb_err);
117 }
118
119 return ((ahb_err | pci_err) ? 1 : 0);
120 }
121
122 static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
123 unsigned int devfn, int where, int size, u32 cmd)
124 {
125 u32 addr;
126
127 addr = ar71xx_pci_bus_addr(bus, devfn, where);
128
129 DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n",
130 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
131 where, size, addr);
132
133 ar71xx_pcicfg_wr(PCI_REG_CFG_AD, addr);
134 ar71xx_pcicfg_wr(PCI_REG_CFG_CBE,
135 cmd | ar71xx_pci_get_ble(where, size, 0));
136
137 return __ar71xx_pci_be_handler(1);
138 }
139
140 static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
141 int where, int size, u32 *value)
142 {
143 static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
144 unsigned long flags;
145 u32 data;
146 int ret;
147
148 ret = PCIBIOS_SUCCESSFUL;
149
150 DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number,
151 PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
152
153 spin_lock_irqsave(&ar71xx_pci_lock, flags);
154
155 if (bus->number == 0 && devfn == 0) {
156 u32 t;
157
158 t = PCI_CRP_CMD_READ | (where & ~3);
159
160 ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
161 data = ar71xx_pcicfg_rr(PCI_REG_CRP_RDDATA);
162
163 DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data);
164
165 } else {
166 int err;
167
168 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
169 PCI_CFG_CMD_READ);
170
171 if (err == 0) {
172 data = ar71xx_pcicfg_rr(PCI_REG_CFG_RDDATA);
173 } else {
174 ret = PCIBIOS_DEVICE_NOT_FOUND;
175 data = ~0;
176 }
177 }
178
179 spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
180
181 DBG("PCI: read config: data=%08x raw=%08x\n",
182 (data >> (8 * (where & 3))) & mask[size & 7], data);
183
184 *value = (data >> (8 * (where & 3))) & mask[size & 7];
185
186 return ret;
187 }
188
189 static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
190 int where, int size, u32 value)
191 {
192 unsigned long flags;
193 int ret;
194
195 DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n",
196 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
197 where, size, value);
198
199 value = value << (8 * (where & 3));
200 ret = PCIBIOS_SUCCESSFUL;
201
202 spin_lock_irqsave(&ar71xx_pci_lock, flags);
203 if (bus->number == 0 && devfn == 0) {
204 u32 t;
205
206 t = PCI_CRP_CMD_WRITE | (where & ~3);
207 t |= ar71xx_pci_get_ble(where, size, 1);
208
209 DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value);
210
211 ar71xx_pcicfg_wr(PCI_REG_CRP_AD_CBE, t);
212 ar71xx_pcicfg_wr(PCI_REG_CRP_WRDATA, value);
213 } else {
214 int err;
215
216 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
217 PCI_CFG_CMD_WRITE);
218
219 if (err == 0)
220 ar71xx_pcicfg_wr(PCI_REG_CFG_WRDATA, value);
221 else
222 ret = PCIBIOS_DEVICE_NOT_FOUND;
223 }
224 spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
225
226 return ret;
227 }
228
229 static void ar71xx_pci_fixup(struct pci_dev *dev)
230 {
231 u32 t;
232
233 if (dev->bus->number != 0 || dev->devfn != 0)
234 return;
235
236 DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev),
237 dev->vendor, dev->device);
238
239 /* setup COMMAND register */
240 t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
241 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
242
243 pci_write_config_word(dev, PCI_COMMAND, t);
244 }
245
246 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup);
247
248 int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
249 {
250 int irq = -1;
251 int i;
252
253 slot -= PCI_IDSEL_ADL_START - PCI_IDSEL_BASE;
254
255 for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
256 struct ar71xx_pci_irq *entry;
257
258 entry = &ar71xx_pci_irq_map[i];
259 if (entry->slot == slot && entry->pin == pin) {
260 irq = entry->irq;
261 break;
262 }
263 }
264
265 if (irq < 0) {
266 printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
267 pin, pci_name((struct pci_dev *)dev));
268 } else {
269 printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
270 irq, pin, pci_name((struct pci_dev *)dev));
271 }
272
273 return irq;
274 }
275
276 int pcibios_plat_dev_init(struct pci_dev *dev)
277 {
278 return 0;
279 }
280
281 static struct pci_ops ar71xx_pci_ops = {
282 .read = ar71xx_pci_read_config,
283 .write = ar71xx_pci_write_config,
284 };
285
286 static struct resource ar71xx_pci_io_resource = {
287 .name = "PCI IO space",
288 .start = 0,
289 .end = 0,
290 .flags = IORESOURCE_IO,
291 };
292
293 static struct resource ar71xx_pci_mem_resource = {
294 .name = "PCI memory space",
295 .start = AR71XX_PCI_MEM_BASE,
296 .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
297 .flags = IORESOURCE_MEM
298 };
299
300 static struct pci_controller ar71xx_pci_controller = {
301 .pci_ops = &ar71xx_pci_ops,
302 .mem_resource = &ar71xx_pci_mem_resource,
303 .io_resource = &ar71xx_pci_io_resource,
304 };
305
306 static int __init __ar71xx_pci_bios_init(unsigned nr_irqs,
307 struct ar71xx_pci_irq *map)
308 {
309 ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
310 ar71xx_pci_delay();
311
312 ar71xx_device_start(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
313 ar71xx_pci_delay();
314
315 ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
316 AR71XX_PCI_CFG_SIZE);
317
318 ar71xx_ddr_wr(DDR_REG_PCI_WIN0, PCI_WIN0_OFFS);
319 ar71xx_ddr_wr(DDR_REG_PCI_WIN1, PCI_WIN1_OFFS);
320 ar71xx_ddr_wr(DDR_REG_PCI_WIN2, PCI_WIN2_OFFS);
321 ar71xx_ddr_wr(DDR_REG_PCI_WIN3, PCI_WIN3_OFFS);
322 ar71xx_ddr_wr(DDR_REG_PCI_WIN4, PCI_WIN4_OFFS);
323 ar71xx_ddr_wr(DDR_REG_PCI_WIN5, PCI_WIN5_OFFS);
324 ar71xx_ddr_wr(DDR_REG_PCI_WIN6, PCI_WIN6_OFFS);
325 ar71xx_ddr_wr(DDR_REG_PCI_WIN7, PCI_WIN7_OFFS);
326
327 ar71xx_pci_delay();
328
329 /* clear bus errors */
330 (void)__ar71xx_pci_be_handler(1);
331
332 ar71xx_pci_nr_irqs = nr_irqs;
333 ar71xx_pci_irq_map = map;
334 ar71xx_pci_be_handler = __ar71xx_pci_be_handler;
335
336 register_pci_controller(&ar71xx_pci_controller);
337
338 return 0;
339 }
340
341 static int __init __ar71xx_pci_init(void)
342 {
343 ar71xx_pci_bios_init = __ar71xx_pci_bios_init;
344 return 0;
345 }
346 pure_initcall(__ar71xx_pci_init);