target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c

   1 /*
   2  *  Atheros AR724x PCI host controller driver
   3  *
   4  *  Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  Parts of this file are based on Atheros' 2.6.15 BSP
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License version 2 as published
  10  *  by the Free Software Foundation.
  11  */
  12
  13 #include <linux/resource.h>
  14 #include <linux/types.h>
  15 #include <linux/delay.h>
  16 #include <linux/bitops.h>
  17 #include <linux/pci.h>
  18 #include <linux/pci_regs.h>
  19 #include <linux/interrupt.h>
  20
  21 #include <asm/mach-ar71xx/ar71xx.h>
  22 #include <asm/mach-ar71xx/pci.h>
  23
  24 #undef DEBUG
  25 #ifdef DEBUG
  26 #define DBG(fmt, args...)       printk(KERN_INFO fmt, ## args)
  27 #else
  28 #define DBG(fmt, args...)
  29 #endif
  30
  31 static void __iomem *ar724x_pci_localcfg_base;
  32 static void __iomem *ar724x_pci_devcfg_base;
  33 static void __iomem *ar724x_pci_ctrl_base;
  34 static int ar724x_pci_fixup_enable;
  35
  36 static DEFINE_SPINLOCK(ar724x_pci_lock);
  37
  38 static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value)
  39 {
  40         unsigned long flags;
  41         u32 data;
  42
  43         spin_lock_irqsave(&ar724x_pci_lock, flags);
  44         data = __raw_readl(base + (where & ~3));
  45
  46         switch (size) {
  47         case 1:
  48                 if (where & 1)
  49                         data >>= 8;
  50                 if (where & 2)
  51                         data >>= 16;
  52                 data &= 0xFF;
  53                 break;
  54         case 2:
  55                 if (where & 2)
  56                         data >>= 16;
  57                 data &= 0xFFFF;
  58                 break;
  59         }
  60
  61         *value = data;
  62         spin_unlock_irqrestore(&ar724x_pci_lock, flags);
  63 }
  64
  65 static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value)
  66 {
  67         unsigned long flags;
  68         u32 data;
  69         int s;
  70
  71         spin_lock_irqsave(&ar724x_pci_lock, flags);
  72         data = __raw_readl(base + (where & ~3));
  73
  74         switch (size) {
  75         case 1:
  76                 s = ((where & 3) << 3);
  77                 data &= ~(0xFF << s);
  78                 data |= ((value & 0xFF) << s);
  79                 break;
  80         case 2:
  81                 s = ((where & 2) << 3);
  82                 data &= ~(0xFFFF << s);
  83                 data |= ((value & 0xFFFF) << s);
  84                 break;
  85         case 4:
  86                 data = value;
  87                 break;
  88         }
  89
  90         __raw_writel(data, base + (where & ~3));
  91         /* flush write */
  92         (void)__raw_readl(base + (where & ~3));
  93         spin_unlock_irqrestore(&ar724x_pci_lock, flags);
  94 }
  95
  96 static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  97                                   int where, int size, u32 *value)
  98 {
  99
 100         if (bus->number != 0 || devfn != 0)
 101                 return PCIBIOS_DEVICE_NOT_FOUND;
 102
 103         ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value);
 104
 105         DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
 106                         bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 107                         where, size, *value);
 108
 109         /*
 110          * WAR for BAR issue - We are unable to access the PCI device space
 111          * if we set the BAR with proper base address
 112          */
 113         if ((where == 0x10) && (size == 4))
 114                 ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff);
 115
 116         return PCIBIOS_SUCCESSFUL;
 117 }
 118
 119 static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 120                                    int where, int size, u32 value)
 121 {
 122         if (bus->number != 0 || devfn != 0)
 123                 return PCIBIOS_DEVICE_NOT_FOUND;
 124
 125         DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
 126                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 127                 where, size, value);
 128
 129         ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value);
 130
 131         return PCIBIOS_SUCCESSFUL;
 132 }
 133
 134 static void ar724x_pci_fixup(struct pci_dev *dev)
 135 {
 136         u16 cmd;
 137
 138         if (!ar724x_pci_fixup_enable)
 139                 return;
 140
 141         if (dev->bus->number != 0 || dev->devfn != 0)
 142                 return;
 143
 144         /* setup COMMAND register */
 145         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 146         cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 147                PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
 148                PCI_COMMAND_FAST_BACK;
 149
 150         pci_write_config_word(dev, PCI_COMMAND, cmd);
 151 }
 152 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup);
 153
 154 int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
 155                                   uint8_t pin)
 156 {
 157         int irq = -1;
 158         int i;
 159
 160         for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
 161                 struct ar71xx_pci_irq *entry;
 162                 entry = &ar71xx_pci_irq_map[i];
 163
 164                 if (entry->slot == slot && entry->pin == pin) {
 165                         irq = entry->irq;
 166                         break;
 167                 }
 168         }
 169
 170         if (irq < 0)
 171                 printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
 172                                 pin, pci_name((struct pci_dev *)dev));
 173         else
 174                 printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
 175                                 irq, pin, pci_name((struct pci_dev *)dev));
 176
 177         return irq;
 178 }
 179
 180 static struct pci_ops ar724x_pci_ops = {
 181         .read   = ar724x_pci_read_config,
 182         .write  = ar724x_pci_write_config,
 183 };
 184
 185 static struct resource ar724x_pci_io_resource = {
 186         .name           = "PCI IO space",
 187         .start          = 0,
 188         .end            = 0,
 189         .flags          = IORESOURCE_IO,
 190 };
 191
 192 static struct resource ar724x_pci_mem_resource = {
 193         .name           = "PCI memory space",
 194         .start          = AR71XX_PCI_MEM_BASE,
 195         .end            = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
 196         .flags          = IORESOURCE_MEM
 197 };
 198
 199 static struct pci_controller ar724x_pci_controller = {
 200         .pci_ops        = &ar724x_pci_ops,
 201         .mem_resource   = &ar724x_pci_mem_resource,
 202         .io_resource    = &ar724x_pci_io_resource,
 203 };
 204
 205 static void __init ar724x_pci_reset(void)
 206 {
 207         ar71xx_device_stop(AR724X_RESET_PCIE);
 208         ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
 209         ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
 210         udelay(100);
 211
 212         ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
 213         udelay(100);
 214         ar71xx_device_start(AR724X_RESET_PCIE_PHY);
 215         ar71xx_device_start(AR724X_RESET_PCIE);
 216 }
 217
 218 static int __init ar724x_pci_setup(void)
 219 {
 220         void __iomem *base = ar724x_pci_ctrl_base;
 221         u32 t;
 222
 223         /* setup COMMAND register */
 224         t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
 225             PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
 226
 227         ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
 228         ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000);
 229         ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000);
 230
 231         t = __raw_readl(base + AR724X_PCI_REG_RESET);
 232         if (t != 0x7) {
 233                 udelay(100000);
 234                 __raw_writel(0, base + AR724X_PCI_REG_RESET);
 235                 udelay(100);
 236                 __raw_writel(4, base + AR724X_PCI_REG_RESET);
 237                 udelay(100000);
 238         }
 239
 240         __raw_writel(AR724X_PCI_APP_LTSSM_ENABLE, base + AR724X_PCI_REG_APP);
 241         /* flush write */
 242         (void) __raw_readl(base + AR724X_PCI_REG_APP);
 243         udelay(1000);
 244
 245         t = __raw_readl(base + AR724X_PCI_REG_RESET);
 246         if ((t & AR724X_PCI_RESET_LINK_UP) == 0x0) {
 247                 printk(KERN_WARNING "PCI: no PCIe module found\n");
 248                 return -ENODEV;
 249         }
 250
 251         return 0;
 252 }
 253
 254 static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 255 {
 256         void __iomem *base = ar724x_pci_ctrl_base;
 257         u32 pending;
 258
 259         pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
 260                   __raw_readl(base + AR724X_PCI_REG_INT_MASK);
 261
 262         if (pending & AR724X_PCI_INT_DEV0)
 263                 generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
 264
 265         else
 266                 spurious_interrupt();
 267 }
 268
 269 static void ar724x_pci_irq_unmask(unsigned int irq)
 270 {
 271         void __iomem *base = ar724x_pci_ctrl_base;
 272         u32 t;
 273
 274         switch (irq) {
 275         case AR71XX_PCI_IRQ_DEV0:
 276                 irq -= AR71XX_PCI_IRQ_BASE;
 277
 278                 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
 279                 __raw_writel(t | AR724X_PCI_INT_DEV0,
 280                              base + AR724X_PCI_REG_INT_MASK);
 281                 /* flush write */
 282                 (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK);
 283         }
 284 }
 285
 286 static void ar724x_pci_irq_mask(unsigned int irq)
 287 {
 288         void __iomem *base = ar724x_pci_ctrl_base;
 289         u32 t;
 290
 291         switch (irq) {
 292         case AR71XX_PCI_IRQ_DEV0:
 293                 irq -= AR71XX_PCI_IRQ_BASE;
 294
 295                 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
 296                 __raw_writel(t & ~AR724X_PCI_INT_DEV0,
 297                              base + AR724X_PCI_REG_INT_MASK);
 298
 299                 /* flush write */
 300                 (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK);
 301
 302                 t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
 303                 __raw_writel(t | AR724X_PCI_INT_DEV0,
 304                              base + AR724X_PCI_REG_INT_STATUS);
 305
 306                 /* flush write */
 307                 (void) __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
 308         }
 309 }
 310
 311 static struct irq_chip ar724x_pci_irq_chip = {
 312         .name           = "AR724X PCI ",
 313         .mask           = ar724x_pci_irq_mask,
 314         .unmask         = ar724x_pci_irq_unmask,
 315         .mask_ack       = ar724x_pci_irq_mask,
 316 };
 317
 318 static void __init ar724x_pci_irq_init(void)
 319 {
 320         void __iomem *base = ar724x_pci_ctrl_base;
 321         u32 t;
 322         int i;
 323
 324         t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
 325         if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY |
 326                  AR724X_RESET_PCIE_PHY_SERIAL)) {
 327                 return;
 328         }
 329
 330         __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
 331         __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
 332
 333         for (i = AR71XX_PCI_IRQ_BASE;
 334              i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
 335                 irq_desc[i].status = IRQ_DISABLED;
 336                 set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
 337                                          handle_level_irq);
 338         }
 339
 340         set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler);
 341 }
 342
 343 int __init ar724x_pcibios_init(void)
 344 {
 345         int ret = -ENOMEM;
 346
 347         ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE,
 348                                                    AR724X_PCI_CRP_SIZE);
 349         if (ar724x_pci_localcfg_base == NULL)
 350                 goto err;
 351
 352         ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE,
 353                                                  AR724X_PCI_CFG_SIZE);
 354         if (ar724x_pci_devcfg_base == NULL)
 355                 goto err_unmap_localcfg;
 356
 357         ar724x_pci_ctrl_base = ioremap_nocache(AR724X_PCI_CTRL_BASE,
 358                                                AR724X_PCI_CTRL_SIZE);
 359         if (ar724x_pci_ctrl_base == NULL)
 360                 goto err_unmap_devcfg;
 361
 362         ar724x_pci_reset();
 363         ret = ar724x_pci_setup();
 364         if (ret)
 365                 goto err_unmap_ctrl;
 366
 367         ar724x_pci_fixup_enable = 1;
 368         ar724x_pci_irq_init();
 369         register_pci_controller(&ar724x_pci_controller);
 370
 371         return 0;
 372
 373  err_unmap_ctrl:
 374         iounmap(ar724x_pci_ctrl_base);
 375   err_unmap_devcfg:
 376         iounmap(ar724x_pci_devcfg_base);
 377  err_unmap_localcfg:
 378         iounmap(ar724x_pci_localcfg_base);
 379  err:
 380         return ret;
 381 }