ar71xx: remove useless irq_desc.status initializations
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / pci / pci-ar724x.c
1 /*
2 * Atheros AR724x PCI host controller driver
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * Parts of this file are based on Atheros' 2.6.15 BSP
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13 #include <linux/resource.h>
14 #include <linux/types.h>
15 #include <linux/delay.h>
16 #include <linux/bitops.h>
17 #include <linux/pci.h>
18 #include <linux/pci_regs.h>
19 #include <linux/interrupt.h>
20
21 #include <asm/mach-ar71xx/ar71xx.h>
22 #include <asm/mach-ar71xx/pci.h>
23
24 #undef DEBUG
25 #ifdef DEBUG
26 #define DBG(fmt, args...) printk(KERN_INFO fmt, ## args)
27 #else
28 #define DBG(fmt, args...)
29 #endif
30
31 static void __iomem *ar724x_pci_localcfg_base;
32 static void __iomem *ar724x_pci_devcfg_base;
33 static void __iomem *ar724x_pci_ctrl_base;
34 static int ar724x_pci_fixup_enable;
35
36 static DEFINE_SPINLOCK(ar724x_pci_lock);
37
38 static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value)
39 {
40 unsigned long flags;
41 u32 data;
42
43 spin_lock_irqsave(&ar724x_pci_lock, flags);
44 data = __raw_readl(base + (where & ~3));
45
46 switch (size) {
47 case 1:
48 if (where & 1)
49 data >>= 8;
50 if (where & 2)
51 data >>= 16;
52 data &= 0xFF;
53 break;
54 case 2:
55 if (where & 2)
56 data >>= 16;
57 data &= 0xFFFF;
58 break;
59 }
60
61 *value = data;
62 spin_unlock_irqrestore(&ar724x_pci_lock, flags);
63 }
64
65 static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value)
66 {
67 unsigned long flags;
68 u32 data;
69 int s;
70
71 spin_lock_irqsave(&ar724x_pci_lock, flags);
72 data = __raw_readl(base + (where & ~3));
73
74 switch (size) {
75 case 1:
76 s = ((where & 3) << 3);
77 data &= ~(0xFF << s);
78 data |= ((value & 0xFF) << s);
79 break;
80 case 2:
81 s = ((where & 2) << 3);
82 data &= ~(0xFFFF << s);
83 data |= ((value & 0xFFFF) << s);
84 break;
85 case 4:
86 data = value;
87 break;
88 }
89
90 __raw_writel(data, base + (where & ~3));
91 /* flush write */
92 (void)__raw_readl(base + (where & ~3));
93 spin_unlock_irqrestore(&ar724x_pci_lock, flags);
94 }
95
96 static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn,
97 int where, int size, u32 *value)
98 {
99
100 if (bus->number != 0 || devfn != 0)
101 return PCIBIOS_DEVICE_NOT_FOUND;
102
103 ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value);
104
105 DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
106 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
107 where, size, *value);
108
109 /*
110 * WAR for BAR issue - We are unable to access the PCI device space
111 * if we set the BAR with proper base address
112 */
113 if ((where == 0x10) && (size == 4)) {
114 u32 val;
115 val = (ar71xx_soc == AR71XX_SOC_AR7240) ? 0xffff : 0x1000ffff;
116 ar724x_pci_write(ar724x_pci_devcfg_base, where, size, val);
117 }
118
119 return PCIBIOS_SUCCESSFUL;
120 }
121
122 static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn,
123 int where, int size, u32 value)
124 {
125 if (bus->number != 0 || devfn != 0)
126 return PCIBIOS_DEVICE_NOT_FOUND;
127
128 DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
129 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
130 where, size, value);
131
132 ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value);
133
134 return PCIBIOS_SUCCESSFUL;
135 }
136
137 static void ar724x_pci_fixup(struct pci_dev *dev)
138 {
139 u16 cmd;
140
141 if (!ar724x_pci_fixup_enable)
142 return;
143
144 if (dev->bus->number != 0 || dev->devfn != 0)
145 return;
146
147 /* setup COMMAND register */
148 pci_read_config_word(dev, PCI_COMMAND, &cmd);
149 cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
150 PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
151 PCI_COMMAND_FAST_BACK;
152
153 pci_write_config_word(dev, PCI_COMMAND, cmd);
154 }
155 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup);
156
157 int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
158 uint8_t pin)
159 {
160 int irq = -1;
161 int i;
162
163 for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
164 struct ar71xx_pci_irq *entry;
165 entry = &ar71xx_pci_irq_map[i];
166
167 if (entry->slot == slot && entry->pin == pin) {
168 irq = entry->irq;
169 break;
170 }
171 }
172
173 if (irq < 0)
174 printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
175 pin, pci_name((struct pci_dev *)dev));
176 else
177 printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
178 irq, pin, pci_name((struct pci_dev *)dev));
179
180 return irq;
181 }
182
183 static struct pci_ops ar724x_pci_ops = {
184 .read = ar724x_pci_read_config,
185 .write = ar724x_pci_write_config,
186 };
187
188 static struct resource ar724x_pci_io_resource = {
189 .name = "PCI IO space",
190 .start = 0,
191 .end = 0,
192 .flags = IORESOURCE_IO,
193 };
194
195 static struct resource ar724x_pci_mem_resource = {
196 .name = "PCI memory space",
197 .start = AR71XX_PCI_MEM_BASE,
198 .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
199 .flags = IORESOURCE_MEM
200 };
201
202 static struct pci_controller ar724x_pci_controller = {
203 .pci_ops = &ar724x_pci_ops,
204 .mem_resource = &ar724x_pci_mem_resource,
205 .io_resource = &ar724x_pci_io_resource,
206 };
207
208 static void __init ar724x_pci_reset(void)
209 {
210 ar71xx_device_stop(AR724X_RESET_PCIE);
211 ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
212 ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
213 udelay(100);
214
215 ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
216 udelay(100);
217 ar71xx_device_start(AR724X_RESET_PCIE_PHY);
218 ar71xx_device_start(AR724X_RESET_PCIE);
219 }
220
221 static int __init ar724x_pci_setup(void)
222 {
223 void __iomem *base = ar724x_pci_ctrl_base;
224 u32 t;
225
226 /* setup COMMAND register */
227 t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
228 PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
229
230 ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
231 ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000);
232 ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000);
233
234 t = __raw_readl(base + AR724X_PCI_REG_RESET);
235 if (t != 0x7) {
236 udelay(100000);
237 __raw_writel(0, base + AR724X_PCI_REG_RESET);
238 udelay(100);
239 __raw_writel(4, base + AR724X_PCI_REG_RESET);
240 udelay(100000);
241 }
242
243 if (ar71xx_soc == AR71XX_SOC_AR7240)
244 t = AR724X_PCI_APP_LTSSM_ENABLE;
245 else
246 t = 0x1ffc1;
247 __raw_writel(t, base + AR724X_PCI_REG_APP);
248 /* flush write */
249 (void) __raw_readl(base + AR724X_PCI_REG_APP);
250 udelay(1000);
251
252 t = __raw_readl(base + AR724X_PCI_REG_RESET);
253 if ((t & AR724X_PCI_RESET_LINK_UP) == 0x0) {
254 printk(KERN_WARNING "PCI: no PCIe module found\n");
255 return -ENODEV;
256 }
257
258 if (ar71xx_soc == AR71XX_SOC_AR7241 ||
259 ar71xx_soc == AR71XX_SOC_AR7242) {
260 t = __raw_readl(base + AR724X_PCI_REG_APP);
261 t |= BIT(16);
262 __raw_writel(t, base + AR724X_PCI_REG_APP);
263 }
264
265 return 0;
266 }
267
268 static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
269 {
270 void __iomem *base = ar724x_pci_ctrl_base;
271 u32 pending;
272
273 pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) &
274 __raw_readl(base + AR724X_PCI_REG_INT_MASK);
275
276 if (pending & AR724X_PCI_INT_DEV0)
277 generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
278
279 else
280 spurious_interrupt();
281 }
282
283 static void ar724x_pci_irq_unmask(unsigned int irq)
284 {
285 void __iomem *base = ar724x_pci_ctrl_base;
286 u32 t;
287
288 switch (irq) {
289 case AR71XX_PCI_IRQ_DEV0:
290 irq -= AR71XX_PCI_IRQ_BASE;
291
292 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
293 __raw_writel(t | AR724X_PCI_INT_DEV0,
294 base + AR724X_PCI_REG_INT_MASK);
295 /* flush write */
296 (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK);
297 }
298 }
299
300 static void ar724x_pci_irq_mask(unsigned int irq)
301 {
302 void __iomem *base = ar724x_pci_ctrl_base;
303 u32 t;
304
305 switch (irq) {
306 case AR71XX_PCI_IRQ_DEV0:
307 irq -= AR71XX_PCI_IRQ_BASE;
308
309 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK);
310 __raw_writel(t & ~AR724X_PCI_INT_DEV0,
311 base + AR724X_PCI_REG_INT_MASK);
312
313 /* flush write */
314 (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK);
315
316 t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
317 __raw_writel(t | AR724X_PCI_INT_DEV0,
318 base + AR724X_PCI_REG_INT_STATUS);
319
320 /* flush write */
321 (void) __raw_readl(base + AR724X_PCI_REG_INT_STATUS);
322 }
323 }
324
325 static struct irq_chip ar724x_pci_irq_chip = {
326 .name = "AR724X PCI ",
327 .mask = ar724x_pci_irq_mask,
328 .unmask = ar724x_pci_irq_unmask,
329 .mask_ack = ar724x_pci_irq_mask,
330 };
331
332 static void __init ar724x_pci_irq_init(void)
333 {
334 void __iomem *base = ar724x_pci_ctrl_base;
335 u32 t;
336 int i;
337
338 t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
339 if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY |
340 AR724X_RESET_PCIE_PHY_SERIAL)) {
341 return;
342 }
343
344 __raw_writel(0, base + AR724X_PCI_REG_INT_MASK);
345 __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS);
346
347 for (i = AR71XX_PCI_IRQ_BASE;
348 i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++)
349 set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
350 handle_level_irq);
351
352 set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler);
353 }
354
355 int __init ar724x_pcibios_init(void)
356 {
357 int ret = -ENOMEM;
358
359 ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE,
360 AR724X_PCI_CRP_SIZE);
361 if (ar724x_pci_localcfg_base == NULL)
362 goto err;
363
364 ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE,
365 AR724X_PCI_CFG_SIZE);
366 if (ar724x_pci_devcfg_base == NULL)
367 goto err_unmap_localcfg;
368
369 ar724x_pci_ctrl_base = ioremap_nocache(AR724X_PCI_CTRL_BASE,
370 AR724X_PCI_CTRL_SIZE);
371 if (ar724x_pci_ctrl_base == NULL)
372 goto err_unmap_devcfg;
373
374 ar724x_pci_reset();
375 ret = ar724x_pci_setup();
376 if (ret)
377 goto err_unmap_ctrl;
378
379 ar724x_pci_fixup_enable = 1;
380 ar724x_pci_irq_init();
381 register_pci_controller(&ar724x_pci_controller);
382
383 return 0;
384
385 err_unmap_ctrl:
386 iounmap(ar724x_pci_ctrl_base);
387 err_unmap_devcfg:
388 iounmap(ar724x_pci_devcfg_base);
389 err_unmap_localcfg:
390 iounmap(ar724x_pci_localcfg_base);
391 err:
392 return ret;
393 }