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[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/phy.h>
29 #include <linux/skbuff.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32
33 #include <linux/bitops.h>
34
35 #include <asm/mach-ar71xx/ar71xx.h>
36 #include <asm/mach-ar71xx/platform.h>
37
38 #define ETH_FCS_LEN 4
39
40 #define AG71XX_DRV_NAME "ag71xx"
41 #define AG71XX_DRV_VERSION "0.5.16"
42
43 #define AG71XX_NAPI_WEIGHT 64
44 #define AG71XX_OOM_REFILL (1 + HZ/10)
45
46 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
47 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
48 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
49
50 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
51 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
52
53 #define AG71XX_TX_FIFO_LEN 2048
54 #define AG71XX_TX_MTU_LEN 1536
55 #define AG71XX_RX_PKT_RESERVE 64
56 #define AG71XX_RX_PKT_SIZE \
57 (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
58
59 #define AG71XX_TX_RING_SIZE 64
60 #define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4)
61 #define AG71XX_TX_THRES_WAKEUP \
62 (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
63
64 #define AG71XX_RX_RING_SIZE 128
65
66 #undef AG71XX_DEBUG
67 #ifdef AG71XX_DEBUG
68 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
69 #else
70 #define DBG(fmt, args...) do {} while (0)
71 #endif
72
73 #define ag71xx_assert(_cond) \
74 do { \
75 if (_cond) \
76 break; \
77 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
78 BUG(); \
79 } while (0)
80
81 struct ag71xx_desc {
82 u32 data;
83 u32 ctrl;
84 #define DESC_EMPTY BIT(31)
85 #define DESC_MORE BIT(24)
86 #define DESC_PKTLEN_M 0x1fff
87 u32 next;
88 u32 pad;
89 };
90
91 struct ag71xx_buf {
92 struct sk_buff *skb;
93 };
94
95 struct ag71xx_ring {
96 struct ag71xx_buf *buf;
97 struct ag71xx_desc *descs;
98 dma_addr_t descs_dma;
99 unsigned int curr;
100 unsigned int dirty;
101 unsigned int size;
102 };
103
104 struct ag71xx_mdio {
105 struct mii_bus mii_bus;
106 int mii_irq[PHY_MAX_ADDR];
107 void __iomem *mdio_base;
108 };
109
110 struct ag71xx {
111 void __iomem *mac_base;
112 void __iomem *mac_base2;
113 void __iomem *mii_ctrl;
114
115 spinlock_t lock;
116 struct platform_device *pdev;
117 struct net_device *dev;
118 struct napi_struct napi;
119 u32 msg_enable;
120
121 struct ag71xx_ring rx_ring;
122 struct ag71xx_ring tx_ring;
123
124 struct mii_bus *mii_bus;
125 struct phy_device *phy_dev;
126
127 unsigned int link;
128 unsigned int speed;
129 int duplex;
130
131 struct work_struct restart_work;
132 struct timer_list oom_timer;
133 };
134
135 extern struct ethtool_ops ag71xx_ethtool_ops;
136
137 extern struct ag71xx_mdio *ag71xx_mdio_bus;
138 extern int ag71xx_mdio_driver_init(void) __init;
139 extern void ag71xx_mdio_driver_exit(void);
140
141 extern int ag71xx_phy_connect(struct ag71xx *ag);
142 extern void ag71xx_phy_disconnect(struct ag71xx *ag);
143 extern void ag71xx_phy_start(struct ag71xx *ag);
144 extern void ag71xx_phy_stop(struct ag71xx *ag);
145
146 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
147 {
148 return ag->pdev->dev.platform_data;
149 }
150
151 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
152 {
153 return ((desc->ctrl & DESC_EMPTY) != 0);
154 }
155
156 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
157 {
158 return (desc->ctrl & DESC_PKTLEN_M);
159 }
160
161 /* Register offsets */
162 #define AG71XX_REG_MAC_CFG1 0x0000
163 #define AG71XX_REG_MAC_CFG2 0x0004
164 #define AG71XX_REG_MAC_IPG 0x0008
165 #define AG71XX_REG_MAC_HDX 0x000c
166 #define AG71XX_REG_MAC_MFL 0x0010
167 #define AG71XX_REG_MII_CFG 0x0020
168 #define AG71XX_REG_MII_CMD 0x0024
169 #define AG71XX_REG_MII_ADDR 0x0028
170 #define AG71XX_REG_MII_CTRL 0x002c
171 #define AG71XX_REG_MII_STATUS 0x0030
172 #define AG71XX_REG_MII_IND 0x0034
173 #define AG71XX_REG_MAC_IFCTL 0x0038
174 #define AG71XX_REG_MAC_ADDR1 0x0040
175 #define AG71XX_REG_MAC_ADDR2 0x0044
176 #define AG71XX_REG_FIFO_CFG0 0x0048
177 #define AG71XX_REG_FIFO_CFG1 0x004c
178 #define AG71XX_REG_FIFO_CFG2 0x0050
179 #define AG71XX_REG_FIFO_CFG3 0x0054
180 #define AG71XX_REG_FIFO_CFG4 0x0058
181 #define AG71XX_REG_FIFO_CFG5 0x005c
182 #define AG71XX_REG_FIFO_RAM0 0x0060
183 #define AG71XX_REG_FIFO_RAM1 0x0064
184 #define AG71XX_REG_FIFO_RAM2 0x0068
185 #define AG71XX_REG_FIFO_RAM3 0x006c
186 #define AG71XX_REG_FIFO_RAM4 0x0070
187 #define AG71XX_REG_FIFO_RAM5 0x0074
188 #define AG71XX_REG_FIFO_RAM6 0x0078
189 #define AG71XX_REG_FIFO_RAM7 0x007c
190
191 #define AG71XX_REG_TX_CTRL 0x0180
192 #define AG71XX_REG_TX_DESC 0x0184
193 #define AG71XX_REG_TX_STATUS 0x0188
194 #define AG71XX_REG_RX_CTRL 0x018c
195 #define AG71XX_REG_RX_DESC 0x0190
196 #define AG71XX_REG_RX_STATUS 0x0194
197 #define AG71XX_REG_INT_ENABLE 0x0198
198 #define AG71XX_REG_INT_STATUS 0x019c
199
200 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
201 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
202 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
203 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
204 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
205 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
206 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
207 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
208
209 #define MAC_CFG2_FDX BIT(0)
210 #define MAC_CFG2_CRC_EN BIT(1)
211 #define MAC_CFG2_PAD_CRC_EN BIT(2)
212 #define MAC_CFG2_LEN_CHECK BIT(4)
213 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
214 #define MAC_CFG2_IF_1000 BIT(9)
215 #define MAC_CFG2_IF_10_100 BIT(8)
216
217 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
218 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
219 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
220 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
221 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
222 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
223 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
224
225 #define FIFO_CFG0_ENABLE_SHIFT 8
226
227 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
228 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
229 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
230 #define FIFO_CFG4_CE BIT(3) /* Code Error */
231 #define FIFO_CFG4_CR BIT(4) /* CRC error */
232 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
233 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
234 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
235 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
236 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
237 #define FIFO_CFG4_DR BIT(10) /* Dribble */
238 #define FIFO_CFG4_LE BIT(11) /* Long Event */
239 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
240 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
241 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
242 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
243 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
244 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
245
246 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
247 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
248 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
249 #define FIFO_CFG5_CE BIT(3) /* Code Error */
250 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
251 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
252 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
253 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
254 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
255 #define FIFO_CFG5_DR BIT(9) /* Dribble */
256 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
257 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
258 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
259 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
260 #define FIFO_CFG5_LE BIT(14) /* Long Event */
261 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
262 #define FIFO_CFG5_16 BIT(16) /* unknown */
263 #define FIFO_CFG5_17 BIT(17) /* unknown */
264 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
265 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
266
267 #define AG71XX_INT_TX_PS BIT(0)
268 #define AG71XX_INT_TX_UR BIT(1)
269 #define AG71XX_INT_TX_BE BIT(3)
270 #define AG71XX_INT_RX_PR BIT(4)
271 #define AG71XX_INT_RX_OF BIT(6)
272 #define AG71XX_INT_RX_BE BIT(7)
273
274 #define MAC_IFCTL_SPEED BIT(16)
275
276 #define MII_CFG_CLK_DIV_4 0
277 #define MII_CFG_CLK_DIV_6 2
278 #define MII_CFG_CLK_DIV_8 3
279 #define MII_CFG_CLK_DIV_10 4
280 #define MII_CFG_CLK_DIV_14 5
281 #define MII_CFG_CLK_DIV_20 6
282 #define MII_CFG_CLK_DIV_28 7
283 #define MII_CFG_RESET BIT(31)
284
285 #define MII_CMD_WRITE 0x0
286 #define MII_CMD_READ 0x1
287 #define MII_ADDR_SHIFT 8
288 #define MII_IND_BUSY BIT(0)
289 #define MII_IND_INVALID BIT(2)
290
291 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
292
293 #define TX_STATUS_PS BIT(0) /* Packet Sent */
294 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
295 #define TX_STATUS_BE BIT(3) /* Bus Error */
296
297 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
298
299 #define RX_STATUS_PR BIT(0) /* Packet Received */
300 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
301 #define RX_STATUS_BE BIT(3) /* Bus Error */
302
303 #define MII_CTRL_IF_MASK 3
304 #define MII_CTRL_SPEED_SHIFT 4
305 #define MII_CTRL_SPEED_MASK 3
306 #define MII_CTRL_SPEED_10 0
307 #define MII_CTRL_SPEED_100 1
308 #define MII_CTRL_SPEED_1000 2
309
310 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
311 {
312 void __iomem *r;
313
314 switch (reg) {
315 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
316 r = ag->mac_base + reg;
317 __raw_writel(value, r);
318 __raw_readl(r);
319 break;
320 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
321 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
322 __raw_writel(value, r);
323 __raw_readl(r);
324 break;
325 default:
326 BUG();
327 }
328 }
329
330 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
331 {
332 void __iomem *r;
333 u32 ret;
334
335 switch (reg) {
336 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
337 r = ag->mac_base + reg;
338 ret = __raw_readl(r);
339 break;
340 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
341 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
342 ret = __raw_readl(r);
343 break;
344 default:
345 BUG();
346 }
347
348 return ret;
349 }
350
351 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
352 {
353 void __iomem *r;
354
355 switch (reg) {
356 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
357 r = ag->mac_base + reg;
358 __raw_writel(__raw_readl(r) | mask, r);
359 __raw_readl(r);
360 break;
361 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
362 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
363 __raw_writel(__raw_readl(r) | mask, r);
364 __raw_readl(r);
365 break;
366 default:
367 BUG();
368 }
369 }
370
371 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
372 {
373 void __iomem *r;
374
375 switch (reg) {
376 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
377 r = ag->mac_base + reg;
378 __raw_writel(__raw_readl(r) & ~mask, r);
379 __raw_readl(r);
380 break;
381 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
382 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
383 __raw_writel(__raw_readl(r) & ~mask, r);
384 __raw_readl(r);
385 break;
386 default:
387 BUG();
388 }
389 }
390
391 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
392 {
393 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
394 }
395
396 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
397 {
398 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
399 }
400
401 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
402 {
403 __raw_writel(value, ag->mii_ctrl);
404 __raw_readl(ag->mii_ctrl);
405 }
406
407 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
408 {
409 return __raw_readl(ag->mii_ctrl);
410 }
411
412 static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
413 unsigned int mii_if)
414 {
415 u32 t;
416
417 t = ag71xx_mii_ctrl_rr(ag);
418 t &= ~(MII_CTRL_IF_MASK);
419 t |= (mii_if & MII_CTRL_IF_MASK);
420 ag71xx_mii_ctrl_wr(ag, t);
421 }
422
423 static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
424 unsigned int speed)
425 {
426 u32 t;
427
428 t = ag71xx_mii_ctrl_rr(ag);
429 t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
430 t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
431 ag71xx_mii_ctrl_wr(ag, t);
432 }
433
434 #endif /* _AG71XX_H */
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