40715c90683583ac9e87fdb0c4ebca13caa2e440
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/phy.h>
29 #include <linux/skbuff.h>
30 #include <linux/dma-mapping.h>
31
32 #include <linux/bitops.h>
33
34 #include <asm/mach-ar71xx/ar71xx.h>
35 #include <asm/mach-ar71xx/platform.h>
36
37 #define ETH_FCS_LEN 4
38
39 #define AG71XX_DRV_NAME "ag71xx"
40 #define AG71XX_DRV_VERSION "0.5.7"
41
42 #define AG71XX_NAPI_TX 1
43
44 #define AG71XX_NAPI_WEIGHT 64
45
46 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
47 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
48 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
49
50 #ifdef AG71XX_NAPI_TX
51 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
52 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
53 #else
54 #define AG71XX_INT_POLL (AG71XX_INT_RX)
55 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL | AG71XX_INT_TX)
56 #endif
57
58 #define AG71XX_TX_FIFO_LEN 2048
59 #define AG71XX_TX_MTU_LEN 1536
60 #define AG71XX_RX_PKT_RESERVE 64
61 #define AG71XX_RX_PKT_SIZE \
62 (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
63
64 #define AG71XX_TX_RING_SIZE 64
65 #define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4)
66 #define AG71XX_TX_THRES_WAKEUP \
67 (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
68
69 #define AG71XX_RX_RING_SIZE 128
70
71 #undef AG71XX_DEBUG
72 #ifdef AG71XX_DEBUG
73 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
74 #else
75 #define DBG(fmt, args...) do {} while (0)
76 #endif
77
78 #define ag71xx_assert(_cond) \
79 do { \
80 if (_cond) \
81 break; \
82 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
83 BUG(); \
84 } while (0)
85
86 struct ag71xx_desc {
87 u32 data;
88 u32 ctrl;
89 #define DESC_EMPTY BIT(31)
90 #define DESC_MORE BIT(24)
91 #define DESC_PKTLEN_M 0x1fff
92 u32 next;
93 };
94
95 struct ag71xx_buf {
96 struct sk_buff *skb;
97 };
98
99 struct ag71xx_ring {
100 struct ag71xx_buf *buf;
101 struct ag71xx_desc *descs;
102 dma_addr_t descs_dma;
103 unsigned int curr;
104 unsigned int dirty;
105 unsigned int size;
106 };
107
108 struct ag71xx_mdio {
109 struct mii_bus mii_bus;
110 int mii_irq[PHY_MAX_ADDR];
111 void __iomem *mdio_base;
112 };
113
114 struct ag71xx {
115 void __iomem *mac_base;
116 void __iomem *mac_base2;
117 void __iomem *mii_ctrl;
118
119 spinlock_t lock;
120 struct platform_device *pdev;
121 struct net_device *dev;
122 struct napi_struct napi;
123 u32 msg_enable;
124
125 struct ag71xx_ring rx_ring;
126 struct ag71xx_ring tx_ring;
127
128 struct mii_bus *mii_bus;
129 struct phy_device *phy_dev;
130
131 unsigned int link;
132 unsigned int speed;
133 int duplex;
134 };
135
136 extern struct ethtool_ops ag71xx_ethtool_ops;
137
138 extern struct ag71xx_mdio *ag71xx_mdio_bus;
139 extern int ag71xx_mdio_driver_init(void) __init;
140 extern void ag71xx_mdio_driver_exit(void);
141
142 extern int ag71xx_phy_connect(struct ag71xx *ag);
143 extern void ag71xx_phy_disconnect(struct ag71xx *ag);
144 extern void ag71xx_phy_start(struct ag71xx *ag);
145 extern void ag71xx_phy_stop(struct ag71xx *ag);
146
147 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
148 {
149 return ag->pdev->dev.platform_data;
150 }
151
152 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
153 {
154 return ((desc->ctrl & DESC_EMPTY) != 0);
155 }
156
157 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
158 {
159 return (desc->ctrl & DESC_PKTLEN_M);
160 }
161
162 /* Register offsets */
163 #define AG71XX_REG_MAC_CFG1 0x0000
164 #define AG71XX_REG_MAC_CFG2 0x0004
165 #define AG71XX_REG_MAC_IPG 0x0008
166 #define AG71XX_REG_MAC_HDX 0x000c
167 #define AG71XX_REG_MAC_MFL 0x0010
168 #define AG71XX_REG_MII_CFG 0x0020
169 #define AG71XX_REG_MII_CMD 0x0024
170 #define AG71XX_REG_MII_ADDR 0x0028
171 #define AG71XX_REG_MII_CTRL 0x002c
172 #define AG71XX_REG_MII_STATUS 0x0030
173 #define AG71XX_REG_MII_IND 0x0034
174 #define AG71XX_REG_MAC_IFCTL 0x0038
175 #define AG71XX_REG_MAC_ADDR1 0x0040
176 #define AG71XX_REG_MAC_ADDR2 0x0044
177 #define AG71XX_REG_FIFO_CFG0 0x0048
178 #define AG71XX_REG_FIFO_CFG1 0x004c
179 #define AG71XX_REG_FIFO_CFG2 0x0050
180 #define AG71XX_REG_FIFO_CFG3 0x0054
181 #define AG71XX_REG_FIFO_CFG4 0x0058
182 #define AG71XX_REG_FIFO_CFG5 0x005c
183 #define AG71XX_REG_FIFO_RAM0 0x0060
184 #define AG71XX_REG_FIFO_RAM1 0x0064
185 #define AG71XX_REG_FIFO_RAM2 0x0068
186 #define AG71XX_REG_FIFO_RAM3 0x006c
187 #define AG71XX_REG_FIFO_RAM4 0x0070
188 #define AG71XX_REG_FIFO_RAM5 0x0074
189 #define AG71XX_REG_FIFO_RAM6 0x0078
190 #define AG71XX_REG_FIFO_RAM7 0x007c
191
192 #define AG71XX_REG_TX_CTRL 0x0180
193 #define AG71XX_REG_TX_DESC 0x0184
194 #define AG71XX_REG_TX_STATUS 0x0188
195 #define AG71XX_REG_RX_CTRL 0x018c
196 #define AG71XX_REG_RX_DESC 0x0190
197 #define AG71XX_REG_RX_STATUS 0x0194
198 #define AG71XX_REG_INT_ENABLE 0x0198
199 #define AG71XX_REG_INT_STATUS 0x019c
200
201 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
202 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
203 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
204 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
205 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
206 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
207 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
208 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
209
210 #define MAC_CFG2_FDX BIT(0)
211 #define MAC_CFG2_CRC_EN BIT(1)
212 #define MAC_CFG2_PAD_CRC_EN BIT(2)
213 #define MAC_CFG2_LEN_CHECK BIT(4)
214 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
215 #define MAC_CFG2_IF_1000 BIT(9)
216 #define MAC_CFG2_IF_10_100 BIT(8)
217
218 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
219 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
220 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
221 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
222 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
223 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
224 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
225
226 #define FIFO_CFG0_ENABLE_SHIFT 8
227
228 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
229 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
230 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
231 #define FIFO_CFG4_CE BIT(3) /* Code Error */
232 #define FIFO_CFG4_CRC BIT(4) /* CRC error */
233 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
234 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
235 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
236 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
237 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
238 #define FIFO_CFG4_DR BIT(10) /* Dribble */
239 #define FIFO_CFG4_LE BIT(11) /* Long Event */
240 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
241 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
242 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
243 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
244 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
245 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
246
247 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
248 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
249 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
250 #define FIFO_CFG5_CE BIT(3) /* Code Error */
251 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
252 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
253 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
254 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
255 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
256 #define FIFO_CFG5_DR BIT(9) /* Dribble */
257 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
258 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
259 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
260 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
261 #define FIFO_CFG5_LE BIT(14) /* Long Event */
262 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
263 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
264 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
265
266 #define AG71XX_INT_TX_PS BIT(0)
267 #define AG71XX_INT_TX_UR BIT(1)
268 #define AG71XX_INT_TX_BE BIT(3)
269 #define AG71XX_INT_RX_PR BIT(4)
270 #define AG71XX_INT_RX_OF BIT(6)
271 #define AG71XX_INT_RX_BE BIT(7)
272
273 #define MAC_IFCTL_SPEED BIT(16)
274
275 #define MII_CFG_CLK_DIV_4 0
276 #define MII_CFG_CLK_DIV_6 2
277 #define MII_CFG_CLK_DIV_8 3
278 #define MII_CFG_CLK_DIV_10 4
279 #define MII_CFG_CLK_DIV_14 5
280 #define MII_CFG_CLK_DIV_20 6
281 #define MII_CFG_CLK_DIV_28 7
282 #define MII_CFG_RESET BIT(31)
283
284 #define MII_CMD_WRITE 0x0
285 #define MII_CMD_READ 0x1
286 #define MII_ADDR_SHIFT 8
287 #define MII_IND_BUSY BIT(0)
288 #define MII_IND_INVALID BIT(2)
289
290 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
291
292 #define TX_STATUS_PS BIT(0) /* Packet Sent */
293 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
294 #define TX_STATUS_BE BIT(3) /* Bus Error */
295
296 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
297
298 #define RX_STATUS_PR BIT(0) /* Packet Received */
299 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
300 #define RX_STATUS_BE BIT(3) /* Bus Error */
301
302 #define MII_CTRL_IF_MASK 3
303 #define MII_CTRL_SPEED_SHIFT 4
304 #define MII_CTRL_SPEED_MASK 3
305 #define MII_CTRL_SPEED_10 0
306 #define MII_CTRL_SPEED_100 1
307 #define MII_CTRL_SPEED_1000 2
308
309 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
310 {
311 switch (reg) {
312 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
313 __raw_writel(value, ag->mac_base + reg);
314 break;
315 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
316 reg -= AG71XX_REG_MAC_IFCTL;
317 __raw_writel(value, ag->mac_base2 + reg);
318 break;
319 default:
320 BUG();
321 }
322 }
323
324 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
325 {
326 u32 ret;
327
328 switch (reg) {
329 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
330 ret = __raw_readl(ag->mac_base + reg);
331 break;
332 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
333 reg -= AG71XX_REG_MAC_IFCTL;
334 ret = __raw_readl(ag->mac_base2 + reg);
335 break;
336 default:
337 BUG();
338 }
339
340 return ret;
341 }
342
343 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
344 {
345 void __iomem *r;
346
347 switch (reg) {
348 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
349 r = ag->mac_base + reg;
350 __raw_writel(__raw_readl(r) | mask, r);
351 break;
352 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
353 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
354 __raw_writel(__raw_readl(r) | mask, r);
355 break;
356 default:
357 BUG();
358 }
359 }
360
361 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
362 {
363 void __iomem *r;
364
365 switch (reg) {
366 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
367 r = ag->mac_base + reg;
368 __raw_writel(__raw_readl(r) & ~mask, r);
369 break;
370 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
371 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
372 __raw_writel(__raw_readl(r) & ~mask, r);
373 break;
374 default:
375 BUG();
376 }
377 }
378
379 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
380 {
381 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
382 }
383
384 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
385 {
386 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
387 }
388
389 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
390 {
391 __raw_writel(value, ag->mii_ctrl);
392 }
393
394 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
395 {
396 return __raw_readl(ag->mii_ctrl);
397 }
398
399 static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
400 unsigned int mii_if)
401 {
402 u32 t;
403
404 t = ag71xx_mii_ctrl_rr(ag);
405 t &= ~(MII_CTRL_IF_MASK);
406 t |= (mii_if & MII_CTRL_IF_MASK);
407 ag71xx_mii_ctrl_wr(ag, t);
408 }
409
410 static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
411 unsigned int speed)
412 {
413 u32 t;
414
415 t = ag71xx_mii_ctrl_rr(ag);
416 t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
417 t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
418 ag71xx_mii_ctrl_wr(ag, t);
419 }
420
421 #endif /* _AG71XX_H */