7daa9f206611dedfb310668be1158d9abdec3caa
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/phy.h>
29 #include <linux/skbuff.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32
33 #include <linux/bitops.h>
34
35 #include <asm/mach-ar71xx/ar71xx.h>
36 #include <asm/mach-ar71xx/platform.h>
37
38 #define ETH_FCS_LEN 4
39
40 #define AG71XX_DRV_NAME "ag71xx"
41 #define AG71XX_DRV_VERSION "0.5.14"
42
43 #define AG71XX_NAPI_WEIGHT 64
44 #define AG71XX_OOM_REFILL (1 + HZ/10)
45
46 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
47 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
48 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
49
50 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
51 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
52
53 #define AG71XX_TX_FIFO_LEN 2048
54 #define AG71XX_TX_MTU_LEN 1536
55 #define AG71XX_RX_PKT_RESERVE 64
56 #define AG71XX_RX_PKT_SIZE \
57 (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
58
59 #define AG71XX_TX_RING_SIZE 64
60 #define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4)
61 #define AG71XX_TX_THRES_WAKEUP \
62 (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
63
64 #define AG71XX_RX_RING_SIZE 128
65
66 #undef AG71XX_DEBUG
67 #ifdef AG71XX_DEBUG
68 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
69 #else
70 #define DBG(fmt, args...) do {} while (0)
71 #endif
72
73 #define ag71xx_assert(_cond) \
74 do { \
75 if (_cond) \
76 break; \
77 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
78 BUG(); \
79 } while (0)
80
81 struct ag71xx_desc {
82 u32 data;
83 u32 ctrl;
84 #define DESC_EMPTY BIT(31)
85 #define DESC_MORE BIT(24)
86 #define DESC_PKTLEN_M 0x1fff
87 u32 next;
88 };
89
90 struct ag71xx_buf {
91 struct sk_buff *skb;
92 };
93
94 struct ag71xx_ring {
95 struct ag71xx_buf *buf;
96 struct ag71xx_desc *descs;
97 dma_addr_t descs_dma;
98 unsigned int curr;
99 unsigned int dirty;
100 unsigned int size;
101 };
102
103 struct ag71xx_mdio {
104 struct mii_bus mii_bus;
105 int mii_irq[PHY_MAX_ADDR];
106 void __iomem *mdio_base;
107 };
108
109 struct ag71xx {
110 void __iomem *mac_base;
111 void __iomem *mac_base2;
112 void __iomem *mii_ctrl;
113
114 spinlock_t lock;
115 struct platform_device *pdev;
116 struct net_device *dev;
117 struct napi_struct napi;
118 u32 msg_enable;
119
120 struct ag71xx_ring rx_ring;
121 struct ag71xx_ring tx_ring;
122
123 struct mii_bus *mii_bus;
124 struct phy_device *phy_dev;
125
126 unsigned int link;
127 unsigned int speed;
128 int duplex;
129
130 struct work_struct restart_work;
131 struct timer_list oom_timer;
132 };
133
134 extern struct ethtool_ops ag71xx_ethtool_ops;
135
136 extern struct ag71xx_mdio *ag71xx_mdio_bus;
137 extern int ag71xx_mdio_driver_init(void) __init;
138 extern void ag71xx_mdio_driver_exit(void);
139
140 extern int ag71xx_phy_connect(struct ag71xx *ag);
141 extern void ag71xx_phy_disconnect(struct ag71xx *ag);
142 extern void ag71xx_phy_start(struct ag71xx *ag);
143 extern void ag71xx_phy_stop(struct ag71xx *ag);
144
145 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
146 {
147 return ag->pdev->dev.platform_data;
148 }
149
150 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
151 {
152 return ((desc->ctrl & DESC_EMPTY) != 0);
153 }
154
155 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
156 {
157 return (desc->ctrl & DESC_PKTLEN_M);
158 }
159
160 /* Register offsets */
161 #define AG71XX_REG_MAC_CFG1 0x0000
162 #define AG71XX_REG_MAC_CFG2 0x0004
163 #define AG71XX_REG_MAC_IPG 0x0008
164 #define AG71XX_REG_MAC_HDX 0x000c
165 #define AG71XX_REG_MAC_MFL 0x0010
166 #define AG71XX_REG_MII_CFG 0x0020
167 #define AG71XX_REG_MII_CMD 0x0024
168 #define AG71XX_REG_MII_ADDR 0x0028
169 #define AG71XX_REG_MII_CTRL 0x002c
170 #define AG71XX_REG_MII_STATUS 0x0030
171 #define AG71XX_REG_MII_IND 0x0034
172 #define AG71XX_REG_MAC_IFCTL 0x0038
173 #define AG71XX_REG_MAC_ADDR1 0x0040
174 #define AG71XX_REG_MAC_ADDR2 0x0044
175 #define AG71XX_REG_FIFO_CFG0 0x0048
176 #define AG71XX_REG_FIFO_CFG1 0x004c
177 #define AG71XX_REG_FIFO_CFG2 0x0050
178 #define AG71XX_REG_FIFO_CFG3 0x0054
179 #define AG71XX_REG_FIFO_CFG4 0x0058
180 #define AG71XX_REG_FIFO_CFG5 0x005c
181 #define AG71XX_REG_FIFO_RAM0 0x0060
182 #define AG71XX_REG_FIFO_RAM1 0x0064
183 #define AG71XX_REG_FIFO_RAM2 0x0068
184 #define AG71XX_REG_FIFO_RAM3 0x006c
185 #define AG71XX_REG_FIFO_RAM4 0x0070
186 #define AG71XX_REG_FIFO_RAM5 0x0074
187 #define AG71XX_REG_FIFO_RAM6 0x0078
188 #define AG71XX_REG_FIFO_RAM7 0x007c
189
190 #define AG71XX_REG_TX_CTRL 0x0180
191 #define AG71XX_REG_TX_DESC 0x0184
192 #define AG71XX_REG_TX_STATUS 0x0188
193 #define AG71XX_REG_RX_CTRL 0x018c
194 #define AG71XX_REG_RX_DESC 0x0190
195 #define AG71XX_REG_RX_STATUS 0x0194
196 #define AG71XX_REG_INT_ENABLE 0x0198
197 #define AG71XX_REG_INT_STATUS 0x019c
198
199 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
200 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
201 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
202 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
203 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
204 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
205 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
206 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
207
208 #define MAC_CFG2_FDX BIT(0)
209 #define MAC_CFG2_CRC_EN BIT(1)
210 #define MAC_CFG2_PAD_CRC_EN BIT(2)
211 #define MAC_CFG2_LEN_CHECK BIT(4)
212 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
213 #define MAC_CFG2_IF_1000 BIT(9)
214 #define MAC_CFG2_IF_10_100 BIT(8)
215
216 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
217 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
218 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
219 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
220 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
221 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
222 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
223
224 #define FIFO_CFG0_ENABLE_SHIFT 8
225
226 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
227 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
228 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
229 #define FIFO_CFG4_CE BIT(3) /* Code Error */
230 #define FIFO_CFG4_CR BIT(4) /* CRC error */
231 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
232 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
233 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
234 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
235 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
236 #define FIFO_CFG4_DR BIT(10) /* Dribble */
237 #define FIFO_CFG4_LE BIT(11) /* Long Event */
238 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
239 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
240 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
241 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
242 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
243 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
244
245 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
246 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
247 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
248 #define FIFO_CFG5_CE BIT(3) /* Code Error */
249 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
250 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
251 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
252 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
253 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
254 #define FIFO_CFG5_DR BIT(9) /* Dribble */
255 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
256 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
257 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
258 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
259 #define FIFO_CFG5_LE BIT(14) /* Long Event */
260 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
261 #define FIFO_CFG5_16 BIT(16) /* unknown */
262 #define FIFO_CFG5_17 BIT(17) /* unknown */
263 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
264 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
265
266 #define AG71XX_INT_TX_PS BIT(0)
267 #define AG71XX_INT_TX_UR BIT(1)
268 #define AG71XX_INT_TX_BE BIT(3)
269 #define AG71XX_INT_RX_PR BIT(4)
270 #define AG71XX_INT_RX_OF BIT(6)
271 #define AG71XX_INT_RX_BE BIT(7)
272
273 #define MAC_IFCTL_SPEED BIT(16)
274
275 #define MII_CFG_CLK_DIV_4 0
276 #define MII_CFG_CLK_DIV_6 2
277 #define MII_CFG_CLK_DIV_8 3
278 #define MII_CFG_CLK_DIV_10 4
279 #define MII_CFG_CLK_DIV_14 5
280 #define MII_CFG_CLK_DIV_20 6
281 #define MII_CFG_CLK_DIV_28 7
282 #define MII_CFG_RESET BIT(31)
283
284 #define MII_CMD_WRITE 0x0
285 #define MII_CMD_READ 0x1
286 #define MII_ADDR_SHIFT 8
287 #define MII_IND_BUSY BIT(0)
288 #define MII_IND_INVALID BIT(2)
289
290 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
291
292 #define TX_STATUS_PS BIT(0) /* Packet Sent */
293 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
294 #define TX_STATUS_BE BIT(3) /* Bus Error */
295
296 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
297
298 #define RX_STATUS_PR BIT(0) /* Packet Received */
299 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
300 #define RX_STATUS_BE BIT(3) /* Bus Error */
301
302 #define MII_CTRL_IF_MASK 3
303 #define MII_CTRL_SPEED_SHIFT 4
304 #define MII_CTRL_SPEED_MASK 3
305 #define MII_CTRL_SPEED_10 0
306 #define MII_CTRL_SPEED_100 1
307 #define MII_CTRL_SPEED_1000 2
308
309 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
310 {
311 void __iomem *r;
312
313 switch (reg) {
314 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
315 r = ag->mac_base + reg;
316 __raw_writel(value, r);
317 __raw_readl(r);
318 break;
319 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
320 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
321 __raw_writel(value, r);
322 __raw_readl(r);
323 break;
324 default:
325 BUG();
326 }
327 }
328
329 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
330 {
331 void __iomem *r;
332 u32 ret;
333
334 switch (reg) {
335 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
336 r = ag->mac_base + reg;
337 ret = __raw_readl(r);
338 break;
339 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
340 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
341 ret = __raw_readl(r);
342 break;
343 default:
344 BUG();
345 }
346
347 return ret;
348 }
349
350 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
351 {
352 void __iomem *r;
353
354 switch (reg) {
355 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
356 r = ag->mac_base + reg;
357 __raw_writel(__raw_readl(r) | mask, r);
358 __raw_readl(r);
359 break;
360 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
361 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
362 __raw_writel(__raw_readl(r) | mask, r);
363 __raw_readl(r);
364 break;
365 default:
366 BUG();
367 }
368 }
369
370 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
371 {
372 void __iomem *r;
373
374 switch (reg) {
375 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
376 r = ag->mac_base + reg;
377 __raw_writel(__raw_readl(r) & ~mask, r);
378 __raw_readl(r);
379 break;
380 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
381 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
382 __raw_writel(__raw_readl(r) & ~mask, r);
383 __raw_readl(r);
384 break;
385 default:
386 BUG();
387 }
388 }
389
390 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
391 {
392 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
393 }
394
395 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
396 {
397 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
398 }
399
400 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
401 {
402 __raw_writel(value, ag->mii_ctrl);
403 __raw_readl(ag->mii_ctrl);
404 }
405
406 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
407 {
408 return __raw_readl(ag->mii_ctrl);
409 }
410
411 static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
412 unsigned int mii_if)
413 {
414 u32 t;
415
416 t = ag71xx_mii_ctrl_rr(ag);
417 t &= ~(MII_CTRL_IF_MASK);
418 t |= (mii_if & MII_CTRL_IF_MASK);
419 ag71xx_mii_ctrl_wr(ag, t);
420 }
421
422 static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
423 unsigned int speed)
424 {
425 u32 t;
426
427 t = ag71xx_mii_ctrl_rr(ag);
428 t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
429 t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
430 ag71xx_mii_ctrl_wr(ag, t);
431 }
432
433 #endif /* _AG71XX_H */