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[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/phy.h>
29 #include <linux/skbuff.h>
30 #include <linux/dma-mapping.h>
31
32 #include <linux/bitops.h>
33
34 #include <asm/mach-ar71xx/ar71xx.h>
35 #include <asm/mach-ar71xx/platform.h>
36
37 #define ETH_FCS_LEN 4
38
39 #define AG71XX_DRV_NAME "ag71xx"
40 #define AG71XX_DRV_VERSION "0.5.10"
41
42 #define AG71XX_NAPI_WEIGHT 64
43
44 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
45 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
46 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
47
48 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
49 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
50
51 #define AG71XX_TX_FIFO_LEN 2048
52 #define AG71XX_TX_MTU_LEN 1536
53 #define AG71XX_RX_PKT_RESERVE 64
54 #define AG71XX_RX_PKT_SIZE \
55 (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
56
57 #define AG71XX_TX_RING_SIZE 64
58 #define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4)
59 #define AG71XX_TX_THRES_WAKEUP \
60 (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
61
62 #define AG71XX_RX_RING_SIZE 128
63
64 #undef AG71XX_DEBUG
65 #ifdef AG71XX_DEBUG
66 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
67 #else
68 #define DBG(fmt, args...) do {} while (0)
69 #endif
70
71 #define ag71xx_assert(_cond) \
72 do { \
73 if (_cond) \
74 break; \
75 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
76 BUG(); \
77 } while (0)
78
79 struct ag71xx_desc {
80 u32 data;
81 u32 ctrl;
82 #define DESC_EMPTY BIT(31)
83 #define DESC_MORE BIT(24)
84 #define DESC_PKTLEN_M 0x1fff
85 u32 next;
86 };
87
88 struct ag71xx_buf {
89 struct sk_buff *skb;
90 };
91
92 struct ag71xx_ring {
93 struct ag71xx_buf *buf;
94 struct ag71xx_desc *descs;
95 dma_addr_t descs_dma;
96 unsigned int curr;
97 unsigned int dirty;
98 unsigned int size;
99 };
100
101 struct ag71xx_mdio {
102 struct mii_bus mii_bus;
103 int mii_irq[PHY_MAX_ADDR];
104 void __iomem *mdio_base;
105 };
106
107 struct ag71xx {
108 void __iomem *mac_base;
109 void __iomem *mac_base2;
110 void __iomem *mii_ctrl;
111
112 spinlock_t lock;
113 struct platform_device *pdev;
114 struct net_device *dev;
115 struct napi_struct napi;
116 u32 msg_enable;
117
118 struct ag71xx_ring rx_ring;
119 struct ag71xx_ring tx_ring;
120
121 struct mii_bus *mii_bus;
122 struct phy_device *phy_dev;
123
124 unsigned int link;
125 unsigned int speed;
126 int duplex;
127 };
128
129 extern struct ethtool_ops ag71xx_ethtool_ops;
130
131 extern struct ag71xx_mdio *ag71xx_mdio_bus;
132 extern int ag71xx_mdio_driver_init(void) __init;
133 extern void ag71xx_mdio_driver_exit(void);
134
135 extern int ag71xx_phy_connect(struct ag71xx *ag);
136 extern void ag71xx_phy_disconnect(struct ag71xx *ag);
137 extern void ag71xx_phy_start(struct ag71xx *ag);
138 extern void ag71xx_phy_stop(struct ag71xx *ag);
139
140 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
141 {
142 return ag->pdev->dev.platform_data;
143 }
144
145 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
146 {
147 return ((desc->ctrl & DESC_EMPTY) != 0);
148 }
149
150 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
151 {
152 return (desc->ctrl & DESC_PKTLEN_M);
153 }
154
155 /* Register offsets */
156 #define AG71XX_REG_MAC_CFG1 0x0000
157 #define AG71XX_REG_MAC_CFG2 0x0004
158 #define AG71XX_REG_MAC_IPG 0x0008
159 #define AG71XX_REG_MAC_HDX 0x000c
160 #define AG71XX_REG_MAC_MFL 0x0010
161 #define AG71XX_REG_MII_CFG 0x0020
162 #define AG71XX_REG_MII_CMD 0x0024
163 #define AG71XX_REG_MII_ADDR 0x0028
164 #define AG71XX_REG_MII_CTRL 0x002c
165 #define AG71XX_REG_MII_STATUS 0x0030
166 #define AG71XX_REG_MII_IND 0x0034
167 #define AG71XX_REG_MAC_IFCTL 0x0038
168 #define AG71XX_REG_MAC_ADDR1 0x0040
169 #define AG71XX_REG_MAC_ADDR2 0x0044
170 #define AG71XX_REG_FIFO_CFG0 0x0048
171 #define AG71XX_REG_FIFO_CFG1 0x004c
172 #define AG71XX_REG_FIFO_CFG2 0x0050
173 #define AG71XX_REG_FIFO_CFG3 0x0054
174 #define AG71XX_REG_FIFO_CFG4 0x0058
175 #define AG71XX_REG_FIFO_CFG5 0x005c
176 #define AG71XX_REG_FIFO_RAM0 0x0060
177 #define AG71XX_REG_FIFO_RAM1 0x0064
178 #define AG71XX_REG_FIFO_RAM2 0x0068
179 #define AG71XX_REG_FIFO_RAM3 0x006c
180 #define AG71XX_REG_FIFO_RAM4 0x0070
181 #define AG71XX_REG_FIFO_RAM5 0x0074
182 #define AG71XX_REG_FIFO_RAM6 0x0078
183 #define AG71XX_REG_FIFO_RAM7 0x007c
184
185 #define AG71XX_REG_TX_CTRL 0x0180
186 #define AG71XX_REG_TX_DESC 0x0184
187 #define AG71XX_REG_TX_STATUS 0x0188
188 #define AG71XX_REG_RX_CTRL 0x018c
189 #define AG71XX_REG_RX_DESC 0x0190
190 #define AG71XX_REG_RX_STATUS 0x0194
191 #define AG71XX_REG_INT_ENABLE 0x0198
192 #define AG71XX_REG_INT_STATUS 0x019c
193
194 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
195 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
196 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
197 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
198 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
199 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
200 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
201 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
202
203 #define MAC_CFG2_FDX BIT(0)
204 #define MAC_CFG2_CRC_EN BIT(1)
205 #define MAC_CFG2_PAD_CRC_EN BIT(2)
206 #define MAC_CFG2_LEN_CHECK BIT(4)
207 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
208 #define MAC_CFG2_IF_1000 BIT(9)
209 #define MAC_CFG2_IF_10_100 BIT(8)
210
211 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
212 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
213 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
214 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
215 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
216 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
217 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
218
219 #define FIFO_CFG0_ENABLE_SHIFT 8
220
221 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
222 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
223 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
224 #define FIFO_CFG4_CE BIT(3) /* Code Error */
225 #define FIFO_CFG4_CRC BIT(4) /* CRC error */
226 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
227 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
228 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
229 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
230 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
231 #define FIFO_CFG4_DR BIT(10) /* Dribble */
232 #define FIFO_CFG4_LE BIT(11) /* Long Event */
233 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
234 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
235 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
236 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
237 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
238 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
239
240 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
241 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
242 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
243 #define FIFO_CFG5_CE BIT(3) /* Code Error */
244 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
245 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
246 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
247 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
248 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
249 #define FIFO_CFG5_DR BIT(9) /* Dribble */
250 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
251 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
252 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
253 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
254 #define FIFO_CFG5_LE BIT(14) /* Long Event */
255 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
256 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
257 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
258
259 #define AG71XX_INT_TX_PS BIT(0)
260 #define AG71XX_INT_TX_UR BIT(1)
261 #define AG71XX_INT_TX_BE BIT(3)
262 #define AG71XX_INT_RX_PR BIT(4)
263 #define AG71XX_INT_RX_OF BIT(6)
264 #define AG71XX_INT_RX_BE BIT(7)
265
266 #define MAC_IFCTL_SPEED BIT(16)
267
268 #define MII_CFG_CLK_DIV_4 0
269 #define MII_CFG_CLK_DIV_6 2
270 #define MII_CFG_CLK_DIV_8 3
271 #define MII_CFG_CLK_DIV_10 4
272 #define MII_CFG_CLK_DIV_14 5
273 #define MII_CFG_CLK_DIV_20 6
274 #define MII_CFG_CLK_DIV_28 7
275 #define MII_CFG_RESET BIT(31)
276
277 #define MII_CMD_WRITE 0x0
278 #define MII_CMD_READ 0x1
279 #define MII_ADDR_SHIFT 8
280 #define MII_IND_BUSY BIT(0)
281 #define MII_IND_INVALID BIT(2)
282
283 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
284
285 #define TX_STATUS_PS BIT(0) /* Packet Sent */
286 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
287 #define TX_STATUS_BE BIT(3) /* Bus Error */
288
289 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
290
291 #define RX_STATUS_PR BIT(0) /* Packet Received */
292 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
293 #define RX_STATUS_BE BIT(3) /* Bus Error */
294
295 #define MII_CTRL_IF_MASK 3
296 #define MII_CTRL_SPEED_SHIFT 4
297 #define MII_CTRL_SPEED_MASK 3
298 #define MII_CTRL_SPEED_10 0
299 #define MII_CTRL_SPEED_100 1
300 #define MII_CTRL_SPEED_1000 2
301
302 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
303 {
304 void __iomem *r;
305
306 switch (reg) {
307 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
308 r = ag->mac_base + reg;
309 __raw_writel(value, r);
310 __raw_readl(r);
311 break;
312 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
313 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
314 __raw_writel(value, r);
315 __raw_readl(r);
316 break;
317 default:
318 BUG();
319 }
320 }
321
322 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
323 {
324 void __iomem *r;
325 u32 ret;
326
327 switch (reg) {
328 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
329 r = ag->mac_base + reg;
330 ret = __raw_readl(r);
331 break;
332 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
333 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
334 ret = __raw_readl(r);
335 break;
336 default:
337 BUG();
338 }
339
340 return ret;
341 }
342
343 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
344 {
345 void __iomem *r;
346
347 switch (reg) {
348 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
349 r = ag->mac_base + reg;
350 __raw_writel(__raw_readl(r) | mask, r);
351 __raw_readl(r);
352 break;
353 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
354 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
355 __raw_writel(__raw_readl(r) | mask, r);
356 __raw_readl(r);
357 break;
358 default:
359 BUG();
360 }
361 }
362
363 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
364 {
365 void __iomem *r;
366
367 switch (reg) {
368 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
369 r = ag->mac_base + reg;
370 __raw_writel(__raw_readl(r) & ~mask, r);
371 __raw_readl(r);
372 break;
373 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
374 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
375 __raw_writel(__raw_readl(r) & ~mask, r);
376 __raw_readl(r);
377 break;
378 default:
379 BUG();
380 }
381 }
382
383 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
384 {
385 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
386 }
387
388 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
389 {
390 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
391 }
392
393 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
394 {
395 __raw_writel(value, ag->mii_ctrl);
396 __raw_readl(ag->mii_ctrl);
397 }
398
399 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
400 {
401 return __raw_readl(ag->mii_ctrl);
402 }
403
404 static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
405 unsigned int mii_if)
406 {
407 u32 t;
408
409 t = ag71xx_mii_ctrl_rr(ag);
410 t &= ~(MII_CTRL_IF_MASK);
411 t |= (mii_if & MII_CTRL_IF_MASK);
412 ag71xx_mii_ctrl_wr(ag, t);
413 }
414
415 static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
416 unsigned int speed)
417 {
418 u32 t;
419
420 t = ag71xx_mii_ctrl_rr(ag);
421 t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
422 t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
423 ag71xx_mii_ctrl_wr(ag, t);
424 }
425
426 #endif /* _AG71XX_H */
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