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ar71xx: ag71xx: fix MAC address setup
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/phy.h>
29 #include <linux/skbuff.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32
33 #include <linux/bitops.h>
34
35 #include <asm/mach-ar71xx/ar71xx.h>
36 #include <asm/mach-ar71xx/platform.h>
37
38 #define ETH_FCS_LEN 4
39
40 #define AG71XX_DRV_NAME "ag71xx"
41 #define AG71XX_DRV_VERSION "0.5.32"
42
43 #define AG71XX_NAPI_WEIGHT 64
44 #define AG71XX_OOM_REFILL (1 + HZ/10)
45
46 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
47 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
48 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
49
50 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
51 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
52
53 #define AG71XX_TX_FIFO_LEN 2048
54 #define AG71XX_TX_MTU_LEN 1536
55 #define AG71XX_RX_PKT_RESERVE 64
56 #define AG71XX_RX_PKT_SIZE \
57 (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
58
59 #define AG71XX_TX_RING_SIZE 64
60 #define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4)
61 #define AG71XX_TX_THRES_WAKEUP \
62 (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
63
64 #define AG71XX_RX_RING_SIZE 128
65
66 #ifdef CONFIG_AG71XX_DEBUG
67 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
68 #else
69 #define DBG(fmt, args...) do {} while (0)
70 #endif
71
72 #define ag71xx_assert(_cond) \
73 do { \
74 if (_cond) \
75 break; \
76 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
77 BUG(); \
78 } while (0)
79
80 struct ag71xx_desc {
81 u32 data;
82 u32 ctrl;
83 #define DESC_EMPTY BIT(31)
84 #define DESC_MORE BIT(24)
85 #define DESC_PKTLEN_M 0xfff
86 u32 next;
87 u32 pad;
88 } __attribute__((aligned(4)));
89
90 struct ag71xx_buf {
91 struct sk_buff *skb;
92 struct ag71xx_desc *desc;
93 dma_addr_t dma_addr;
94 u32 pad;
95 };
96
97 struct ag71xx_ring {
98 struct ag71xx_buf *buf;
99 u8 *descs_cpu;
100 dma_addr_t descs_dma;
101 unsigned int desc_size;
102 unsigned int curr;
103 unsigned int dirty;
104 unsigned int size;
105 };
106
107 struct ag71xx_mdio {
108 struct mii_bus *mii_bus;
109 int mii_irq[PHY_MAX_ADDR];
110 void __iomem *mdio_base;
111 struct ag71xx_mdio_platform_data *pdata;
112 };
113
114 struct ag71xx_int_stats {
115 unsigned long rx_pr;
116 unsigned long rx_be;
117 unsigned long rx_of;
118 unsigned long tx_ps;
119 unsigned long tx_be;
120 unsigned long tx_ur;
121 unsigned long total;
122 };
123
124 struct ag71xx_napi_stats {
125 unsigned long napi_calls;
126 unsigned long rx_count;
127 unsigned long rx_packets;
128 unsigned long rx_packets_max;
129 unsigned long tx_count;
130 unsigned long tx_packets;
131 unsigned long tx_packets_max;
132
133 unsigned long rx[AG71XX_NAPI_WEIGHT + 1];
134 unsigned long tx[AG71XX_NAPI_WEIGHT + 1];
135 };
136
137 struct ag71xx_debug {
138 struct dentry *debugfs_dir;
139 struct dentry *debugfs_int_stats;
140 struct dentry *debugfs_napi_stats;
141
142 struct ag71xx_int_stats int_stats;
143 struct ag71xx_napi_stats napi_stats;
144 };
145
146 struct ag71xx {
147 void __iomem *mac_base;
148 void __iomem *mii_ctrl;
149
150 spinlock_t lock;
151 struct platform_device *pdev;
152 struct net_device *dev;
153 struct napi_struct napi;
154 u32 msg_enable;
155
156 struct ag71xx_ring rx_ring;
157 struct ag71xx_ring tx_ring;
158
159 struct mii_bus *mii_bus;
160 struct phy_device *phy_dev;
161
162 unsigned int link;
163 unsigned int speed;
164 int duplex;
165
166 struct work_struct restart_work;
167 struct timer_list oom_timer;
168
169 #ifdef CONFIG_AG71XX_DEBUG_FS
170 struct ag71xx_debug debug;
171 #endif
172 };
173
174 extern struct ethtool_ops ag71xx_ethtool_ops;
175 void ag71xx_link_adjust(struct ag71xx *ag);
176
177 int ag71xx_mdio_driver_init(void) __init;
178 void ag71xx_mdio_driver_exit(void);
179
180 int ag71xx_phy_connect(struct ag71xx *ag);
181 void ag71xx_phy_disconnect(struct ag71xx *ag);
182 void ag71xx_phy_start(struct ag71xx *ag);
183 void ag71xx_phy_stop(struct ag71xx *ag);
184
185 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
186 {
187 return ag->pdev->dev.platform_data;
188 }
189
190 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
191 {
192 return ((desc->ctrl & DESC_EMPTY) != 0);
193 }
194
195 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
196 {
197 return (desc->ctrl & DESC_PKTLEN_M);
198 }
199
200 /* Register offsets */
201 #define AG71XX_REG_MAC_CFG1 0x0000
202 #define AG71XX_REG_MAC_CFG2 0x0004
203 #define AG71XX_REG_MAC_IPG 0x0008
204 #define AG71XX_REG_MAC_HDX 0x000c
205 #define AG71XX_REG_MAC_MFL 0x0010
206 #define AG71XX_REG_MII_CFG 0x0020
207 #define AG71XX_REG_MII_CMD 0x0024
208 #define AG71XX_REG_MII_ADDR 0x0028
209 #define AG71XX_REG_MII_CTRL 0x002c
210 #define AG71XX_REG_MII_STATUS 0x0030
211 #define AG71XX_REG_MII_IND 0x0034
212 #define AG71XX_REG_MAC_IFCTL 0x0038
213 #define AG71XX_REG_MAC_ADDR1 0x0040
214 #define AG71XX_REG_MAC_ADDR2 0x0044
215 #define AG71XX_REG_FIFO_CFG0 0x0048
216 #define AG71XX_REG_FIFO_CFG1 0x004c
217 #define AG71XX_REG_FIFO_CFG2 0x0050
218 #define AG71XX_REG_FIFO_CFG3 0x0054
219 #define AG71XX_REG_FIFO_CFG4 0x0058
220 #define AG71XX_REG_FIFO_CFG5 0x005c
221 #define AG71XX_REG_FIFO_RAM0 0x0060
222 #define AG71XX_REG_FIFO_RAM1 0x0064
223 #define AG71XX_REG_FIFO_RAM2 0x0068
224 #define AG71XX_REG_FIFO_RAM3 0x006c
225 #define AG71XX_REG_FIFO_RAM4 0x0070
226 #define AG71XX_REG_FIFO_RAM5 0x0074
227 #define AG71XX_REG_FIFO_RAM6 0x0078
228 #define AG71XX_REG_FIFO_RAM7 0x007c
229
230 #define AG71XX_REG_TX_CTRL 0x0180
231 #define AG71XX_REG_TX_DESC 0x0184
232 #define AG71XX_REG_TX_STATUS 0x0188
233 #define AG71XX_REG_RX_CTRL 0x018c
234 #define AG71XX_REG_RX_DESC 0x0190
235 #define AG71XX_REG_RX_STATUS 0x0194
236 #define AG71XX_REG_INT_ENABLE 0x0198
237 #define AG71XX_REG_INT_STATUS 0x019c
238
239 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
240 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
241 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
242 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
243 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
244 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
245 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
246 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
247
248 #define MAC_CFG2_FDX BIT(0)
249 #define MAC_CFG2_CRC_EN BIT(1)
250 #define MAC_CFG2_PAD_CRC_EN BIT(2)
251 #define MAC_CFG2_LEN_CHECK BIT(4)
252 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
253 #define MAC_CFG2_IF_1000 BIT(9)
254 #define MAC_CFG2_IF_10_100 BIT(8)
255
256 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
257 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
258 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
259 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
260 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
261 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
262 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
263
264 #define FIFO_CFG0_ENABLE_SHIFT 8
265
266 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
267 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
268 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
269 #define FIFO_CFG4_CE BIT(3) /* Code Error */
270 #define FIFO_CFG4_CR BIT(4) /* CRC error */
271 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
272 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
273 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
274 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
275 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
276 #define FIFO_CFG4_DR BIT(10) /* Dribble */
277 #define FIFO_CFG4_LE BIT(11) /* Long Event */
278 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
279 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
280 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
281 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
282 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
283 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
284
285 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
286 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
287 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
288 #define FIFO_CFG5_CE BIT(3) /* Code Error */
289 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
290 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
291 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
292 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
293 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
294 #define FIFO_CFG5_DR BIT(9) /* Dribble */
295 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
296 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
297 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
298 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
299 #define FIFO_CFG5_LE BIT(14) /* Long Event */
300 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
301 #define FIFO_CFG5_16 BIT(16) /* unknown */
302 #define FIFO_CFG5_17 BIT(17) /* unknown */
303 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
304 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
305
306 #define AG71XX_INT_TX_PS BIT(0)
307 #define AG71XX_INT_TX_UR BIT(1)
308 #define AG71XX_INT_TX_BE BIT(3)
309 #define AG71XX_INT_RX_PR BIT(4)
310 #define AG71XX_INT_RX_OF BIT(6)
311 #define AG71XX_INT_RX_BE BIT(7)
312
313 #define MAC_IFCTL_SPEED BIT(16)
314
315 #define MII_CFG_CLK_DIV_4 0
316 #define MII_CFG_CLK_DIV_6 2
317 #define MII_CFG_CLK_DIV_8 3
318 #define MII_CFG_CLK_DIV_10 4
319 #define MII_CFG_CLK_DIV_14 5
320 #define MII_CFG_CLK_DIV_20 6
321 #define MII_CFG_CLK_DIV_28 7
322 #define MII_CFG_RESET BIT(31)
323
324 #define MII_CMD_WRITE 0x0
325 #define MII_CMD_READ 0x1
326 #define MII_ADDR_SHIFT 8
327 #define MII_IND_BUSY BIT(0)
328 #define MII_IND_INVALID BIT(2)
329
330 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
331
332 #define TX_STATUS_PS BIT(0) /* Packet Sent */
333 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
334 #define TX_STATUS_BE BIT(3) /* Bus Error */
335
336 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
337
338 #define RX_STATUS_PR BIT(0) /* Packet Received */
339 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
340 #define RX_STATUS_BE BIT(3) /* Bus Error */
341
342 #define MII_CTRL_IF_MASK 3
343 #define MII_CTRL_SPEED_SHIFT 4
344 #define MII_CTRL_SPEED_MASK 3
345 #define MII_CTRL_SPEED_10 0
346 #define MII_CTRL_SPEED_100 1
347 #define MII_CTRL_SPEED_1000 2
348
349 static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
350 {
351 switch (reg) {
352 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
353 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
354 break;
355
356 default:
357 BUG();
358 }
359 }
360
361 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
362 {
363 ag71xx_check_reg_offset(ag, reg);
364
365 __raw_writel(value, ag->mac_base + reg);
366 /* flush write */
367 (void) __raw_readl(ag->mac_base + reg);
368 }
369
370 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
371 {
372 ag71xx_check_reg_offset(ag, reg);
373
374 return __raw_readl(ag->mac_base + reg);
375 }
376
377 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
378 {
379 void __iomem *r;
380
381 ag71xx_check_reg_offset(ag, reg);
382
383 r = ag->mac_base + reg;
384 __raw_writel(__raw_readl(r) | mask, r);
385 /* flush write */
386 (void)__raw_readl(r);
387 }
388
389 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
390 {
391 void __iomem *r;
392
393 ag71xx_check_reg_offset(ag, reg);
394
395 r = ag->mac_base + reg;
396 __raw_writel(__raw_readl(r) & ~mask, r);
397 /* flush write */
398 (void) __raw_readl(r);
399 }
400
401 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
402 {
403 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
404 }
405
406 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
407 {
408 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
409 }
410
411 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
412 {
413 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
414
415 if (pdata->is_ar724x)
416 return;
417
418 __raw_writel(value, ag->mii_ctrl);
419
420 /* flush write */
421 __raw_readl(ag->mii_ctrl);
422 }
423
424 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
425 {
426 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
427
428 if (pdata->is_ar724x)
429 return 0xffffffff;
430
431 return __raw_readl(ag->mii_ctrl);
432 }
433
434 static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
435 unsigned int mii_if)
436 {
437 u32 t;
438
439 t = ag71xx_mii_ctrl_rr(ag);
440 t &= ~(MII_CTRL_IF_MASK);
441 t |= (mii_if & MII_CTRL_IF_MASK);
442 ag71xx_mii_ctrl_wr(ag, t);
443 }
444
445 static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
446 unsigned int speed)
447 {
448 u32 t;
449
450 t = ag71xx_mii_ctrl_rr(ag);
451 t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
452 t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
453 ag71xx_mii_ctrl_wr(ag, t);
454 }
455
456 #ifdef CONFIG_AG71XX_AR8216_SUPPORT
457 void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
458 int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
459 #else
460 static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
461 struct sk_buff *skb)
462 {
463 }
464
465 static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
466 struct sk_buff *skb)
467 {
468 return 0;
469 }
470 #endif
471
472 #ifdef CONFIG_AG71XX_DEBUG_FS
473 int ag71xx_debugfs_root_init(void);
474 void ag71xx_debugfs_root_exit(void);
475 int ag71xx_debugfs_init(struct ag71xx *ag);
476 void ag71xx_debugfs_exit(struct ag71xx *ag);
477 void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
478 void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
479 #else
480 static inline int ag71xx_debugfs_root_init(void) { return 0; }
481 static inline void ag71xx_debugfs_root_exit(void) {}
482 static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
483 static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
484 static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
485 u32 status) {}
486 static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
487 int rx, int tx) {}
488 #endif /* CONFIG_AG71XX_DEBUG_FS */
489
490 #endif /* _AG71XX_H */
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