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[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/phy.h>
29 #include <linux/skbuff.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32
33 #include <linux/bitops.h>
34
35 #include <asm/mach-ar71xx/ar71xx.h>
36 #include <asm/mach-ar71xx/platform.h>
37
38 #define ETH_FCS_LEN 4
39
40 #define AG71XX_DRV_NAME "ag71xx"
41 #define AG71XX_DRV_VERSION "0.5.25"
42
43 #define AG71XX_NAPI_WEIGHT 64
44 #define AG71XX_OOM_REFILL (1 + HZ/10)
45
46 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
47 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
48 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
49
50 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
51 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
52
53 #define AG71XX_TX_FIFO_LEN 2048
54 #define AG71XX_TX_MTU_LEN 1536
55 #define AG71XX_RX_PKT_RESERVE 64
56 #define AG71XX_RX_PKT_SIZE \
57 (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
58
59 #define AG71XX_TX_RING_SIZE 64
60 #define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4)
61 #define AG71XX_TX_THRES_WAKEUP \
62 (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
63
64 #define AG71XX_RX_RING_SIZE 128
65
66 #ifdef CONFIG_AG71XX_DEBUG
67 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
68 #else
69 #define DBG(fmt, args...) do {} while (0)
70 #endif
71
72 #define ag71xx_assert(_cond) \
73 do { \
74 if (_cond) \
75 break; \
76 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
77 BUG(); \
78 } while (0)
79
80 struct ag71xx_desc {
81 u32 data;
82 u32 ctrl;
83 #define DESC_EMPTY BIT(31)
84 #define DESC_MORE BIT(24)
85 #define DESC_PKTLEN_M 0xfff
86 u32 next;
87 u32 pad;
88 } __attribute__((aligned(4)));
89
90 struct ag71xx_buf {
91 struct sk_buff *skb;
92 struct ag71xx_desc *desc;
93 };
94
95 struct ag71xx_ring {
96 struct ag71xx_buf *buf;
97 u8 *descs_cpu;
98 dma_addr_t descs_dma;
99 unsigned int desc_size;
100 unsigned int curr;
101 unsigned int dirty;
102 unsigned int size;
103 };
104
105 struct ag71xx_mdio {
106 struct mii_bus *mii_bus;
107 int mii_irq[PHY_MAX_ADDR];
108 void __iomem *mdio_base;
109 struct ag71xx_mdio_platform_data *pdata;
110 };
111
112 struct ag71xx_debug {
113 struct dentry *debugfs_dir;
114 };
115
116 struct ag71xx {
117 void __iomem *mac_base;
118 void __iomem *mii_ctrl;
119
120 spinlock_t lock;
121 struct platform_device *pdev;
122 struct net_device *dev;
123 struct napi_struct napi;
124 u32 msg_enable;
125
126 struct ag71xx_ring rx_ring;
127 struct ag71xx_ring tx_ring;
128
129 struct mii_bus *mii_bus;
130 struct phy_device *phy_dev;
131
132 unsigned int link;
133 unsigned int speed;
134 int duplex;
135
136 struct work_struct restart_work;
137 struct timer_list oom_timer;
138
139 #ifdef CONFIG_AG71XX_DEBUG_FS
140 struct ag71xx_debug debug;
141 #endif
142 };
143
144 extern struct ethtool_ops ag71xx_ethtool_ops;
145
146 int ag71xx_mdio_driver_init(void) __init;
147 void ag71xx_mdio_driver_exit(void);
148
149 int ag71xx_phy_connect(struct ag71xx *ag);
150 void ag71xx_phy_disconnect(struct ag71xx *ag);
151 void ag71xx_phy_start(struct ag71xx *ag);
152 void ag71xx_phy_stop(struct ag71xx *ag);
153
154 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
155 {
156 return ag->pdev->dev.platform_data;
157 }
158
159 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
160 {
161 return ((desc->ctrl & DESC_EMPTY) != 0);
162 }
163
164 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
165 {
166 return (desc->ctrl & DESC_PKTLEN_M);
167 }
168
169 /* Register offsets */
170 #define AG71XX_REG_MAC_CFG1 0x0000
171 #define AG71XX_REG_MAC_CFG2 0x0004
172 #define AG71XX_REG_MAC_IPG 0x0008
173 #define AG71XX_REG_MAC_HDX 0x000c
174 #define AG71XX_REG_MAC_MFL 0x0010
175 #define AG71XX_REG_MII_CFG 0x0020
176 #define AG71XX_REG_MII_CMD 0x0024
177 #define AG71XX_REG_MII_ADDR 0x0028
178 #define AG71XX_REG_MII_CTRL 0x002c
179 #define AG71XX_REG_MII_STATUS 0x0030
180 #define AG71XX_REG_MII_IND 0x0034
181 #define AG71XX_REG_MAC_IFCTL 0x0038
182 #define AG71XX_REG_MAC_ADDR1 0x0040
183 #define AG71XX_REG_MAC_ADDR2 0x0044
184 #define AG71XX_REG_FIFO_CFG0 0x0048
185 #define AG71XX_REG_FIFO_CFG1 0x004c
186 #define AG71XX_REG_FIFO_CFG2 0x0050
187 #define AG71XX_REG_FIFO_CFG3 0x0054
188 #define AG71XX_REG_FIFO_CFG4 0x0058
189 #define AG71XX_REG_FIFO_CFG5 0x005c
190 #define AG71XX_REG_FIFO_RAM0 0x0060
191 #define AG71XX_REG_FIFO_RAM1 0x0064
192 #define AG71XX_REG_FIFO_RAM2 0x0068
193 #define AG71XX_REG_FIFO_RAM3 0x006c
194 #define AG71XX_REG_FIFO_RAM4 0x0070
195 #define AG71XX_REG_FIFO_RAM5 0x0074
196 #define AG71XX_REG_FIFO_RAM6 0x0078
197 #define AG71XX_REG_FIFO_RAM7 0x007c
198
199 #define AG71XX_REG_TX_CTRL 0x0180
200 #define AG71XX_REG_TX_DESC 0x0184
201 #define AG71XX_REG_TX_STATUS 0x0188
202 #define AG71XX_REG_RX_CTRL 0x018c
203 #define AG71XX_REG_RX_DESC 0x0190
204 #define AG71XX_REG_RX_STATUS 0x0194
205 #define AG71XX_REG_INT_ENABLE 0x0198
206 #define AG71XX_REG_INT_STATUS 0x019c
207
208 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
209 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
210 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
211 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
212 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
213 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
214 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
215 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
216
217 #define MAC_CFG2_FDX BIT(0)
218 #define MAC_CFG2_CRC_EN BIT(1)
219 #define MAC_CFG2_PAD_CRC_EN BIT(2)
220 #define MAC_CFG2_LEN_CHECK BIT(4)
221 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
222 #define MAC_CFG2_IF_1000 BIT(9)
223 #define MAC_CFG2_IF_10_100 BIT(8)
224
225 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
226 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
227 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
228 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
229 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
230 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
231 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
232
233 #define FIFO_CFG0_ENABLE_SHIFT 8
234
235 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
236 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
237 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
238 #define FIFO_CFG4_CE BIT(3) /* Code Error */
239 #define FIFO_CFG4_CR BIT(4) /* CRC error */
240 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
241 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
242 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
243 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
244 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
245 #define FIFO_CFG4_DR BIT(10) /* Dribble */
246 #define FIFO_CFG4_LE BIT(11) /* Long Event */
247 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
248 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
249 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
250 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
251 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
252 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
253
254 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
255 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
256 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
257 #define FIFO_CFG5_CE BIT(3) /* Code Error */
258 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
259 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
260 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
261 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
262 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
263 #define FIFO_CFG5_DR BIT(9) /* Dribble */
264 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
265 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
266 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
267 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
268 #define FIFO_CFG5_LE BIT(14) /* Long Event */
269 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
270 #define FIFO_CFG5_16 BIT(16) /* unknown */
271 #define FIFO_CFG5_17 BIT(17) /* unknown */
272 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
273 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
274
275 #define AG71XX_INT_TX_PS BIT(0)
276 #define AG71XX_INT_TX_UR BIT(1)
277 #define AG71XX_INT_TX_BE BIT(3)
278 #define AG71XX_INT_RX_PR BIT(4)
279 #define AG71XX_INT_RX_OF BIT(6)
280 #define AG71XX_INT_RX_BE BIT(7)
281
282 #define MAC_IFCTL_SPEED BIT(16)
283
284 #define MII_CFG_CLK_DIV_4 0
285 #define MII_CFG_CLK_DIV_6 2
286 #define MII_CFG_CLK_DIV_8 3
287 #define MII_CFG_CLK_DIV_10 4
288 #define MII_CFG_CLK_DIV_14 5
289 #define MII_CFG_CLK_DIV_20 6
290 #define MII_CFG_CLK_DIV_28 7
291 #define MII_CFG_RESET BIT(31)
292
293 #define MII_CMD_WRITE 0x0
294 #define MII_CMD_READ 0x1
295 #define MII_ADDR_SHIFT 8
296 #define MII_IND_BUSY BIT(0)
297 #define MII_IND_INVALID BIT(2)
298
299 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
300
301 #define TX_STATUS_PS BIT(0) /* Packet Sent */
302 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
303 #define TX_STATUS_BE BIT(3) /* Bus Error */
304
305 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
306
307 #define RX_STATUS_PR BIT(0) /* Packet Received */
308 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
309 #define RX_STATUS_BE BIT(3) /* Bus Error */
310
311 #define MII_CTRL_IF_MASK 3
312 #define MII_CTRL_SPEED_SHIFT 4
313 #define MII_CTRL_SPEED_MASK 3
314 #define MII_CTRL_SPEED_10 0
315 #define MII_CTRL_SPEED_100 1
316 #define MII_CTRL_SPEED_1000 2
317
318 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
319 {
320 void __iomem *r;
321
322 switch (reg) {
323 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
324 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
325 r = ag->mac_base + reg;
326 __raw_writel(value, r);
327
328 /* flush write */
329 (void) __raw_readl(r);
330 break;
331 default:
332 BUG();
333 }
334 }
335
336 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
337 {
338 void __iomem *r;
339 u32 ret;
340
341 switch (reg) {
342 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
343 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
344 r = ag->mac_base + reg;
345 ret = __raw_readl(r);
346 break;
347 default:
348 BUG();
349 }
350
351 return ret;
352 }
353
354 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
355 {
356 void __iomem *r;
357
358 switch (reg) {
359 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
360 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
361 r = ag->mac_base + reg;
362 __raw_writel(__raw_readl(r) | mask, r);
363
364 /* flush write */
365 (void)__raw_readl(r);
366 break;
367 default:
368 BUG();
369 }
370 }
371
372 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
373 {
374 void __iomem *r;
375
376 switch (reg) {
377 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
378 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
379 r = ag->mac_base + reg;
380 __raw_writel(__raw_readl(r) & ~mask, r);
381
382 /* flush write */
383 (void) __raw_readl(r);
384 break;
385 default:
386 BUG();
387 }
388 }
389
390 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
391 {
392 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
393 }
394
395 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
396 {
397 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
398 }
399
400 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
401 {
402 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
403
404 if (pdata->is_ar724x)
405 return;
406
407 __raw_writel(value, ag->mii_ctrl);
408
409 /* flush write */
410 __raw_readl(ag->mii_ctrl);
411 }
412
413 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
414 {
415 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
416
417 if (pdata->is_ar724x)
418 return 0xffffffff;
419
420 return __raw_readl(ag->mii_ctrl);
421 }
422
423 static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
424 unsigned int mii_if)
425 {
426 u32 t;
427
428 t = ag71xx_mii_ctrl_rr(ag);
429 t &= ~(MII_CTRL_IF_MASK);
430 t |= (mii_if & MII_CTRL_IF_MASK);
431 ag71xx_mii_ctrl_wr(ag, t);
432 }
433
434 static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
435 unsigned int speed)
436 {
437 u32 t;
438
439 t = ag71xx_mii_ctrl_rr(ag);
440 t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
441 t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
442 ag71xx_mii_ctrl_wr(ag, t);
443 }
444
445 #ifdef CONFIG_AG71XX_AR8216_SUPPORT
446 void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
447 int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
448 #else
449 static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
450 struct sk_buff *skb)
451 {
452 }
453
454 static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
455 struct sk_buff *skb)
456 {
457 return 0;
458 }
459 #endif
460
461 #ifdef CONFIG_AG71XX_DEBUG_FS
462 int ag71xx_debugfs_root_init(void);
463 void ag71xx_debugfs_root_exit(void);
464 int ag71xx_debugfs_init(struct ag71xx *ag);
465 void ag71xx_debugfs_exit(struct ag71xx *ag);
466 #else
467 static inline int ag71xx_debugfs_root_init(void) { return 0; }
468 static inline void ag71xx_debugfs_root_exit(void) {}
469 static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
470 static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
471 #endif /* CONFIG_AG71XX_DEBUG_FS */
472
473 #endif /* _AG71XX_H */
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