d5f7743d4ca0508e633279a02e16841ae3481772
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/phy.h>
29 #include <linux/skbuff.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32
33 #include <linux/bitops.h>
34
35 #include <asm/mach-ar71xx/ar71xx.h>
36 #include <asm/mach-ar71xx/platform.h>
37
38 #define ETH_FCS_LEN 4
39
40 #define AG71XX_DRV_NAME "ag71xx"
41 #define AG71XX_DRV_VERSION "0.5.11"
42
43 #define AG71XX_NAPI_WEIGHT 64
44
45 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
46 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
47 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
48
49 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
50 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
51
52 #define AG71XX_TX_FIFO_LEN 2048
53 #define AG71XX_TX_MTU_LEN 1536
54 #define AG71XX_RX_PKT_RESERVE 64
55 #define AG71XX_RX_PKT_SIZE \
56 (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN)
57
58 #define AG71XX_TX_RING_SIZE 64
59 #define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4)
60 #define AG71XX_TX_THRES_WAKEUP \
61 (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4))
62
63 #define AG71XX_RX_RING_SIZE 128
64
65 #undef AG71XX_DEBUG
66 #ifdef AG71XX_DEBUG
67 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
68 #else
69 #define DBG(fmt, args...) do {} while (0)
70 #endif
71
72 #define ag71xx_assert(_cond) \
73 do { \
74 if (_cond) \
75 break; \
76 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
77 BUG(); \
78 } while (0)
79
80 struct ag71xx_desc {
81 u32 data;
82 u32 ctrl;
83 #define DESC_EMPTY BIT(31)
84 #define DESC_MORE BIT(24)
85 #define DESC_PKTLEN_M 0x1fff
86 u32 next;
87 };
88
89 struct ag71xx_buf {
90 struct sk_buff *skb;
91 };
92
93 struct ag71xx_ring {
94 struct ag71xx_buf *buf;
95 struct ag71xx_desc *descs;
96 dma_addr_t descs_dma;
97 unsigned int curr;
98 unsigned int dirty;
99 unsigned int size;
100 };
101
102 struct ag71xx_mdio {
103 struct mii_bus mii_bus;
104 int mii_irq[PHY_MAX_ADDR];
105 void __iomem *mdio_base;
106 };
107
108 struct ag71xx {
109 void __iomem *mac_base;
110 void __iomem *mac_base2;
111 void __iomem *mii_ctrl;
112
113 spinlock_t lock;
114 struct platform_device *pdev;
115 struct net_device *dev;
116 struct napi_struct napi;
117 u32 msg_enable;
118
119 struct ag71xx_ring rx_ring;
120 struct ag71xx_ring tx_ring;
121
122 struct mii_bus *mii_bus;
123 struct phy_device *phy_dev;
124
125 unsigned int link;
126 unsigned int speed;
127 int duplex;
128
129 struct work_struct restart_work;
130 };
131
132 extern struct ethtool_ops ag71xx_ethtool_ops;
133
134 extern struct ag71xx_mdio *ag71xx_mdio_bus;
135 extern int ag71xx_mdio_driver_init(void) __init;
136 extern void ag71xx_mdio_driver_exit(void);
137
138 extern int ag71xx_phy_connect(struct ag71xx *ag);
139 extern void ag71xx_phy_disconnect(struct ag71xx *ag);
140 extern void ag71xx_phy_start(struct ag71xx *ag);
141 extern void ag71xx_phy_stop(struct ag71xx *ag);
142
143 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
144 {
145 return ag->pdev->dev.platform_data;
146 }
147
148 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
149 {
150 return ((desc->ctrl & DESC_EMPTY) != 0);
151 }
152
153 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
154 {
155 return (desc->ctrl & DESC_PKTLEN_M);
156 }
157
158 /* Register offsets */
159 #define AG71XX_REG_MAC_CFG1 0x0000
160 #define AG71XX_REG_MAC_CFG2 0x0004
161 #define AG71XX_REG_MAC_IPG 0x0008
162 #define AG71XX_REG_MAC_HDX 0x000c
163 #define AG71XX_REG_MAC_MFL 0x0010
164 #define AG71XX_REG_MII_CFG 0x0020
165 #define AG71XX_REG_MII_CMD 0x0024
166 #define AG71XX_REG_MII_ADDR 0x0028
167 #define AG71XX_REG_MII_CTRL 0x002c
168 #define AG71XX_REG_MII_STATUS 0x0030
169 #define AG71XX_REG_MII_IND 0x0034
170 #define AG71XX_REG_MAC_IFCTL 0x0038
171 #define AG71XX_REG_MAC_ADDR1 0x0040
172 #define AG71XX_REG_MAC_ADDR2 0x0044
173 #define AG71XX_REG_FIFO_CFG0 0x0048
174 #define AG71XX_REG_FIFO_CFG1 0x004c
175 #define AG71XX_REG_FIFO_CFG2 0x0050
176 #define AG71XX_REG_FIFO_CFG3 0x0054
177 #define AG71XX_REG_FIFO_CFG4 0x0058
178 #define AG71XX_REG_FIFO_CFG5 0x005c
179 #define AG71XX_REG_FIFO_RAM0 0x0060
180 #define AG71XX_REG_FIFO_RAM1 0x0064
181 #define AG71XX_REG_FIFO_RAM2 0x0068
182 #define AG71XX_REG_FIFO_RAM3 0x006c
183 #define AG71XX_REG_FIFO_RAM4 0x0070
184 #define AG71XX_REG_FIFO_RAM5 0x0074
185 #define AG71XX_REG_FIFO_RAM6 0x0078
186 #define AG71XX_REG_FIFO_RAM7 0x007c
187
188 #define AG71XX_REG_TX_CTRL 0x0180
189 #define AG71XX_REG_TX_DESC 0x0184
190 #define AG71XX_REG_TX_STATUS 0x0188
191 #define AG71XX_REG_RX_CTRL 0x018c
192 #define AG71XX_REG_RX_DESC 0x0190
193 #define AG71XX_REG_RX_STATUS 0x0194
194 #define AG71XX_REG_INT_ENABLE 0x0198
195 #define AG71XX_REG_INT_STATUS 0x019c
196
197 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
198 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
199 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
200 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
201 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
202 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
203 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
204 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
205
206 #define MAC_CFG2_FDX BIT(0)
207 #define MAC_CFG2_CRC_EN BIT(1)
208 #define MAC_CFG2_PAD_CRC_EN BIT(2)
209 #define MAC_CFG2_LEN_CHECK BIT(4)
210 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
211 #define MAC_CFG2_IF_1000 BIT(9)
212 #define MAC_CFG2_IF_10_100 BIT(8)
213
214 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
215 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
216 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
217 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
218 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
219 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
220 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
221
222 #define FIFO_CFG0_ENABLE_SHIFT 8
223
224 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
225 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
226 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
227 #define FIFO_CFG4_CE BIT(3) /* Code Error */
228 #define FIFO_CFG4_CRC BIT(4) /* CRC error */
229 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
230 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
231 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
232 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
233 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
234 #define FIFO_CFG4_DR BIT(10) /* Dribble */
235 #define FIFO_CFG4_LE BIT(11) /* Long Event */
236 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
237 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
238 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
239 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
240 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
241 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
242
243 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
244 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
245 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
246 #define FIFO_CFG5_CE BIT(3) /* Code Error */
247 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
248 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
249 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
250 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
251 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
252 #define FIFO_CFG5_DR BIT(9) /* Dribble */
253 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
254 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
255 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
256 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
257 #define FIFO_CFG5_LE BIT(14) /* Long Event */
258 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
259 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
260 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
261
262 #define AG71XX_INT_TX_PS BIT(0)
263 #define AG71XX_INT_TX_UR BIT(1)
264 #define AG71XX_INT_TX_BE BIT(3)
265 #define AG71XX_INT_RX_PR BIT(4)
266 #define AG71XX_INT_RX_OF BIT(6)
267 #define AG71XX_INT_RX_BE BIT(7)
268
269 #define MAC_IFCTL_SPEED BIT(16)
270
271 #define MII_CFG_CLK_DIV_4 0
272 #define MII_CFG_CLK_DIV_6 2
273 #define MII_CFG_CLK_DIV_8 3
274 #define MII_CFG_CLK_DIV_10 4
275 #define MII_CFG_CLK_DIV_14 5
276 #define MII_CFG_CLK_DIV_20 6
277 #define MII_CFG_CLK_DIV_28 7
278 #define MII_CFG_RESET BIT(31)
279
280 #define MII_CMD_WRITE 0x0
281 #define MII_CMD_READ 0x1
282 #define MII_ADDR_SHIFT 8
283 #define MII_IND_BUSY BIT(0)
284 #define MII_IND_INVALID BIT(2)
285
286 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
287
288 #define TX_STATUS_PS BIT(0) /* Packet Sent */
289 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
290 #define TX_STATUS_BE BIT(3) /* Bus Error */
291
292 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
293
294 #define RX_STATUS_PR BIT(0) /* Packet Received */
295 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
296 #define RX_STATUS_BE BIT(3) /* Bus Error */
297
298 #define MII_CTRL_IF_MASK 3
299 #define MII_CTRL_SPEED_SHIFT 4
300 #define MII_CTRL_SPEED_MASK 3
301 #define MII_CTRL_SPEED_10 0
302 #define MII_CTRL_SPEED_100 1
303 #define MII_CTRL_SPEED_1000 2
304
305 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
306 {
307 void __iomem *r;
308
309 switch (reg) {
310 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
311 r = ag->mac_base + reg;
312 __raw_writel(value, r);
313 __raw_readl(r);
314 break;
315 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
316 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
317 __raw_writel(value, r);
318 __raw_readl(r);
319 break;
320 default:
321 BUG();
322 }
323 }
324
325 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
326 {
327 void __iomem *r;
328 u32 ret;
329
330 switch (reg) {
331 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
332 r = ag->mac_base + reg;
333 ret = __raw_readl(r);
334 break;
335 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
336 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
337 ret = __raw_readl(r);
338 break;
339 default:
340 BUG();
341 }
342
343 return ret;
344 }
345
346 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
347 {
348 void __iomem *r;
349
350 switch (reg) {
351 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
352 r = ag->mac_base + reg;
353 __raw_writel(__raw_readl(r) | mask, r);
354 __raw_readl(r);
355 break;
356 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
357 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
358 __raw_writel(__raw_readl(r) | mask, r);
359 __raw_readl(r);
360 break;
361 default:
362 BUG();
363 }
364 }
365
366 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
367 {
368 void __iomem *r;
369
370 switch (reg) {
371 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
372 r = ag->mac_base + reg;
373 __raw_writel(__raw_readl(r) & ~mask, r);
374 __raw_readl(r);
375 break;
376 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
377 r = ag->mac_base2 + reg - AG71XX_REG_MAC_IFCTL;
378 __raw_writel(__raw_readl(r) & ~mask, r);
379 __raw_readl(r);
380 break;
381 default:
382 BUG();
383 }
384 }
385
386 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
387 {
388 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
389 }
390
391 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
392 {
393 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
394 }
395
396 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
397 {
398 __raw_writel(value, ag->mii_ctrl);
399 __raw_readl(ag->mii_ctrl);
400 }
401
402 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
403 {
404 return __raw_readl(ag->mii_ctrl);
405 }
406
407 static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
408 unsigned int mii_if)
409 {
410 u32 t;
411
412 t = ag71xx_mii_ctrl_rr(ag);
413 t &= ~(MII_CTRL_IF_MASK);
414 t |= (mii_if & MII_CTRL_IF_MASK);
415 ag71xx_mii_ctrl_wr(ag, t);
416 }
417
418 static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
419 unsigned int speed)
420 {
421 u32 t;
422
423 t = ag71xx_mii_ctrl_rr(ag);
424 t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
425 t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
426 ag71xx_mii_ctrl_wr(ag, t);
427 }
428
429 #endif /* _AG71XX_H */