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[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
29
30 #define AR7240_REG_MAC_ADDR0 0x20
31 #define AR7240_REG_MAC_ADDR1 0x24
32
33 #define AR7240_REG_FLOOD_MASK 0x2c
34 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
35
36 #define AR7240_REG_GLOBAL_CTRL 0x30
37 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
38
39 #define AR7240_REG_VTU 0x0040
40 #define AR7240_VTU_OP BITM(3)
41 #define AR7240_VTU_OP_NOOP 0x0
42 #define AR7240_VTU_OP_FLUSH 0x1
43 #define AR7240_VTU_OP_LOAD 0x2
44 #define AR7240_VTU_OP_PURGE 0x3
45 #define AR7240_VTU_OP_REMOVE_PORT 0x4
46 #define AR7240_VTU_ACTIVE BIT(3)
47 #define AR7240_VTU_FULL BIT(4)
48 #define AR7240_VTU_PORT BITS(8, 4)
49 #define AR7240_VTU_PORT_S 8
50 #define AR7240_VTU_VID BITS(16, 12)
51 #define AR7240_VTU_VID_S 16
52 #define AR7240_VTU_PRIO BITS(28, 3)
53 #define AR7240_VTU_PRIO_S 28
54 #define AR7240_VTU_PRIO_EN BIT(31)
55
56 #define AR7240_REG_VTU_DATA 0x0044
57 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
58 #define AR7240_VTUDATA_VALID BIT(11)
59
60 #define AR7240_REG_ATU 0x50
61 #define AR7240_ATU_FLUSH_ALL 0x1
62
63 #define AR7240_REG_AT_CTRL 0x5c
64 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
65 #define AR7240_AT_CTRL_AGE_EN BIT(17)
66 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
67 #define AR7240_AT_CTRL_ARP_EN BIT(20)
68
69 #define AR7240_REG_TAG_PRIORITY 0x70
70
71 #define AR7240_REG_SERVICE_TAG 0x74
72 #define AR7240_SERVICE_TAG_M BITM(16)
73
74 #define AR7240_REG_CPU_PORT 0x78
75 #define AR7240_MIRROR_PORT_S 4
76 #define AR7240_CPU_PORT_EN BIT(8)
77
78 #define AR7240_REG_MIB_FUNCTION0 0x80
79 #define AR7240_MIB_TIMER_M BITM(16)
80 #define AR7240_MIB_AT_HALF_EN BIT(16)
81 #define AR7240_MIB_BUSY BIT(17)
82 #define AR7240_MIB_FUNC_S 24
83 #define AR7240_MIB_FUNC_NO_OP 0x0
84 #define AR7240_MIB_FUNC_FLUSH 0x1
85 #define AR7240_MIB_FUNC_CAPTURE 0x3
86
87 #define AR7240_REG_MDIO_CTRL 0x98
88 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
89 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
90 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
91 #define AR7240_MDIO_CTRL_CMD_WRITE 0
92 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
93 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
94 #define AR7240_MDIO_CTRL_BUSY BIT(31)
95
96 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
97
98 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
99 #define AR7240_PORT_STATUS_SPEED_S 0
100 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
101 #define AR7240_PORT_STATUS_SPEED_10 0
102 #define AR7240_PORT_STATUS_SPEED_100 1
103 #define AR7240_PORT_STATUS_SPEED_1000 2
104 #define AR7240_PORT_STATUS_TXMAC BIT(2)
105 #define AR7240_PORT_STATUS_RXMAC BIT(3)
106 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
107 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
108 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
109 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
110 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
111 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
112
113 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
114 #define AR7240_PORT_CTRL_STATE_M BITM(3)
115 #define AR7240_PORT_CTRL_STATE_DISABLED 0
116 #define AR7240_PORT_CTRL_STATE_BLOCK 1
117 #define AR7240_PORT_CTRL_STATE_LISTEN 2
118 #define AR7240_PORT_CTRL_STATE_LEARN 3
119 #define AR7240_PORT_CTRL_STATE_FORWARD 4
120 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
121 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
122 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
123 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
124 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
125 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
126 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
127 #define AR7240_PORT_CTRL_HEADER BIT(11)
128 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
129 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
130 #define AR7240_PORT_CTRL_LEARN BIT(14)
131 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
132 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
133 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
134
135 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
136
137 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
138 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
139 #define AR7240_PORT_VLAN_MODE_S 30
140 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
141 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
142 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
143 #define AR7240_PORT_VLAN_MODE_SECURE 3
144
145
146 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
147
148 #define AR7240_STATS_RXBROAD 0x00
149 #define AR7240_STATS_RXPAUSE 0x04
150 #define AR7240_STATS_RXMULTI 0x08
151 #define AR7240_STATS_RXFCSERR 0x0c
152 #define AR7240_STATS_RXALIGNERR 0x10
153 #define AR7240_STATS_RXRUNT 0x14
154 #define AR7240_STATS_RXFRAGMENT 0x18
155 #define AR7240_STATS_RX64BYTE 0x1c
156 #define AR7240_STATS_RX128BYTE 0x20
157 #define AR7240_STATS_RX256BYTE 0x24
158 #define AR7240_STATS_RX512BYTE 0x28
159 #define AR7240_STATS_RX1024BYTE 0x2c
160 #define AR7240_STATS_RX1518BYTE 0x30
161 #define AR7240_STATS_RXMAXBYTE 0x34
162 #define AR7240_STATS_RXTOOLONG 0x38
163 #define AR7240_STATS_RXGOODBYTE 0x3c
164 #define AR7240_STATS_RXBADBYTE 0x44
165 #define AR7240_STATS_RXOVERFLOW 0x4c
166 #define AR7240_STATS_FILTERED 0x50
167 #define AR7240_STATS_TXBROAD 0x54
168 #define AR7240_STATS_TXPAUSE 0x58
169 #define AR7240_STATS_TXMULTI 0x5c
170 #define AR7240_STATS_TXUNDERRUN 0x60
171 #define AR7240_STATS_TX64BYTE 0x64
172 #define AR7240_STATS_TX128BYTE 0x68
173 #define AR7240_STATS_TX256BYTE 0x6c
174 #define AR7240_STATS_TX512BYTE 0x70
175 #define AR7240_STATS_TX1024BYTE 0x74
176 #define AR7240_STATS_TX1518BYTE 0x78
177 #define AR7240_STATS_TXMAXBYTE 0x7c
178 #define AR7240_STATS_TXOVERSIZE 0x80
179 #define AR7240_STATS_TXBYTE 0x84
180 #define AR7240_STATS_TXCOLLISION 0x8c
181 #define AR7240_STATS_TXABORTCOL 0x90
182 #define AR7240_STATS_TXMULTICOL 0x94
183 #define AR7240_STATS_TXSINGLECOL 0x98
184 #define AR7240_STATS_TXEXCDEFER 0x9c
185 #define AR7240_STATS_TXDEFER 0xa0
186 #define AR7240_STATS_TXLATECOL 0xa4
187
188 #define AR7240_PORT_CPU 0
189 #define AR7240_NUM_PORTS 6
190 #define AR7240_NUM_PHYS 5
191
192 #define AR7240_PHY_ID1 0x004d
193 #define AR7240_PHY_ID2 0xd041
194
195 #define AR7240_PORT_MASK(_port) BIT((_port))
196 #define AR7240_PORT_MASK_ALL BITM(AR7240_NUM_PORTS)
197 #define AR7240_PORT_MASK_BUT(_port) (AR7240_PORT_MASK_ALL & ~BIT((_port)))
198
199 #define AR7240_MAX_VLANS 16
200
201 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
202
203 struct ar7240sw {
204 struct mii_bus *mii_bus;
205 struct switch_dev swdev;
206 bool vlan;
207 u16 vlan_id[AR7240_MAX_VLANS];
208 u8 vlan_table[AR7240_MAX_VLANS];
209 u8 vlan_tagged;
210 u16 pvid[AR7240_NUM_PORTS];
211 char buf[80];
212 };
213
214 struct ar7240sw_hw_stat {
215 char string[ETH_GSTRING_LEN];
216 int sizeof_stat;
217 int reg;
218 };
219
220 static DEFINE_MUTEX(reg_mutex);
221
222 static inline u16 mk_phy_addr(u32 reg)
223 {
224 return 0x17 & ((reg >> 4) | 0x10);
225 }
226
227 static inline u16 mk_phy_reg(u32 reg)
228 {
229 return (reg << 1) & 0x1e;
230 }
231
232 static inline u16 mk_high_addr(u32 reg)
233 {
234 return (reg >> 7) & 0x1ff;
235 }
236
237 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
238 {
239 unsigned long flags;
240 u16 phy_addr;
241 u16 phy_reg;
242 u32 hi, lo;
243
244 reg = (reg & 0xfffffffc) >> 2;
245 phy_addr = mk_phy_addr(reg);
246 phy_reg = mk_phy_reg(reg);
247
248 local_irq_save(flags);
249 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
250 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
251 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
252 local_irq_restore(flags);
253
254 return (hi << 16) | lo;
255 }
256
257 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
258 {
259 unsigned long flags;
260 u16 phy_addr;
261 u16 phy_reg;
262
263 reg = (reg & 0xfffffffc) >> 2;
264 phy_addr = mk_phy_addr(reg);
265 phy_reg = mk_phy_reg(reg);
266
267 local_irq_save(flags);
268 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
269 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
270 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
271 local_irq_restore(flags);
272 }
273
274 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
275 {
276 u32 ret;
277
278 mutex_lock(&reg_mutex);
279 ret = __ar7240sw_reg_read(mii, reg_addr);
280 mutex_unlock(&reg_mutex);
281
282 return ret;
283 }
284
285 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
286 {
287 mutex_lock(&reg_mutex);
288 __ar7240sw_reg_write(mii, reg_addr, reg_val);
289 mutex_unlock(&reg_mutex);
290 }
291
292 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
293 {
294 u32 t;
295
296 mutex_lock(&reg_mutex);
297 t = __ar7240sw_reg_read(mii, reg);
298 t &= ~mask;
299 t |= val;
300 __ar7240sw_reg_write(mii, reg, t);
301 mutex_unlock(&reg_mutex);
302
303 return t;
304 }
305
306 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
307 {
308 u32 t;
309
310 mutex_lock(&reg_mutex);
311 t = __ar7240sw_reg_read(mii, reg);
312 t |= val;
313 __ar7240sw_reg_write(mii, reg, t);
314 mutex_unlock(&reg_mutex);
315 }
316
317 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
318 unsigned timeout)
319 {
320 int i;
321
322 for (i = 0; i < timeout; i++) {
323 u32 t;
324
325 t = __ar7240sw_reg_read(mii, reg);
326 if ((t & mask) == val)
327 return 0;
328
329 msleep(1);
330 }
331
332 return -ETIMEDOUT;
333 }
334
335 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
336 unsigned timeout)
337 {
338 int ret;
339
340 mutex_lock(&reg_mutex);
341 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
342 mutex_unlock(&reg_mutex);
343 return ret;
344 }
345
346 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
347 unsigned reg_addr)
348 {
349 u32 t, val = 0xffff;
350 int err;
351
352 if (phy_addr >= AR7240_NUM_PHYS)
353 return 0xffff;
354
355 mutex_lock(&reg_mutex);
356 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
357 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
358 AR7240_MDIO_CTRL_MASTER_EN |
359 AR7240_MDIO_CTRL_BUSY |
360 AR7240_MDIO_CTRL_CMD_READ;
361
362 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
363 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
364 AR7240_MDIO_CTRL_BUSY, 0, 5);
365 if (!err)
366 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
367 mutex_unlock(&reg_mutex);
368
369 return val & AR7240_MDIO_CTRL_DATA_M;
370 }
371
372 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
373 unsigned reg_addr, u16 reg_val)
374 {
375 u32 t;
376 int ret;
377
378 if (phy_addr >= AR7240_NUM_PHYS)
379 return -EINVAL;
380
381 mutex_lock(&reg_mutex);
382 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
383 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
384 AR7240_MDIO_CTRL_MASTER_EN |
385 AR7240_MDIO_CTRL_BUSY |
386 AR7240_MDIO_CTRL_CMD_WRITE |
387 reg_val;
388
389 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
390 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
391 AR7240_MDIO_CTRL_BUSY, 0, 5);
392 mutex_unlock(&reg_mutex);
393
394 return ret;
395 }
396
397 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
398 {
399 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
400 AR7240_PORT_CTRL_STATE_DISABLED);
401 }
402
403 static void ar7240sw_setup(struct ar7240sw *as)
404 {
405 struct mii_bus *mii = as->mii_bus;
406
407 /* Enable CPU port, and disable mirror port */
408 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
409 AR7240_CPU_PORT_EN |
410 (15 << AR7240_MIRROR_PORT_S));
411
412 /* Setup TAG priority mapping */
413 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
414
415 /* Enable ARP frame acknowledge, aging, MAC replacing */
416 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
417 0x2b /* 5 min age time */ |
418 AR7240_AT_CTRL_AGE_EN |
419 AR7240_AT_CTRL_ARP_EN |
420 AR7240_AT_CTRL_LEARN_CHANGE);
421
422 /* Enable Broadcast frames transmitted to the CPU */
423 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
424 AR7240_FLOOD_MASK_BROAD_TO_CPU);
425
426 /* setup MTU */
427 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
428 1536);
429
430 /* setup Service TAG */
431 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
432 }
433
434 static int ar7240sw_reset(struct ar7240sw *as)
435 {
436 struct mii_bus *mii = as->mii_bus;
437 int ret;
438 int i;
439
440 /* Set all ports to disabled state. */
441 for (i = 0; i < AR7240_NUM_PORTS; i++)
442 ar7240sw_disable_port(as, i);
443
444 /* Wait for transmit queues to drain. */
445 msleep(2);
446
447 /* Reset the switch. */
448 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
449 AR7240_MASK_CTRL_SOFT_RESET);
450
451 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
452 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
453
454 ar7240sw_setup(as);
455 return ret;
456 }
457
458 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
459 {
460 struct mii_bus *mii = as->mii_bus;
461 u32 ctrl;
462 u32 vlan;
463
464 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
465 AR7240_PORT_CTRL_SINGLE_VLAN;
466
467 if (port == AR7240_PORT_CPU) {
468 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
469 AR7240_PORT_STATUS_SPEED_1000 |
470 AR7240_PORT_STATUS_TXFLOW |
471 AR7240_PORT_STATUS_RXFLOW |
472 AR7240_PORT_STATUS_TXMAC |
473 AR7240_PORT_STATUS_RXMAC |
474 AR7240_PORT_STATUS_DUPLEX);
475 } else {
476 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
477 AR7240_PORT_STATUS_LINK_AUTO);
478 }
479
480 /* Set the default VID for this port */
481 if (as->vlan) {
482 vlan = as->vlan_id[as->pvid[port]];
483 vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
484 AR7240_PORT_VLAN_MODE_S;
485 } else {
486 vlan = port;
487 vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
488 AR7240_PORT_VLAN_MODE_S;
489 }
490
491 if (as->vlan && (as->vlan_tagged & BIT(port))) {
492 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
493 AR7240_PORT_CTRL_VLAN_MODE_S;
494 } else {
495 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
496 AR7240_PORT_CTRL_VLAN_MODE_S;
497 }
498
499 if (!portmask) {
500 if (port == AR7240_PORT_CPU)
501 portmask = AR7240_PORT_MASK_BUT(AR7240_PORT_CPU);
502 else
503 portmask = AR7240_PORT_MASK(AR7240_PORT_CPU);
504 }
505
506 /* allow the port to talk to all other ports, but exclude its
507 * own ID to prevent frames from being reflected back to the
508 * port that they came from */
509 portmask &= AR7240_PORT_MASK_BUT(port);
510
511 /* set default VID and and destination ports for this VLAN */
512 vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
513
514 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
515 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
516 }
517
518 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
519 {
520 struct mii_bus *mii = as->mii_bus;
521 u32 t;
522
523 t = (addr[4] << 8) | addr[5];
524 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
525
526 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
527 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
528
529 return 0;
530 }
531
532 static int
533 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
534 struct switch_val *val)
535 {
536 struct ar7240sw *as = sw_to_ar7240(dev);
537 as->vlan_id[val->port_vlan] = val->value.i;
538 return 0;
539 }
540
541 static int
542 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
543 struct switch_val *val)
544 {
545 struct ar7240sw *as = sw_to_ar7240(dev);
546 val->value.i = as->vlan_id[val->port_vlan];
547 return 0;
548 }
549
550 static int
551 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
552 {
553 struct ar7240sw *as = sw_to_ar7240(dev);
554
555 /* make sure no invalid PVIDs get set */
556
557 if (vlan >= dev->vlans)
558 return -EINVAL;
559
560 as->pvid[port] = vlan;
561 return 0;
562 }
563
564 static int
565 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
566 {
567 struct ar7240sw *as = sw_to_ar7240(dev);
568 *vlan = as->pvid[port];
569 return 0;
570 }
571
572 static int
573 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
574 {
575 struct ar7240sw *as = sw_to_ar7240(dev);
576 u8 ports = as->vlan_table[val->port_vlan];
577 int i;
578
579 val->len = 0;
580 for (i = 0; i < AR7240_NUM_PORTS; i++) {
581 struct switch_port *p;
582
583 if (!(ports & (1 << i)))
584 continue;
585
586 p = &val->value.ports[val->len++];
587 p->id = i;
588 if (as->vlan_tagged & (1 << i))
589 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
590 else
591 p->flags = 0;
592 }
593 return 0;
594 }
595
596 static int
597 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
598 {
599 struct ar7240sw *as = sw_to_ar7240(dev);
600 u8 *vt = &as->vlan_table[val->port_vlan];
601 int i, j;
602
603 *vt = 0;
604 for (i = 0; i < val->len; i++) {
605 struct switch_port *p = &val->value.ports[i];
606
607 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
608 as->vlan_tagged |= (1 << p->id);
609 else {
610 as->vlan_tagged &= ~(1 << p->id);
611 as->pvid[p->id] = val->port_vlan;
612
613 /* make sure that an untagged port does not
614 * appear in other vlans */
615 for (j = 0; j < AR7240_MAX_VLANS; j++) {
616 if (j == val->port_vlan)
617 continue;
618 as->vlan_table[j] &= ~(1 << p->id);
619 }
620 }
621
622 *vt |= 1 << p->id;
623 }
624 return 0;
625 }
626
627 static int
628 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
629 struct switch_val *val)
630 {
631 struct ar7240sw *as = sw_to_ar7240(dev);
632 as->vlan = !!val->value.i;
633 return 0;
634 }
635
636 static int
637 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
638 struct switch_val *val)
639 {
640 struct ar7240sw *as = sw_to_ar7240(dev);
641 val->value.i = as->vlan;
642 return 0;
643 }
644
645 static const char *
646 ar7240_speed_str(u32 status)
647 {
648 u32 speed;
649
650 speed = (status >> AR7240_PORT_STATUS_SPEED_S) &
651 AR7240_PORT_STATUS_SPEED_M;
652 switch (speed) {
653 case AR7240_PORT_STATUS_SPEED_10:
654 return "10baseT";
655 case AR7240_PORT_STATUS_SPEED_100:
656 return "100baseT";
657 case AR7240_PORT_STATUS_SPEED_1000:
658 return "1000baseT";
659 }
660
661 return "unknown";
662 }
663
664 static int
665 ar7240_port_get_link(struct switch_dev *dev, const struct switch_attr *attr,
666 struct switch_val *val)
667 {
668 struct ar7240sw *as = sw_to_ar7240(dev);
669 struct mii_bus *mii = as->mii_bus;
670 u32 len;
671 u32 status;
672 int port;
673
674 port = val->port_vlan;
675
676 memset(as->buf, '\0', sizeof(as->buf));
677 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
678
679 if (status & AR7240_PORT_STATUS_LINK_UP) {
680 len = snprintf(as->buf, sizeof(as->buf),
681 "port:%d link:up speed:%s %s-duplex %s%s%s",
682 port,
683 ar7240_speed_str(status),
684 (status & AR7240_PORT_STATUS_DUPLEX) ?
685 "full" : "half",
686 (status & AR7240_PORT_STATUS_TXFLOW) ?
687 "txflow ": "",
688 (status & AR7240_PORT_STATUS_RXFLOW) ?
689 "rxflow " : "",
690 (status & AR7240_PORT_STATUS_LINK_AUTO) ?
691 "auto ": "");
692 } else {
693 len = snprintf(as->buf, sizeof(as->buf),
694 "port:%d link:down", port);
695 }
696
697 val->value.s = as->buf;
698 val->len = len;
699
700 return 0;
701 }
702
703 static void
704 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
705 {
706 struct mii_bus *mii = as->mii_bus;
707
708 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
709 return;
710
711 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
712 val &= AR7240_VTUDATA_MEMBER;
713 val |= AR7240_VTUDATA_VALID;
714 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
715 }
716 op |= AR7240_VTU_ACTIVE;
717 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
718 }
719
720 static int
721 ar7240_hw_apply(struct switch_dev *dev)
722 {
723 struct ar7240sw *as = sw_to_ar7240(dev);
724 u8 portmask[AR7240_NUM_PORTS];
725 int i, j;
726
727 /* flush all vlan translation unit entries */
728 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
729
730 memset(portmask, 0, sizeof(portmask));
731 if (as->vlan) {
732 /* calculate the port destination masks and load vlans
733 * into the vlan translation unit */
734 for (j = 0; j < AR7240_MAX_VLANS; j++) {
735 u8 vp = as->vlan_table[j];
736
737 if (!vp)
738 continue;
739
740 for (i = 0; i < AR7240_NUM_PORTS; i++) {
741 u8 mask = (1 << i);
742 if (vp & mask)
743 portmask[i] |= vp & ~mask;
744 }
745
746 ar7240_vtu_op(as,
747 AR7240_VTU_OP_LOAD |
748 (as->vlan_id[j] << AR7240_VTU_VID_S),
749 as->vlan_table[j]);
750 }
751 } else {
752 /* vlan disabled:
753 * isolate all ports, but connect them to the cpu port */
754 for (i = 0; i < AR7240_NUM_PORTS; i++) {
755 if (i == AR7240_PORT_CPU)
756 continue;
757
758 portmask[i] = 1 << AR7240_PORT_CPU;
759 portmask[AR7240_PORT_CPU] |= (1 << i);
760 }
761 }
762
763 /* update the port destination mask registers and tag settings */
764 for (i = 0; i < AR7240_NUM_PORTS; i++)
765 ar7240sw_setup_port(as, i, portmask[i]);
766
767 return 0;
768 }
769
770 static int
771 ar7240_reset_switch(struct switch_dev *dev)
772 {
773 struct ar7240sw *as = sw_to_ar7240(dev);
774 ar7240sw_reset(as);
775 return 0;
776 }
777
778 static struct switch_attr ar7240_globals[] = {
779 {
780 .type = SWITCH_TYPE_INT,
781 .name = "enable_vlan",
782 .description = "Enable VLAN mode",
783 .set = ar7240_set_vlan,
784 .get = ar7240_get_vlan,
785 .max = 1
786 },
787 };
788
789 static struct switch_attr ar7240_port[] = {
790 {
791 .type = SWITCH_TYPE_STRING,
792 .name = "link",
793 .description = "Get port link information",
794 .max = 1,
795 .set = NULL,
796 .get = ar7240_port_get_link,
797 },
798 };
799
800 static struct switch_attr ar7240_vlan[] = {
801 {
802 .type = SWITCH_TYPE_INT,
803 .name = "vid",
804 .description = "VLAN ID",
805 .set = ar7240_set_vid,
806 .get = ar7240_get_vid,
807 .max = 4094,
808 },
809 };
810
811 static const struct switch_dev_ops ar7240_ops = {
812 .attr_global = {
813 .attr = ar7240_globals,
814 .n_attr = ARRAY_SIZE(ar7240_globals),
815 },
816 .attr_port = {
817 .attr = ar7240_port,
818 .n_attr = ARRAY_SIZE(ar7240_port),
819 },
820 .attr_vlan = {
821 .attr = ar7240_vlan,
822 .n_attr = ARRAY_SIZE(ar7240_vlan),
823 },
824 .get_port_pvid = ar7240_get_pvid,
825 .set_port_pvid = ar7240_set_pvid,
826 .get_vlan_ports = ar7240_get_ports,
827 .set_vlan_ports = ar7240_set_ports,
828 .apply_config = ar7240_hw_apply,
829 .reset_switch = ar7240_reset_switch,
830 };
831
832 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
833 {
834 struct mii_bus *mii = ag->mii_bus;
835 struct ar7240sw *as;
836 struct switch_dev *swdev;
837 u32 ctrl;
838 u16 phy_id1;
839 u16 phy_id2;
840 u8 ver;
841 int i;
842
843 as = kzalloc(sizeof(*as), GFP_KERNEL);
844 if (!as)
845 return NULL;
846
847 as->mii_bus = mii;
848
849 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
850
851 ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M;
852 if (ver != 1) {
853 pr_err("%s: unsupported chip, ctrl=%08x\n",
854 ag->dev->name, ctrl);
855 return NULL;
856 }
857
858 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
859 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
860 if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) {
861 pr_err("%s: unknown phy id '%04x:%04x'\n",
862 ag->dev->name, phy_id1, phy_id2);
863 return NULL;
864 }
865
866 swdev = &as->swdev;
867 swdev->name = "AR7240 built-in switch";
868 swdev->ports = AR7240_NUM_PORTS;
869 swdev->cpu_port = AR7240_PORT_CPU;
870 swdev->vlans = AR7240_MAX_VLANS;
871 swdev->ops = &ar7240_ops;
872
873 if (register_switch(&as->swdev, ag->dev) < 0) {
874 kfree(as);
875 return NULL;
876 }
877
878 pr_info("%s: Found an AR7240 built-in switch\n", ag->dev->name);
879
880 /* initialize defaults */
881 for (i = 0; i < AR7240_MAX_VLANS; i++)
882 as->vlan_id[i] = i;
883
884 as->vlan_table[0] = AR7240_PORT_MASK_ALL;
885
886 return as;
887 }
888
889 static void link_function(struct work_struct *work) {
890 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
891 unsigned long flags;
892 int i;
893 int status = 0;
894
895 for (i = 0; i < 4; i++) {
896 int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
897 if(link & BMSR_LSTATUS) {
898 status = 1;
899 break;
900 }
901 }
902
903 spin_lock_irqsave(&ag->lock, flags);
904 if(status != ag->link) {
905 ag->link = status;
906 ag71xx_link_adjust(ag);
907 }
908 spin_unlock_irqrestore(&ag->lock, flags);
909
910 schedule_delayed_work(&ag->link_work, HZ / 2);
911 }
912
913 void ag71xx_ar7240_start(struct ag71xx *ag)
914 {
915 struct ar7240sw *as = ag->phy_priv;
916
917 ar7240sw_reset(as);
918
919 ag->speed = SPEED_1000;
920 ag->duplex = 1;
921
922 ar7240_set_addr(as, ag->dev->dev_addr);
923 ar7240_hw_apply(&as->swdev);
924
925 schedule_delayed_work(&ag->link_work, HZ / 10);
926 }
927
928 void ag71xx_ar7240_stop(struct ag71xx *ag)
929 {
930 cancel_delayed_work_sync(&ag->link_work);
931 }
932
933 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
934 {
935 struct ar7240sw *as;
936
937 as = ar7240_probe(ag);
938 if (!as)
939 return -ENODEV;
940
941 ag->phy_priv = as;
942 ar7240sw_reset(as);
943
944 INIT_DELAYED_WORK(&ag->link_work, link_function);
945
946 return 0;
947 }
948
949 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
950 {
951 struct ar7240sw *as = ag->phy_priv;
952
953 if (!as)
954 return;
955
956 unregister_switch(&as->swdev);
957 kfree(as);
958 ag->phy_priv = NULL;
959 }
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