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ar71xx: ag71xx: fix switch port setup for AR934X
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
31
32 #define AR7240_REG_MAC_ADDR0 0x20
33 #define AR7240_REG_MAC_ADDR1 0x24
34
35 #define AR7240_REG_FLOOD_MASK 0x2c
36 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
37
38 #define AR7240_REG_GLOBAL_CTRL 0x30
39 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
40
41 #define AR7240_REG_VTU 0x0040
42 #define AR7240_VTU_OP BITM(3)
43 #define AR7240_VTU_OP_NOOP 0x0
44 #define AR7240_VTU_OP_FLUSH 0x1
45 #define AR7240_VTU_OP_LOAD 0x2
46 #define AR7240_VTU_OP_PURGE 0x3
47 #define AR7240_VTU_OP_REMOVE_PORT 0x4
48 #define AR7240_VTU_ACTIVE BIT(3)
49 #define AR7240_VTU_FULL BIT(4)
50 #define AR7240_VTU_PORT BITS(8, 4)
51 #define AR7240_VTU_PORT_S 8
52 #define AR7240_VTU_VID BITS(16, 12)
53 #define AR7240_VTU_VID_S 16
54 #define AR7240_VTU_PRIO BITS(28, 3)
55 #define AR7240_VTU_PRIO_S 28
56 #define AR7240_VTU_PRIO_EN BIT(31)
57
58 #define AR7240_REG_VTU_DATA 0x0044
59 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
60 #define AR7240_VTUDATA_VALID BIT(11)
61
62 #define AR7240_REG_ATU 0x50
63 #define AR7240_ATU_FLUSH_ALL 0x1
64
65 #define AR7240_REG_AT_CTRL 0x5c
66 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
67 #define AR7240_AT_CTRL_AGE_EN BIT(17)
68 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
69 #define AR7240_AT_CTRL_ARP_EN BIT(20)
70
71 #define AR7240_REG_TAG_PRIORITY 0x70
72
73 #define AR7240_REG_SERVICE_TAG 0x74
74 #define AR7240_SERVICE_TAG_M BITM(16)
75
76 #define AR7240_REG_CPU_PORT 0x78
77 #define AR7240_MIRROR_PORT_S 4
78 #define AR7240_CPU_PORT_EN BIT(8)
79
80 #define AR7240_REG_MIB_FUNCTION0 0x80
81 #define AR7240_MIB_TIMER_M BITM(16)
82 #define AR7240_MIB_AT_HALF_EN BIT(16)
83 #define AR7240_MIB_BUSY BIT(17)
84 #define AR7240_MIB_FUNC_S 24
85 #define AR7240_MIB_FUNC_NO_OP 0x0
86 #define AR7240_MIB_FUNC_FLUSH 0x1
87 #define AR7240_MIB_FUNC_CAPTURE 0x3
88
89 #define AR7240_REG_MDIO_CTRL 0x98
90 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
91 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
92 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
93 #define AR7240_MDIO_CTRL_CMD_WRITE 0
94 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
95 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
96 #define AR7240_MDIO_CTRL_BUSY BIT(31)
97
98 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
99
100 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
101 #define AR7240_PORT_STATUS_SPEED_S 0
102 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
103 #define AR7240_PORT_STATUS_SPEED_10 0
104 #define AR7240_PORT_STATUS_SPEED_100 1
105 #define AR7240_PORT_STATUS_SPEED_1000 2
106 #define AR7240_PORT_STATUS_TXMAC BIT(2)
107 #define AR7240_PORT_STATUS_RXMAC BIT(3)
108 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
109 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
110 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
111 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
112 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
113 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
114
115 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
116 #define AR7240_PORT_CTRL_STATE_M BITM(3)
117 #define AR7240_PORT_CTRL_STATE_DISABLED 0
118 #define AR7240_PORT_CTRL_STATE_BLOCK 1
119 #define AR7240_PORT_CTRL_STATE_LISTEN 2
120 #define AR7240_PORT_CTRL_STATE_LEARN 3
121 #define AR7240_PORT_CTRL_STATE_FORWARD 4
122 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
123 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
124 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
125 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
126 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
127 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
128 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
129 #define AR7240_PORT_CTRL_HEADER BIT(11)
130 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
131 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
132 #define AR7240_PORT_CTRL_LEARN BIT(14)
133 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
134 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
135 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
136
137 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
138
139 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
140 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
141 #define AR7240_PORT_VLAN_MODE_S 30
142 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
143 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
144 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
145 #define AR7240_PORT_VLAN_MODE_SECURE 3
146
147
148 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
149
150 #define AR7240_STATS_RXBROAD 0x00
151 #define AR7240_STATS_RXPAUSE 0x04
152 #define AR7240_STATS_RXMULTI 0x08
153 #define AR7240_STATS_RXFCSERR 0x0c
154 #define AR7240_STATS_RXALIGNERR 0x10
155 #define AR7240_STATS_RXRUNT 0x14
156 #define AR7240_STATS_RXFRAGMENT 0x18
157 #define AR7240_STATS_RX64BYTE 0x1c
158 #define AR7240_STATS_RX128BYTE 0x20
159 #define AR7240_STATS_RX256BYTE 0x24
160 #define AR7240_STATS_RX512BYTE 0x28
161 #define AR7240_STATS_RX1024BYTE 0x2c
162 #define AR7240_STATS_RX1518BYTE 0x30
163 #define AR7240_STATS_RXMAXBYTE 0x34
164 #define AR7240_STATS_RXTOOLONG 0x38
165 #define AR7240_STATS_RXGOODBYTE 0x3c
166 #define AR7240_STATS_RXBADBYTE 0x44
167 #define AR7240_STATS_RXOVERFLOW 0x4c
168 #define AR7240_STATS_FILTERED 0x50
169 #define AR7240_STATS_TXBROAD 0x54
170 #define AR7240_STATS_TXPAUSE 0x58
171 #define AR7240_STATS_TXMULTI 0x5c
172 #define AR7240_STATS_TXUNDERRUN 0x60
173 #define AR7240_STATS_TX64BYTE 0x64
174 #define AR7240_STATS_TX128BYTE 0x68
175 #define AR7240_STATS_TX256BYTE 0x6c
176 #define AR7240_STATS_TX512BYTE 0x70
177 #define AR7240_STATS_TX1024BYTE 0x74
178 #define AR7240_STATS_TX1518BYTE 0x78
179 #define AR7240_STATS_TXMAXBYTE 0x7c
180 #define AR7240_STATS_TXOVERSIZE 0x80
181 #define AR7240_STATS_TXBYTE 0x84
182 #define AR7240_STATS_TXCOLLISION 0x8c
183 #define AR7240_STATS_TXABORTCOL 0x90
184 #define AR7240_STATS_TXMULTICOL 0x94
185 #define AR7240_STATS_TXSINGLECOL 0x98
186 #define AR7240_STATS_TXEXCDEFER 0x9c
187 #define AR7240_STATS_TXDEFER 0xa0
188 #define AR7240_STATS_TXLATECOL 0xa4
189
190 #define AR7240_PORT_CPU 0
191 #define AR7240_NUM_PORTS 6
192 #define AR7240_NUM_PHYS 5
193
194 #define AR7240_PHY_ID1 0x004d
195 #define AR7240_PHY_ID2 0xd041
196
197 #define AR934X_PHY_ID1 0x004d
198 #define AR934X_PHY_ID2 0xd042
199
200 #define AR7240_MAX_VLANS 16
201
202 #define AR934X_REG_OPER_MODE0 0x04
203 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
204 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
205
206 #define AR934X_REG_OPER_MODE1 0x08
207 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
208
209 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
210
211 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
212 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
213 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
214 #define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
215 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
216 #define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
217 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
218 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
219 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
220
221 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
222 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
223 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30
224 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
225 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
226 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
227 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
228
229 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
230
231 struct ar7240sw {
232 struct mii_bus *mii_bus;
233 struct ag71xx_switch_platform_data *swdata;
234 struct switch_dev swdev;
235 int num_ports;
236 u8 ver;
237 bool vlan;
238 u16 vlan_id[AR7240_MAX_VLANS];
239 u8 vlan_table[AR7240_MAX_VLANS];
240 u8 vlan_tagged;
241 u16 pvid[AR7240_NUM_PORTS];
242 char buf[80];
243 };
244
245 struct ar7240sw_hw_stat {
246 char string[ETH_GSTRING_LEN];
247 int sizeof_stat;
248 int reg;
249 };
250
251 static DEFINE_MUTEX(reg_mutex);
252
253 static inline int sw_is_ar7240(struct ar7240sw *as)
254 {
255 return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
256 }
257
258 static inline int sw_is_ar934x(struct ar7240sw *as)
259 {
260 return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
261 }
262
263 static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
264 {
265 return BIT(port);
266 }
267
268 static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
269 {
270 return BIT(as->swdev.ports) - 1;
271 }
272
273 static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
274 {
275 return ar7240sw_port_mask_all(as) & ~BIT(port);
276 }
277
278 static inline u16 mk_phy_addr(u32 reg)
279 {
280 return 0x17 & ((reg >> 4) | 0x10);
281 }
282
283 static inline u16 mk_phy_reg(u32 reg)
284 {
285 return (reg << 1) & 0x1e;
286 }
287
288 static inline u16 mk_high_addr(u32 reg)
289 {
290 return (reg >> 7) & 0x1ff;
291 }
292
293 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
294 {
295 unsigned long flags;
296 u16 phy_addr;
297 u16 phy_reg;
298 u32 hi, lo;
299
300 reg = (reg & 0xfffffffc) >> 2;
301 phy_addr = mk_phy_addr(reg);
302 phy_reg = mk_phy_reg(reg);
303
304 local_irq_save(flags);
305 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
306 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
307 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
308 local_irq_restore(flags);
309
310 return (hi << 16) | lo;
311 }
312
313 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
314 {
315 unsigned long flags;
316 u16 phy_addr;
317 u16 phy_reg;
318
319 reg = (reg & 0xfffffffc) >> 2;
320 phy_addr = mk_phy_addr(reg);
321 phy_reg = mk_phy_reg(reg);
322
323 local_irq_save(flags);
324 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
325 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
326 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
327 local_irq_restore(flags);
328 }
329
330 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
331 {
332 u32 ret;
333
334 mutex_lock(&reg_mutex);
335 ret = __ar7240sw_reg_read(mii, reg_addr);
336 mutex_unlock(&reg_mutex);
337
338 return ret;
339 }
340
341 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
342 {
343 mutex_lock(&reg_mutex);
344 __ar7240sw_reg_write(mii, reg_addr, reg_val);
345 mutex_unlock(&reg_mutex);
346 }
347
348 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
349 {
350 u32 t;
351
352 mutex_lock(&reg_mutex);
353 t = __ar7240sw_reg_read(mii, reg);
354 t &= ~mask;
355 t |= val;
356 __ar7240sw_reg_write(mii, reg, t);
357 mutex_unlock(&reg_mutex);
358
359 return t;
360 }
361
362 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
363 {
364 u32 t;
365
366 mutex_lock(&reg_mutex);
367 t = __ar7240sw_reg_read(mii, reg);
368 t |= val;
369 __ar7240sw_reg_write(mii, reg, t);
370 mutex_unlock(&reg_mutex);
371 }
372
373 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
374 unsigned timeout)
375 {
376 int i;
377
378 for (i = 0; i < timeout; i++) {
379 u32 t;
380
381 t = __ar7240sw_reg_read(mii, reg);
382 if ((t & mask) == val)
383 return 0;
384
385 msleep(1);
386 }
387
388 return -ETIMEDOUT;
389 }
390
391 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
392 unsigned timeout)
393 {
394 int ret;
395
396 mutex_lock(&reg_mutex);
397 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
398 mutex_unlock(&reg_mutex);
399 return ret;
400 }
401
402 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
403 unsigned reg_addr)
404 {
405 u32 t, val = 0xffff;
406 int err;
407
408 if (phy_addr >= AR7240_NUM_PHYS)
409 return 0xffff;
410
411 mutex_lock(&reg_mutex);
412 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
413 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
414 AR7240_MDIO_CTRL_MASTER_EN |
415 AR7240_MDIO_CTRL_BUSY |
416 AR7240_MDIO_CTRL_CMD_READ;
417
418 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
419 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
420 AR7240_MDIO_CTRL_BUSY, 0, 5);
421 if (!err)
422 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
423 mutex_unlock(&reg_mutex);
424
425 return val & AR7240_MDIO_CTRL_DATA_M;
426 }
427
428 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
429 unsigned reg_addr, u16 reg_val)
430 {
431 u32 t;
432 int ret;
433
434 if (phy_addr >= AR7240_NUM_PHYS)
435 return -EINVAL;
436
437 mutex_lock(&reg_mutex);
438 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
439 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
440 AR7240_MDIO_CTRL_MASTER_EN |
441 AR7240_MDIO_CTRL_BUSY |
442 AR7240_MDIO_CTRL_CMD_WRITE |
443 reg_val;
444
445 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
446 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
447 AR7240_MDIO_CTRL_BUSY, 0, 5);
448 mutex_unlock(&reg_mutex);
449
450 return ret;
451 }
452
453 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
454 {
455 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
456 AR7240_PORT_CTRL_STATE_DISABLED);
457 }
458
459 static void ar7240sw_setup(struct ar7240sw *as)
460 {
461 struct mii_bus *mii = as->mii_bus;
462
463 /* Enable CPU port, and disable mirror port */
464 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
465 AR7240_CPU_PORT_EN |
466 (15 << AR7240_MIRROR_PORT_S));
467
468 /* Setup TAG priority mapping */
469 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
470
471 /* Enable ARP frame acknowledge, aging, MAC replacing */
472 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
473 0x2b /* 5 min age time */ |
474 AR7240_AT_CTRL_AGE_EN |
475 AR7240_AT_CTRL_ARP_EN |
476 AR7240_AT_CTRL_LEARN_CHANGE);
477
478 /* Enable Broadcast frames transmitted to the CPU */
479 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
480 AR7240_FLOOD_MASK_BROAD_TO_CPU);
481
482 /* setup MTU */
483 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
484 1536);
485
486 /* setup Service TAG */
487 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
488 }
489
490 static int ar7240sw_reset(struct ar7240sw *as)
491 {
492 struct mii_bus *mii = as->mii_bus;
493 int ret;
494 int i;
495
496 /* Set all ports to disabled state. */
497 for (i = 0; i < AR7240_NUM_PORTS; i++)
498 ar7240sw_disable_port(as, i);
499
500 /* Wait for transmit queues to drain. */
501 msleep(2);
502
503 /* Reset the switch. */
504 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
505 AR7240_MASK_CTRL_SOFT_RESET);
506
507 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
508 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
509
510 ar7240sw_setup(as);
511 return ret;
512 }
513
514 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
515 {
516 struct mii_bus *mii = as->mii_bus;
517 u32 ctrl;
518 u32 vid, mode;
519
520 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
521 AR7240_PORT_CTRL_SINGLE_VLAN;
522
523 if (port == AR7240_PORT_CPU) {
524 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
525 AR7240_PORT_STATUS_SPEED_1000 |
526 AR7240_PORT_STATUS_TXFLOW |
527 AR7240_PORT_STATUS_RXFLOW |
528 AR7240_PORT_STATUS_TXMAC |
529 AR7240_PORT_STATUS_RXMAC |
530 AR7240_PORT_STATUS_DUPLEX);
531 } else {
532 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
533 AR7240_PORT_STATUS_LINK_AUTO);
534 }
535
536 /* Set the default VID for this port */
537 if (as->vlan) {
538 vid = as->vlan_id[as->pvid[port]];
539 mode = AR7240_PORT_VLAN_MODE_SECURE;
540 } else {
541 vid = port;
542 mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
543 }
544
545 if (as->vlan && (as->vlan_tagged & BIT(port))) {
546 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
547 AR7240_PORT_CTRL_VLAN_MODE_S;
548 } else {
549 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
550 AR7240_PORT_CTRL_VLAN_MODE_S;
551 }
552
553 if (!portmask) {
554 if (port == AR7240_PORT_CPU)
555 portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
556 else
557 portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
558 }
559
560 /* allow the port to talk to all other ports, but exclude its
561 * own ID to prevent frames from being reflected back to the
562 * port that they came from */
563 portmask &= ar7240sw_port_mask_but(as, port);
564
565 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
566 if (sw_is_ar934x(as)) {
567 u32 vlan1, vlan2;
568
569 vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
570 vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
571 (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
572 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
573 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
574 } else {
575 u32 vlan;
576
577 vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
578 (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
579
580 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
581 }
582 }
583
584 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
585 {
586 struct mii_bus *mii = as->mii_bus;
587 u32 t;
588
589 t = (addr[4] << 8) | addr[5];
590 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
591
592 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
593 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
594
595 return 0;
596 }
597
598 static int
599 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
600 struct switch_val *val)
601 {
602 struct ar7240sw *as = sw_to_ar7240(dev);
603 as->vlan_id[val->port_vlan] = val->value.i;
604 return 0;
605 }
606
607 static int
608 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
609 struct switch_val *val)
610 {
611 struct ar7240sw *as = sw_to_ar7240(dev);
612 val->value.i = as->vlan_id[val->port_vlan];
613 return 0;
614 }
615
616 static int
617 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
618 {
619 struct ar7240sw *as = sw_to_ar7240(dev);
620
621 /* make sure no invalid PVIDs get set */
622
623 if (vlan >= dev->vlans)
624 return -EINVAL;
625
626 as->pvid[port] = vlan;
627 return 0;
628 }
629
630 static int
631 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
632 {
633 struct ar7240sw *as = sw_to_ar7240(dev);
634 *vlan = as->pvid[port];
635 return 0;
636 }
637
638 static int
639 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
640 {
641 struct ar7240sw *as = sw_to_ar7240(dev);
642 u8 ports = as->vlan_table[val->port_vlan];
643 int i;
644
645 val->len = 0;
646 for (i = 0; i < as->swdev.ports; i++) {
647 struct switch_port *p;
648
649 if (!(ports & (1 << i)))
650 continue;
651
652 p = &val->value.ports[val->len++];
653 p->id = i;
654 if (as->vlan_tagged & (1 << i))
655 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
656 else
657 p->flags = 0;
658 }
659 return 0;
660 }
661
662 static int
663 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
664 {
665 struct ar7240sw *as = sw_to_ar7240(dev);
666 u8 *vt = &as->vlan_table[val->port_vlan];
667 int i, j;
668
669 *vt = 0;
670 for (i = 0; i < val->len; i++) {
671 struct switch_port *p = &val->value.ports[i];
672
673 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
674 as->vlan_tagged |= (1 << p->id);
675 else {
676 as->vlan_tagged &= ~(1 << p->id);
677 as->pvid[p->id] = val->port_vlan;
678
679 /* make sure that an untagged port does not
680 * appear in other vlans */
681 for (j = 0; j < AR7240_MAX_VLANS; j++) {
682 if (j == val->port_vlan)
683 continue;
684 as->vlan_table[j] &= ~(1 << p->id);
685 }
686 }
687
688 *vt |= 1 << p->id;
689 }
690 return 0;
691 }
692
693 static int
694 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
695 struct switch_val *val)
696 {
697 struct ar7240sw *as = sw_to_ar7240(dev);
698 as->vlan = !!val->value.i;
699 return 0;
700 }
701
702 static int
703 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
704 struct switch_val *val)
705 {
706 struct ar7240sw *as = sw_to_ar7240(dev);
707 val->value.i = as->vlan;
708 return 0;
709 }
710
711 static const char *
712 ar7240_speed_str(u32 status)
713 {
714 u32 speed;
715
716 speed = (status >> AR7240_PORT_STATUS_SPEED_S) &
717 AR7240_PORT_STATUS_SPEED_M;
718 switch (speed) {
719 case AR7240_PORT_STATUS_SPEED_10:
720 return "10baseT";
721 case AR7240_PORT_STATUS_SPEED_100:
722 return "100baseT";
723 case AR7240_PORT_STATUS_SPEED_1000:
724 return "1000baseT";
725 }
726
727 return "unknown";
728 }
729
730 static int
731 ar7240_port_get_link(struct switch_dev *dev, const struct switch_attr *attr,
732 struct switch_val *val)
733 {
734 struct ar7240sw *as = sw_to_ar7240(dev);
735 struct mii_bus *mii = as->mii_bus;
736 u32 len;
737 u32 status;
738 int port;
739
740 port = val->port_vlan;
741
742 memset(as->buf, '\0', sizeof(as->buf));
743 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
744
745 if (status & AR7240_PORT_STATUS_LINK_UP) {
746 len = snprintf(as->buf, sizeof(as->buf),
747 "port:%d link:up speed:%s %s-duplex %s%s%s",
748 port,
749 ar7240_speed_str(status),
750 (status & AR7240_PORT_STATUS_DUPLEX) ?
751 "full" : "half",
752 (status & AR7240_PORT_STATUS_TXFLOW) ?
753 "txflow ": "",
754 (status & AR7240_PORT_STATUS_RXFLOW) ?
755 "rxflow " : "",
756 (status & AR7240_PORT_STATUS_LINK_AUTO) ?
757 "auto ": "");
758 } else {
759 len = snprintf(as->buf, sizeof(as->buf),
760 "port:%d link:down", port);
761 }
762
763 val->value.s = as->buf;
764 val->len = len;
765
766 return 0;
767 }
768
769 static void
770 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
771 {
772 struct mii_bus *mii = as->mii_bus;
773
774 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
775 return;
776
777 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
778 val &= AR7240_VTUDATA_MEMBER;
779 val |= AR7240_VTUDATA_VALID;
780 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
781 }
782 op |= AR7240_VTU_ACTIVE;
783 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
784 }
785
786 static int
787 ar7240_hw_apply(struct switch_dev *dev)
788 {
789 struct ar7240sw *as = sw_to_ar7240(dev);
790 u8 portmask[AR7240_NUM_PORTS];
791 int i, j;
792
793 /* flush all vlan translation unit entries */
794 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
795
796 memset(portmask, 0, sizeof(portmask));
797 if (as->vlan) {
798 /* calculate the port destination masks and load vlans
799 * into the vlan translation unit */
800 for (j = 0; j < AR7240_MAX_VLANS; j++) {
801 u8 vp = as->vlan_table[j];
802
803 if (!vp)
804 continue;
805
806 for (i = 0; i < as->swdev.ports; i++) {
807 u8 mask = (1 << i);
808 if (vp & mask)
809 portmask[i] |= vp & ~mask;
810 }
811
812 ar7240_vtu_op(as,
813 AR7240_VTU_OP_LOAD |
814 (as->vlan_id[j] << AR7240_VTU_VID_S),
815 as->vlan_table[j]);
816 }
817 } else {
818 /* vlan disabled:
819 * isolate all ports, but connect them to the cpu port */
820 for (i = 0; i < as->swdev.ports; i++) {
821 if (i == AR7240_PORT_CPU)
822 continue;
823
824 portmask[i] = 1 << AR7240_PORT_CPU;
825 portmask[AR7240_PORT_CPU] |= (1 << i);
826 }
827 }
828
829 /* update the port destination mask registers and tag settings */
830 for (i = 0; i < as->swdev.ports; i++)
831 ar7240sw_setup_port(as, i, portmask[i]);
832
833 return 0;
834 }
835
836 static int
837 ar7240_reset_switch(struct switch_dev *dev)
838 {
839 struct ar7240sw *as = sw_to_ar7240(dev);
840 ar7240sw_reset(as);
841 return 0;
842 }
843
844 static struct switch_attr ar7240_globals[] = {
845 {
846 .type = SWITCH_TYPE_INT,
847 .name = "enable_vlan",
848 .description = "Enable VLAN mode",
849 .set = ar7240_set_vlan,
850 .get = ar7240_get_vlan,
851 .max = 1
852 },
853 };
854
855 static struct switch_attr ar7240_port[] = {
856 {
857 .type = SWITCH_TYPE_STRING,
858 .name = "link",
859 .description = "Get port link information",
860 .max = 1,
861 .set = NULL,
862 .get = ar7240_port_get_link,
863 },
864 };
865
866 static struct switch_attr ar7240_vlan[] = {
867 {
868 .type = SWITCH_TYPE_INT,
869 .name = "vid",
870 .description = "VLAN ID",
871 .set = ar7240_set_vid,
872 .get = ar7240_get_vid,
873 .max = 4094,
874 },
875 };
876
877 static const struct switch_dev_ops ar7240_ops = {
878 .attr_global = {
879 .attr = ar7240_globals,
880 .n_attr = ARRAY_SIZE(ar7240_globals),
881 },
882 .attr_port = {
883 .attr = ar7240_port,
884 .n_attr = ARRAY_SIZE(ar7240_port),
885 },
886 .attr_vlan = {
887 .attr = ar7240_vlan,
888 .n_attr = ARRAY_SIZE(ar7240_vlan),
889 },
890 .get_port_pvid = ar7240_get_pvid,
891 .set_port_pvid = ar7240_set_pvid,
892 .get_vlan_ports = ar7240_get_ports,
893 .set_vlan_ports = ar7240_set_ports,
894 .apply_config = ar7240_hw_apply,
895 .reset_switch = ar7240_reset_switch,
896 };
897
898 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
899 {
900 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
901 struct mii_bus *mii = ag->mii_bus;
902 struct ar7240sw *as;
903 struct switch_dev *swdev;
904 u32 ctrl;
905 u16 phy_id1;
906 u16 phy_id2;
907 int i;
908
909 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
910 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
911 if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
912 (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
913 pr_err("%s: unknown phy id '%04x:%04x'\n",
914 ag->dev->name, phy_id1, phy_id2);
915 return NULL;
916 }
917
918 as = kzalloc(sizeof(*as), GFP_KERNEL);
919 if (!as)
920 return NULL;
921
922 as->mii_bus = mii;
923 as->swdata = pdata->switch_data;
924
925 swdev = &as->swdev;
926
927 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
928 as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
929 AR7240_MASK_CTRL_VERSION_M;
930
931 if (sw_is_ar7240(as)) {
932 swdev->name = "AR7240/AR9330 built-in switch";
933 } else if (sw_is_ar934x(as)) {
934 swdev->name = "AR934X built-in switch";
935
936 if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
937 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
938 AR934X_OPER_MODE0_MAC_GMII_EN);
939 } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
940 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
941 AR934X_OPER_MODE0_PHY_MII_EN);
942 } else {
943 pr_err("%s: invalid PHY interface mode\n",
944 ag->dev->name);
945 goto err_free;
946 }
947
948 if (as->swdata->phy4_mii_en)
949 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
950 AR934X_REG_OPER_MODE1_PHY4_MII_EN);
951 } else {
952 pr_err("%s: unsupported chip, ctrl=%08x\n",
953 ag->dev->name, ctrl);
954 goto err_free;
955 }
956
957 swdev->ports = AR7240_NUM_PORTS - 1;
958 swdev->cpu_port = AR7240_PORT_CPU;
959 swdev->vlans = AR7240_MAX_VLANS;
960 swdev->ops = &ar7240_ops;
961
962 if (register_switch(&as->swdev, ag->dev) < 0)
963 goto err_free;
964
965 pr_info("%s: Found an %s\n", ag->dev->name, swdev->name);
966
967 /* initialize defaults */
968 for (i = 0; i < AR7240_MAX_VLANS; i++)
969 as->vlan_id[i] = i;
970
971 as->vlan_table[0] = ar7240sw_port_mask_all(as);
972
973 return as;
974
975 err_free:
976 kfree(as);
977 return NULL;
978 }
979
980 static void link_function(struct work_struct *work) {
981 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
982 unsigned long flags;
983 int i;
984 int status = 0;
985
986 for (i = 0; i < 4; i++) {
987 int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
988 if(link & BMSR_LSTATUS) {
989 status = 1;
990 break;
991 }
992 }
993
994 spin_lock_irqsave(&ag->lock, flags);
995 if(status != ag->link) {
996 ag->link = status;
997 ag71xx_link_adjust(ag);
998 }
999 spin_unlock_irqrestore(&ag->lock, flags);
1000
1001 schedule_delayed_work(&ag->link_work, HZ / 2);
1002 }
1003
1004 void ag71xx_ar7240_start(struct ag71xx *ag)
1005 {
1006 struct ar7240sw *as = ag->phy_priv;
1007
1008 ar7240sw_reset(as);
1009
1010 ag->speed = SPEED_1000;
1011 ag->duplex = 1;
1012
1013 ar7240_set_addr(as, ag->dev->dev_addr);
1014 ar7240_hw_apply(&as->swdev);
1015
1016 schedule_delayed_work(&ag->link_work, HZ / 10);
1017 }
1018
1019 void ag71xx_ar7240_stop(struct ag71xx *ag)
1020 {
1021 cancel_delayed_work_sync(&ag->link_work);
1022 }
1023
1024 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
1025 {
1026 struct ar7240sw *as;
1027
1028 as = ar7240_probe(ag);
1029 if (!as)
1030 return -ENODEV;
1031
1032 ag->phy_priv = as;
1033 ar7240sw_reset(as);
1034
1035 INIT_DELAYED_WORK(&ag->link_work, link_function);
1036
1037 return 0;
1038 }
1039
1040 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
1041 {
1042 struct ar7240sw *as = ag->phy_priv;
1043
1044 if (!as)
1045 return;
1046
1047 unregister_switch(&as->swdev);
1048 kfree(as);
1049 ag->phy_priv = NULL;
1050 }
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