ar71xx: ag71xx: add support for getting switch port link status
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
29
30 #define AR7240_REG_MAC_ADDR0 0x20
31 #define AR7240_REG_MAC_ADDR1 0x24
32
33 #define AR7240_REG_FLOOD_MASK 0x2c
34 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
35
36 #define AR7240_REG_GLOBAL_CTRL 0x30
37 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
38
39 #define AR7240_REG_VTU 0x0040
40 #define AR7240_VTU_OP BITM(3)
41 #define AR7240_VTU_OP_NOOP 0x0
42 #define AR7240_VTU_OP_FLUSH 0x1
43 #define AR7240_VTU_OP_LOAD 0x2
44 #define AR7240_VTU_OP_PURGE 0x3
45 #define AR7240_VTU_OP_REMOVE_PORT 0x4
46 #define AR7240_VTU_ACTIVE BIT(3)
47 #define AR7240_VTU_FULL BIT(4)
48 #define AR7240_VTU_PORT BITS(8, 4)
49 #define AR7240_VTU_PORT_S 8
50 #define AR7240_VTU_VID BITS(16, 12)
51 #define AR7240_VTU_VID_S 16
52 #define AR7240_VTU_PRIO BITS(28, 3)
53 #define AR7240_VTU_PRIO_S 28
54 #define AR7240_VTU_PRIO_EN BIT(31)
55
56 #define AR7240_REG_VTU_DATA 0x0044
57 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
58 #define AR7240_VTUDATA_VALID BIT(11)
59
60 #define AR7240_REG_ATU 0x50
61 #define AR7240_ATU_FLUSH_ALL 0x1
62
63 #define AR7240_REG_AT_CTRL 0x5c
64 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
65 #define AR7240_AT_CTRL_AGE_EN BIT(17)
66 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
67 #define AR7240_AT_CTRL_ARP_EN BIT(20)
68
69 #define AR7240_REG_TAG_PRIORITY 0x70
70
71 #define AR7240_REG_SERVICE_TAG 0x74
72 #define AR7240_SERVICE_TAG_M BITM(16)
73
74 #define AR7240_REG_CPU_PORT 0x78
75 #define AR7240_MIRROR_PORT_S 4
76 #define AR7240_CPU_PORT_EN BIT(8)
77
78 #define AR7240_REG_MIB_FUNCTION0 0x80
79 #define AR7240_MIB_TIMER_M BITM(16)
80 #define AR7240_MIB_AT_HALF_EN BIT(16)
81 #define AR7240_MIB_BUSY BIT(17)
82 #define AR7240_MIB_FUNC_S 24
83 #define AR7240_MIB_FUNC_NO_OP 0x0
84 #define AR7240_MIB_FUNC_FLUSH 0x1
85 #define AR7240_MIB_FUNC_CAPTURE 0x3
86
87 #define AR7240_REG_MDIO_CTRL 0x98
88 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
89 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
90 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
91 #define AR7240_MDIO_CTRL_CMD_WRITE 0
92 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
93 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
94 #define AR7240_MDIO_CTRL_BUSY BIT(31)
95
96 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
97
98 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
99 #define AR7240_PORT_STATUS_SPEED_S 0
100 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
101 #define AR7240_PORT_STATUS_SPEED_10 0
102 #define AR7240_PORT_STATUS_SPEED_100 1
103 #define AR7240_PORT_STATUS_SPEED_1000 2
104 #define AR7240_PORT_STATUS_TXMAC BIT(2)
105 #define AR7240_PORT_STATUS_RXMAC BIT(3)
106 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
107 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
108 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
109 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
110 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
111 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
112
113 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
114 #define AR7240_PORT_CTRL_STATE_M BITM(3)
115 #define AR7240_PORT_CTRL_STATE_DISABLED 0
116 #define AR7240_PORT_CTRL_STATE_BLOCK 1
117 #define AR7240_PORT_CTRL_STATE_LISTEN 2
118 #define AR7240_PORT_CTRL_STATE_LEARN 3
119 #define AR7240_PORT_CTRL_STATE_FORWARD 4
120 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
121 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
122 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
123 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
124 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
125 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
126 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
127 #define AR7240_PORT_CTRL_HEADER BIT(11)
128 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
129 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
130 #define AR7240_PORT_CTRL_LEARN BIT(14)
131 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
132 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
133 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
134
135 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
136
137 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
138 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
139 #define AR7240_PORT_VLAN_MODE_S 30
140 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
141 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
142 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
143 #define AR7240_PORT_VLAN_MODE_SECURE 3
144
145
146 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
147
148 #define AR7240_STATS_RXBROAD 0x00
149 #define AR7240_STATS_RXPAUSE 0x04
150 #define AR7240_STATS_RXMULTI 0x08
151 #define AR7240_STATS_RXFCSERR 0x0c
152 #define AR7240_STATS_RXALIGNERR 0x10
153 #define AR7240_STATS_RXRUNT 0x14
154 #define AR7240_STATS_RXFRAGMENT 0x18
155 #define AR7240_STATS_RX64BYTE 0x1c
156 #define AR7240_STATS_RX128BYTE 0x20
157 #define AR7240_STATS_RX256BYTE 0x24
158 #define AR7240_STATS_RX512BYTE 0x28
159 #define AR7240_STATS_RX1024BYTE 0x2c
160 #define AR7240_STATS_RX1518BYTE 0x30
161 #define AR7240_STATS_RXMAXBYTE 0x34
162 #define AR7240_STATS_RXTOOLONG 0x38
163 #define AR7240_STATS_RXGOODBYTE 0x3c
164 #define AR7240_STATS_RXBADBYTE 0x44
165 #define AR7240_STATS_RXOVERFLOW 0x4c
166 #define AR7240_STATS_FILTERED 0x50
167 #define AR7240_STATS_TXBROAD 0x54
168 #define AR7240_STATS_TXPAUSE 0x58
169 #define AR7240_STATS_TXMULTI 0x5c
170 #define AR7240_STATS_TXUNDERRUN 0x60
171 #define AR7240_STATS_TX64BYTE 0x64
172 #define AR7240_STATS_TX128BYTE 0x68
173 #define AR7240_STATS_TX256BYTE 0x6c
174 #define AR7240_STATS_TX512BYTE 0x70
175 #define AR7240_STATS_TX1024BYTE 0x74
176 #define AR7240_STATS_TX1518BYTE 0x78
177 #define AR7240_STATS_TXMAXBYTE 0x7c
178 #define AR7240_STATS_TXOVERSIZE 0x80
179 #define AR7240_STATS_TXBYTE 0x84
180 #define AR7240_STATS_TXCOLLISION 0x8c
181 #define AR7240_STATS_TXABORTCOL 0x90
182 #define AR7240_STATS_TXMULTICOL 0x94
183 #define AR7240_STATS_TXSINGLECOL 0x98
184 #define AR7240_STATS_TXEXCDEFER 0x9c
185 #define AR7240_STATS_TXDEFER 0xa0
186 #define AR7240_STATS_TXLATECOL 0xa4
187
188 #define AR7240_PORT_CPU 0
189 #define AR7240_NUM_PORTS 6
190 #define AR7240_NUM_PHYS 5
191
192 #define AR7240_PHY_ID1 0x004d
193 #define AR7240_PHY_ID2 0xd041
194
195 #define AR7240_PORT_MASK(_port) BIT((_port))
196 #define AR7240_PORT_MASK_ALL BITM(AR7240_NUM_PORTS)
197 #define AR7240_PORT_MASK_BUT(_port) (AR7240_PORT_MASK_ALL & ~BIT((_port)))
198
199 #define AR7240_MAX_VLANS 16
200
201 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
202
203 struct ar7240sw {
204 struct mii_bus *mii_bus;
205 struct switch_dev swdev;
206 bool vlan;
207 u16 vlan_id[AR7240_MAX_VLANS];
208 u8 vlan_table[AR7240_MAX_VLANS];
209 u8 vlan_tagged;
210 u16 pvid[AR7240_NUM_PORTS];
211 char buf[80];
212 };
213
214 struct ar7240sw_hw_stat {
215 char string[ETH_GSTRING_LEN];
216 int sizeof_stat;
217 int reg;
218 };
219
220 static DEFINE_MUTEX(reg_mutex);
221
222 static inline void ar7240sw_init(struct ar7240sw *as, struct mii_bus *mii)
223 {
224 as->mii_bus = mii;
225 }
226
227 static inline u16 mk_phy_addr(u32 reg)
228 {
229 return 0x17 & ((reg >> 4) | 0x10);
230 }
231
232 static inline u16 mk_phy_reg(u32 reg)
233 {
234 return (reg << 1) & 0x1e;
235 }
236
237 static inline u16 mk_high_addr(u32 reg)
238 {
239 return (reg >> 7) & 0x1ff;
240 }
241
242 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
243 {
244 unsigned long flags;
245 u16 phy_addr;
246 u16 phy_reg;
247 u32 hi, lo;
248
249 reg = (reg & 0xfffffffc) >> 2;
250 phy_addr = mk_phy_addr(reg);
251 phy_reg = mk_phy_reg(reg);
252
253 local_irq_save(flags);
254 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
255 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
256 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
257 local_irq_restore(flags);
258
259 return (hi << 16) | lo;
260 }
261
262 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
263 {
264 unsigned long flags;
265 u16 phy_addr;
266 u16 phy_reg;
267
268 reg = (reg & 0xfffffffc) >> 2;
269 phy_addr = mk_phy_addr(reg);
270 phy_reg = mk_phy_reg(reg);
271
272 local_irq_save(flags);
273 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
274 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
275 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
276 local_irq_restore(flags);
277 }
278
279 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
280 {
281 u32 ret;
282
283 mutex_lock(&reg_mutex);
284 ret = __ar7240sw_reg_read(mii, reg_addr);
285 mutex_unlock(&reg_mutex);
286
287 return ret;
288 }
289
290 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
291 {
292 mutex_lock(&reg_mutex);
293 __ar7240sw_reg_write(mii, reg_addr, reg_val);
294 mutex_unlock(&reg_mutex);
295 }
296
297 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
298 {
299 u32 t;
300
301 mutex_lock(&reg_mutex);
302 t = __ar7240sw_reg_read(mii, reg);
303 t &= ~mask;
304 t |= val;
305 __ar7240sw_reg_write(mii, reg, t);
306 mutex_unlock(&reg_mutex);
307
308 return t;
309 }
310
311 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
312 {
313 u32 t;
314
315 mutex_lock(&reg_mutex);
316 t = __ar7240sw_reg_read(mii, reg);
317 t |= val;
318 __ar7240sw_reg_write(mii, reg, t);
319 mutex_unlock(&reg_mutex);
320 }
321
322 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
323 unsigned timeout)
324 {
325 int i;
326
327 for (i = 0; i < timeout; i++) {
328 u32 t;
329
330 t = __ar7240sw_reg_read(mii, reg);
331 if ((t & mask) == val)
332 return 0;
333
334 msleep(1);
335 }
336
337 return -ETIMEDOUT;
338 }
339
340 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
341 unsigned timeout)
342 {
343 int ret;
344
345 mutex_lock(&reg_mutex);
346 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
347 mutex_unlock(&reg_mutex);
348 return ret;
349 }
350
351 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
352 unsigned reg_addr)
353 {
354 u32 t, val = 0xffff;
355 int err;
356
357 if (phy_addr >= AR7240_NUM_PHYS)
358 return 0xffff;
359
360 mutex_lock(&reg_mutex);
361 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
362 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
363 AR7240_MDIO_CTRL_MASTER_EN |
364 AR7240_MDIO_CTRL_BUSY |
365 AR7240_MDIO_CTRL_CMD_READ;
366
367 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
368 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
369 AR7240_MDIO_CTRL_BUSY, 0, 5);
370 if (!err)
371 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
372 mutex_unlock(&reg_mutex);
373
374 return val & AR7240_MDIO_CTRL_DATA_M;
375 }
376
377 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
378 unsigned reg_addr, u16 reg_val)
379 {
380 u32 t;
381 int ret;
382
383 if (phy_addr >= AR7240_NUM_PHYS)
384 return -EINVAL;
385
386 mutex_lock(&reg_mutex);
387 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
388 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
389 AR7240_MDIO_CTRL_MASTER_EN |
390 AR7240_MDIO_CTRL_BUSY |
391 AR7240_MDIO_CTRL_CMD_WRITE |
392 reg_val;
393
394 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
395 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
396 AR7240_MDIO_CTRL_BUSY, 0, 5);
397 mutex_unlock(&reg_mutex);
398
399 return ret;
400 }
401
402 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
403 {
404 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
405 AR7240_PORT_CTRL_STATE_DISABLED);
406 }
407
408 static void ar7240sw_setup(struct ar7240sw *as)
409 {
410 struct mii_bus *mii = as->mii_bus;
411
412 /* Enable CPU port, and disable mirror port */
413 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
414 AR7240_CPU_PORT_EN |
415 (15 << AR7240_MIRROR_PORT_S));
416
417 /* Setup TAG priority mapping */
418 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
419
420 /* Enable ARP frame acknowledge, aging, MAC replacing */
421 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
422 0x2b /* 5 min age time */ |
423 AR7240_AT_CTRL_AGE_EN |
424 AR7240_AT_CTRL_ARP_EN |
425 AR7240_AT_CTRL_LEARN_CHANGE);
426
427 /* Enable Broadcast frames transmitted to the CPU */
428 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
429 AR7240_FLOOD_MASK_BROAD_TO_CPU);
430
431 /* setup MTU */
432 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
433 1536);
434
435 /* setup Service TAG */
436 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
437 }
438
439 static int ar7240sw_reset(struct ar7240sw *as)
440 {
441 struct mii_bus *mii = as->mii_bus;
442 int ret;
443 int i;
444
445 /* Set all ports to disabled state. */
446 for (i = 0; i < AR7240_NUM_PORTS; i++)
447 ar7240sw_disable_port(as, i);
448
449 /* Wait for transmit queues to drain. */
450 msleep(2);
451
452 /* Reset the switch. */
453 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
454 AR7240_MASK_CTRL_SOFT_RESET);
455
456 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
457 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
458
459 ar7240sw_setup(as);
460 return ret;
461 }
462
463 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
464 {
465 struct mii_bus *mii = as->mii_bus;
466 u32 ctrl;
467 u32 vlan;
468
469 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
470 AR7240_PORT_CTRL_SINGLE_VLAN;
471
472 if (port == AR7240_PORT_CPU) {
473 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
474 AR7240_PORT_STATUS_SPEED_1000 |
475 AR7240_PORT_STATUS_TXFLOW |
476 AR7240_PORT_STATUS_RXFLOW |
477 AR7240_PORT_STATUS_TXMAC |
478 AR7240_PORT_STATUS_RXMAC |
479 AR7240_PORT_STATUS_DUPLEX);
480 } else {
481 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
482 AR7240_PORT_STATUS_LINK_AUTO);
483 }
484
485 /* Set the default VID for this port */
486 if (as->vlan) {
487 vlan = as->vlan_id[as->pvid[port]];
488 vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
489 AR7240_PORT_VLAN_MODE_S;
490 } else {
491 vlan = port;
492 vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
493 AR7240_PORT_VLAN_MODE_S;
494 }
495
496 if (as->vlan && (as->vlan_tagged & BIT(port))) {
497 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
498 AR7240_PORT_CTRL_VLAN_MODE_S;
499 } else {
500 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
501 AR7240_PORT_CTRL_VLAN_MODE_S;
502 }
503
504 if (!portmask) {
505 if (port == AR7240_PORT_CPU)
506 portmask = AR7240_PORT_MASK_BUT(AR7240_PORT_CPU);
507 else
508 portmask = AR7240_PORT_MASK(AR7240_PORT_CPU);
509 }
510
511 /* allow the port to talk to all other ports, but exclude its
512 * own ID to prevent frames from being reflected back to the
513 * port that they came from */
514 portmask &= AR7240_PORT_MASK_BUT(port);
515
516 /* set default VID and and destination ports for this VLAN */
517 vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
518
519 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
520 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
521 }
522
523 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
524 {
525 struct mii_bus *mii = as->mii_bus;
526 u32 t;
527
528 t = (addr[4] << 8) | addr[5];
529 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
530
531 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
532 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
533
534 return 0;
535 }
536
537 static int
538 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
539 struct switch_val *val)
540 {
541 struct ar7240sw *as = sw_to_ar7240(dev);
542 as->vlan_id[val->port_vlan] = val->value.i;
543 return 0;
544 }
545
546 static int
547 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
548 struct switch_val *val)
549 {
550 struct ar7240sw *as = sw_to_ar7240(dev);
551 val->value.i = as->vlan_id[val->port_vlan];
552 return 0;
553 }
554
555 static int
556 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
557 {
558 struct ar7240sw *as = sw_to_ar7240(dev);
559
560 /* make sure no invalid PVIDs get set */
561
562 if (vlan >= dev->vlans)
563 return -EINVAL;
564
565 as->pvid[port] = vlan;
566 return 0;
567 }
568
569 static int
570 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
571 {
572 struct ar7240sw *as = sw_to_ar7240(dev);
573 *vlan = as->pvid[port];
574 return 0;
575 }
576
577 static int
578 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
579 {
580 struct ar7240sw *as = sw_to_ar7240(dev);
581 u8 ports = as->vlan_table[val->port_vlan];
582 int i;
583
584 val->len = 0;
585 for (i = 0; i < AR7240_NUM_PORTS; i++) {
586 struct switch_port *p;
587
588 if (!(ports & (1 << i)))
589 continue;
590
591 p = &val->value.ports[val->len++];
592 p->id = i;
593 if (as->vlan_tagged & (1 << i))
594 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
595 else
596 p->flags = 0;
597 }
598 return 0;
599 }
600
601 static int
602 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
603 {
604 struct ar7240sw *as = sw_to_ar7240(dev);
605 u8 *vt = &as->vlan_table[val->port_vlan];
606 int i, j;
607
608 *vt = 0;
609 for (i = 0; i < val->len; i++) {
610 struct switch_port *p = &val->value.ports[i];
611
612 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
613 as->vlan_tagged |= (1 << p->id);
614 else {
615 as->vlan_tagged &= ~(1 << p->id);
616 as->pvid[p->id] = val->port_vlan;
617
618 /* make sure that an untagged port does not
619 * appear in other vlans */
620 for (j = 0; j < AR7240_MAX_VLANS; j++) {
621 if (j == val->port_vlan)
622 continue;
623 as->vlan_table[j] &= ~(1 << p->id);
624 }
625 }
626
627 *vt |= 1 << p->id;
628 }
629 return 0;
630 }
631
632 static int
633 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
634 struct switch_val *val)
635 {
636 struct ar7240sw *as = sw_to_ar7240(dev);
637 as->vlan = !!val->value.i;
638 return 0;
639 }
640
641 static int
642 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
643 struct switch_val *val)
644 {
645 struct ar7240sw *as = sw_to_ar7240(dev);
646 val->value.i = as->vlan;
647 return 0;
648 }
649
650 static const char *
651 ar7240_speed_str(u32 status)
652 {
653 u32 speed;
654
655 speed = (status >> AR7240_PORT_STATUS_SPEED_S) &
656 AR7240_PORT_STATUS_SPEED_M;
657 switch (speed) {
658 case AR7240_PORT_STATUS_SPEED_10:
659 return "10baseT";
660 case AR7240_PORT_STATUS_SPEED_100:
661 return "100baseT";
662 case AR7240_PORT_STATUS_SPEED_1000:
663 return "1000baseT";
664 }
665
666 return "unknown";
667 }
668
669 static int
670 ar7240_port_get_link(struct switch_dev *dev, const struct switch_attr *attr,
671 struct switch_val *val)
672 {
673 struct ar7240sw *as = sw_to_ar7240(dev);
674 struct mii_bus *mii = as->mii_bus;
675 u32 len;
676 u32 status;
677 int port;
678
679 port = val->port_vlan;
680
681 memset(as->buf, '\0', sizeof(as->buf));
682 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
683
684 if (status & AR7240_PORT_STATUS_LINK_UP) {
685 len = snprintf(as->buf, sizeof(as->buf),
686 "port:%d link:up speed:%s %s-duplex %s%s%s",
687 port,
688 ar7240_speed_str(status),
689 (status & AR7240_PORT_STATUS_DUPLEX) ?
690 "full" : "half",
691 (status & AR7240_PORT_STATUS_TXFLOW) ?
692 "txflow ": "",
693 (status & AR7240_PORT_STATUS_RXFLOW) ?
694 "rxflow " : "",
695 (status & AR7240_PORT_STATUS_LINK_AUTO) ?
696 "auto ": "");
697 } else {
698 len = snprintf(as->buf, sizeof(as->buf),
699 "port:%d link:down", port);
700 }
701
702 val->value.s = as->buf;
703 val->len = len;
704
705 return 0;
706 }
707
708 static void
709 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
710 {
711 struct mii_bus *mii = as->mii_bus;
712
713 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
714 return;
715
716 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
717 val &= AR7240_VTUDATA_MEMBER;
718 val |= AR7240_VTUDATA_VALID;
719 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
720 }
721 op |= AR7240_VTU_ACTIVE;
722 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
723 }
724
725 static int
726 ar7240_hw_apply(struct switch_dev *dev)
727 {
728 struct ar7240sw *as = sw_to_ar7240(dev);
729 u8 portmask[AR7240_NUM_PORTS];
730 int i, j;
731
732 /* flush all vlan translation unit entries */
733 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
734
735 memset(portmask, 0, sizeof(portmask));
736 if (as->vlan) {
737 /* calculate the port destination masks and load vlans
738 * into the vlan translation unit */
739 for (j = 0; j < AR7240_MAX_VLANS; j++) {
740 u8 vp = as->vlan_table[j];
741
742 if (!vp)
743 continue;
744
745 for (i = 0; i < AR7240_NUM_PORTS; i++) {
746 u8 mask = (1 << i);
747 if (vp & mask)
748 portmask[i] |= vp & ~mask;
749 }
750
751 ar7240_vtu_op(as,
752 AR7240_VTU_OP_LOAD |
753 (as->vlan_id[j] << AR7240_VTU_VID_S),
754 as->vlan_table[j]);
755 }
756 } else {
757 /* vlan disabled:
758 * isolate all ports, but connect them to the cpu port */
759 for (i = 0; i < AR7240_NUM_PORTS; i++) {
760 if (i == AR7240_PORT_CPU)
761 continue;
762
763 portmask[i] = 1 << AR7240_PORT_CPU;
764 portmask[AR7240_PORT_CPU] |= (1 << i);
765 }
766 }
767
768 /* update the port destination mask registers and tag settings */
769 for (i = 0; i < AR7240_NUM_PORTS; i++)
770 ar7240sw_setup_port(as, i, portmask[i]);
771
772 return 0;
773 }
774
775 static int
776 ar7240_reset_switch(struct switch_dev *dev)
777 {
778 struct ar7240sw *as = sw_to_ar7240(dev);
779 ar7240sw_reset(as);
780 return 0;
781 }
782
783 static struct switch_attr ar7240_globals[] = {
784 {
785 .type = SWITCH_TYPE_INT,
786 .name = "enable_vlan",
787 .description = "Enable VLAN mode",
788 .set = ar7240_set_vlan,
789 .get = ar7240_get_vlan,
790 .max = 1
791 },
792 };
793
794 static struct switch_attr ar7240_port[] = {
795 {
796 .type = SWITCH_TYPE_STRING,
797 .name = "link",
798 .description = "Get port link information",
799 .max = 1,
800 .set = NULL,
801 .get = ar7240_port_get_link,
802 },
803 };
804
805 static struct switch_attr ar7240_vlan[] = {
806 {
807 .type = SWITCH_TYPE_INT,
808 .name = "vid",
809 .description = "VLAN ID",
810 .set = ar7240_set_vid,
811 .get = ar7240_get_vid,
812 .max = 4094,
813 },
814 };
815
816 static const struct switch_dev_ops ar7240_ops = {
817 .attr_global = {
818 .attr = ar7240_globals,
819 .n_attr = ARRAY_SIZE(ar7240_globals),
820 },
821 .attr_port = {
822 .attr = ar7240_port,
823 .n_attr = ARRAY_SIZE(ar7240_port),
824 },
825 .attr_vlan = {
826 .attr = ar7240_vlan,
827 .n_attr = ARRAY_SIZE(ar7240_vlan),
828 },
829 .get_port_pvid = ar7240_get_pvid,
830 .set_port_pvid = ar7240_set_pvid,
831 .get_vlan_ports = ar7240_get_ports,
832 .set_vlan_ports = ar7240_set_ports,
833 .apply_config = ar7240_hw_apply,
834 .reset_switch = ar7240_reset_switch,
835 };
836
837 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
838 {
839 struct mii_bus *mii = ag->mii_bus;
840 struct ar7240sw *as;
841 struct switch_dev *swdev;
842 u32 ctrl;
843 u16 phy_id1;
844 u16 phy_id2;
845 u8 ver;
846 int i;
847
848 as = kzalloc(sizeof(*as), GFP_KERNEL);
849 if (!as)
850 return NULL;
851
852 ar7240sw_init(as, mii);
853
854 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
855
856 ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M;
857 if (ver != 1) {
858 pr_err("%s: unsupported chip, ctrl=%08x\n",
859 ag->dev->name, ctrl);
860 return NULL;
861 }
862
863 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
864 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
865 if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) {
866 pr_err("%s: unknown phy id '%04x:%04x'\n",
867 ag->dev->name, phy_id1, phy_id2);
868 return NULL;
869 }
870
871 swdev = &as->swdev;
872 swdev->name = "AR7240 built-in switch";
873 swdev->ports = AR7240_NUM_PORTS;
874 swdev->cpu_port = AR7240_PORT_CPU;
875 swdev->vlans = AR7240_MAX_VLANS;
876 swdev->ops = &ar7240_ops;
877
878 if (register_switch(&as->swdev, ag->dev) < 0) {
879 kfree(as);
880 return NULL;
881 }
882
883 pr_info("%s: Found an AR7240 built-in switch\n", ag->dev->name);
884
885 /* initialize defaults */
886 for (i = 0; i < AR7240_MAX_VLANS; i++)
887 as->vlan_id[i] = i;
888
889 as->vlan_table[0] = AR7240_PORT_MASK_ALL;
890
891 return as;
892 }
893
894 static void link_function(struct work_struct *work) {
895 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
896 unsigned long flags;
897 int i;
898 int status = 0;
899
900 for (i = 0; i < 4; i++) {
901 int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
902 if(link & BMSR_LSTATUS) {
903 status = 1;
904 break;
905 }
906 }
907
908 spin_lock_irqsave(&ag->lock, flags);
909 if(status != ag->link) {
910 ag->link = status;
911 ag71xx_link_adjust(ag);
912 }
913 spin_unlock_irqrestore(&ag->lock, flags);
914
915 schedule_delayed_work(&ag->link_work, HZ / 2);
916 }
917
918 void ag71xx_ar7240_start(struct ag71xx *ag)
919 {
920 struct ar7240sw *as = ag->phy_priv;
921
922 ar7240sw_reset(as);
923
924 ag->speed = SPEED_1000;
925 ag->duplex = 1;
926
927 ar7240_set_addr(as, ag->dev->dev_addr);
928 ar7240_hw_apply(&as->swdev);
929
930 schedule_delayed_work(&ag->link_work, HZ / 10);
931 }
932
933 void ag71xx_ar7240_stop(struct ag71xx *ag)
934 {
935 cancel_delayed_work_sync(&ag->link_work);
936 }
937
938 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
939 {
940 struct ar7240sw *as;
941
942 as = ar7240_probe(ag);
943 if (!as)
944 return -ENODEV;
945
946 ag->phy_priv = as;
947 ar7240sw_reset(as);
948
949 INIT_DELAYED_WORK(&ag->link_work, link_function);
950
951 return 0;
952 }
953
954 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
955 {
956 struct ar7240sw *as = ag->phy_priv;
957
958 if (!as)
959 return;
960
961 unregister_switch(&as->swdev);
962 kfree(as);
963 ag->phy_priv = NULL;
964 }