ar71xx: ag71xx: fix section mismatch warnings
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
29
30 #define AR7240_REG_MAC_ADDR0 0x20
31 #define AR7240_REG_MAC_ADDR1 0x24
32
33 #define AR7240_REG_FLOOD_MASK 0x2c
34 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
35
36 #define AR7240_REG_GLOBAL_CTRL 0x30
37 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
38
39 #define AR7240_REG_VTU 0x0040
40 #define AR7240_VTU_OP BITM(3)
41 #define AR7240_VTU_OP_NOOP 0x0
42 #define AR7240_VTU_OP_FLUSH 0x1
43 #define AR7240_VTU_OP_LOAD 0x2
44 #define AR7240_VTU_OP_PURGE 0x3
45 #define AR7240_VTU_OP_REMOVE_PORT 0x4
46 #define AR7240_VTU_ACTIVE BIT(3)
47 #define AR7240_VTU_FULL BIT(4)
48 #define AR7240_VTU_PORT BITS(8, 4)
49 #define AR7240_VTU_PORT_S 8
50 #define AR7240_VTU_VID BITS(16, 12)
51 #define AR7240_VTU_VID_S 16
52 #define AR7240_VTU_PRIO BITS(28, 3)
53 #define AR7240_VTU_PRIO_S 28
54 #define AR7240_VTU_PRIO_EN BIT(31)
55
56 #define AR7240_REG_VTU_DATA 0x0044
57 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
58 #define AR7240_VTUDATA_VALID BIT(11)
59
60 #define AR7240_REG_AT_CTRL 0x5c
61 #define AR7240_AT_CTRL_ARP_EN BIT(20)
62
63 #define AR7240_REG_TAG_PRIORITY 0x70
64
65 #define AR7240_REG_SERVICE_TAG 0x74
66 #define AR7240_SERVICE_TAG_M BITM(16)
67
68 #define AR7240_REG_CPU_PORT 0x78
69 #define AR7240_MIRROR_PORT_S 4
70 #define AR7240_CPU_PORT_EN BIT(8)
71
72 #define AR7240_REG_MIB_FUNCTION0 0x80
73 #define AR7240_MIB_TIMER_M BITM(16)
74 #define AR7240_MIB_AT_HALF_EN BIT(16)
75 #define AR7240_MIB_BUSY BIT(17)
76 #define AR7240_MIB_FUNC_S 24
77 #define AR7240_MIB_FUNC_NO_OP 0x0
78 #define AR7240_MIB_FUNC_FLUSH 0x1
79 #define AR7240_MIB_FUNC_CAPTURE 0x3
80
81 #define AR7240_REG_MDIO_CTRL 0x98
82 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
83 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
84 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
85 #define AR7240_MDIO_CTRL_CMD_WRITE 0
86 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
87 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
88 #define AR7240_MDIO_CTRL_BUSY BIT(31)
89
90 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
91
92 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
93 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
94 #define AR7240_PORT_STATUS_SPEED_10 0
95 #define AR7240_PORT_STATUS_SPEED_100 1
96 #define AR7240_PORT_STATUS_SPEED_1000 2
97 #define AR7240_PORT_STATUS_TXMAC BIT(2)
98 #define AR7240_PORT_STATUS_RXMAC BIT(3)
99 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
100 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
101 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
102 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
103 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
104 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
105
106 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
107 #define AR7240_PORT_CTRL_STATE_M BITM(3)
108 #define AR7240_PORT_CTRL_STATE_DISABLED 0
109 #define AR7240_PORT_CTRL_STATE_BLOCK 1
110 #define AR7240_PORT_CTRL_STATE_LISTEN 2
111 #define AR7240_PORT_CTRL_STATE_LEARN 3
112 #define AR7240_PORT_CTRL_STATE_FORWARD 4
113 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
114 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
115 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
116 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
117 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
118 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
119 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
120 #define AR7240_PORT_CTRL_HEADER BIT(11)
121 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
122 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
123 #define AR7240_PORT_CTRL_LEARN BIT(14)
124 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
125 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
126 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
127
128 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
129
130 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
131 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
132 #define AR7240_PORT_VLAN_MODE_S 30
133 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
134 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
135 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
136 #define AR7240_PORT_VLAN_MODE_SECURE 3
137
138
139 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
140
141 #define AR7240_STATS_RXBROAD 0x00
142 #define AR7240_STATS_RXPAUSE 0x04
143 #define AR7240_STATS_RXMULTI 0x08
144 #define AR7240_STATS_RXFCSERR 0x0c
145 #define AR7240_STATS_RXALIGNERR 0x10
146 #define AR7240_STATS_RXRUNT 0x14
147 #define AR7240_STATS_RXFRAGMENT 0x18
148 #define AR7240_STATS_RX64BYTE 0x1c
149 #define AR7240_STATS_RX128BYTE 0x20
150 #define AR7240_STATS_RX256BYTE 0x24
151 #define AR7240_STATS_RX512BYTE 0x28
152 #define AR7240_STATS_RX1024BYTE 0x2c
153 #define AR7240_STATS_RX1518BYTE 0x30
154 #define AR7240_STATS_RXMAXBYTE 0x34
155 #define AR7240_STATS_RXTOOLONG 0x38
156 #define AR7240_STATS_RXGOODBYTE 0x3c
157 #define AR7240_STATS_RXBADBYTE 0x44
158 #define AR7240_STATS_RXOVERFLOW 0x4c
159 #define AR7240_STATS_FILTERED 0x50
160 #define AR7240_STATS_TXBROAD 0x54
161 #define AR7240_STATS_TXPAUSE 0x58
162 #define AR7240_STATS_TXMULTI 0x5c
163 #define AR7240_STATS_TXUNDERRUN 0x60
164 #define AR7240_STATS_TX64BYTE 0x64
165 #define AR7240_STATS_TX128BYTE 0x68
166 #define AR7240_STATS_TX256BYTE 0x6c
167 #define AR7240_STATS_TX512BYTE 0x70
168 #define AR7240_STATS_TX1024BYTE 0x74
169 #define AR7240_STATS_TX1518BYTE 0x78
170 #define AR7240_STATS_TXMAXBYTE 0x7c
171 #define AR7240_STATS_TXOVERSIZE 0x80
172 #define AR7240_STATS_TXBYTE 0x84
173 #define AR7240_STATS_TXCOLLISION 0x8c
174 #define AR7240_STATS_TXABORTCOL 0x90
175 #define AR7240_STATS_TXMULTICOL 0x94
176 #define AR7240_STATS_TXSINGLECOL 0x98
177 #define AR7240_STATS_TXEXCDEFER 0x9c
178 #define AR7240_STATS_TXDEFER 0xa0
179 #define AR7240_STATS_TXLATECOL 0xa4
180
181 #define AR7240_PORT_CPU 0
182 #define AR7240_NUM_PORTS 6
183 #define AR7240_NUM_PHYS 5
184
185 #define AR7240_PHY_ID1 0x004d
186 #define AR7240_PHY_ID2 0xd041
187
188 #define AR7240_PORT_MASK(_port) BIT((_port))
189 #define AR7240_PORT_MASK_ALL BITM(AR7240_NUM_PORTS)
190 #define AR7240_PORT_MASK_BUT(_port) (AR7240_PORT_MASK_ALL & ~BIT((_port)))
191
192 #define AR7240_MAX_VLANS 16
193
194 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
195
196 struct ar7240sw {
197 struct mii_bus *mii_bus;
198 struct switch_dev swdev;
199 bool vlan;
200 u16 vlan_id[AR7240_MAX_VLANS];
201 u8 vlan_table[AR7240_MAX_VLANS];
202 u8 vlan_tagged;
203 u16 pvid[AR7240_NUM_PORTS];
204 };
205
206 struct ar7240sw_hw_stat {
207 char string[ETH_GSTRING_LEN];
208 int sizeof_stat;
209 int reg;
210 };
211
212 static DEFINE_MUTEX(reg_mutex);
213
214 static inline void ar7240sw_init(struct ar7240sw *as, struct mii_bus *mii)
215 {
216 as->mii_bus = mii;
217 }
218
219 static inline u16 mk_phy_addr(u32 reg)
220 {
221 return 0x17 & ((reg >> 4) | 0x10);
222 }
223
224 static inline u16 mk_phy_reg(u32 reg)
225 {
226 return (reg << 1) & 0x1e;
227 }
228
229 static inline u16 mk_high_addr(u32 reg)
230 {
231 return (reg >> 7) & 0x1ff;
232 }
233
234 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
235 {
236 u16 phy_addr;
237 u16 phy_reg;
238 u32 hi, lo;
239
240 reg = (reg & 0xfffffffc) >> 2;
241
242 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
243
244 phy_addr = mk_phy_addr(reg);
245 phy_reg = mk_phy_reg(reg);
246
247 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
248 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
249
250 return (hi << 16) | lo;
251 }
252
253 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
254 {
255 u16 phy_addr;
256 u16 phy_reg;
257
258 reg = (reg & 0xfffffffc) >> 2;
259
260 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
261
262 phy_addr = mk_phy_addr(reg);
263 phy_reg = mk_phy_reg(reg);
264
265 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
266 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
267 }
268
269 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
270 {
271 u32 ret;
272
273 mutex_lock(&reg_mutex);
274 ret = __ar7240sw_reg_read(mii, reg_addr);
275 mutex_unlock(&reg_mutex);
276
277 return ret;
278 }
279
280 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
281 {
282 mutex_lock(&reg_mutex);
283 __ar7240sw_reg_write(mii, reg_addr, reg_val);
284 mutex_unlock(&reg_mutex);
285 }
286
287 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
288 {
289 u32 t;
290
291 mutex_lock(&reg_mutex);
292 t = __ar7240sw_reg_read(mii, reg);
293 t &= ~mask;
294 t |= val;
295 __ar7240sw_reg_write(mii, reg, t);
296 mutex_unlock(&reg_mutex);
297
298 return t;
299 }
300
301 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
302 {
303 u32 t;
304
305 mutex_lock(&reg_mutex);
306 t = __ar7240sw_reg_read(mii, reg);
307 t |= val;
308 __ar7240sw_reg_write(mii, reg, t);
309 mutex_unlock(&reg_mutex);
310 }
311
312 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
313 unsigned timeout)
314 {
315 int i;
316
317 for (i = 0; i < timeout; i++) {
318 u32 t;
319
320 t = __ar7240sw_reg_read(mii, reg);
321 if ((t & mask) == val)
322 return 0;
323
324 msleep(1);
325 }
326
327 return -ETIMEDOUT;
328 }
329
330 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
331 unsigned timeout)
332 {
333 int ret;
334
335 mutex_lock(&reg_mutex);
336 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
337 mutex_unlock(&reg_mutex);
338 return ret;
339 }
340
341 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
342 unsigned reg_addr)
343 {
344 u32 t, val = 0xffff;
345 int err;
346
347 if (phy_addr >= AR7240_NUM_PHYS)
348 return 0xffff;
349
350 mutex_lock(&reg_mutex);
351 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
352 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
353 AR7240_MDIO_CTRL_MASTER_EN |
354 AR7240_MDIO_CTRL_BUSY |
355 AR7240_MDIO_CTRL_CMD_READ;
356
357 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
358 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
359 AR7240_MDIO_CTRL_BUSY, 0, 5);
360 if (!err)
361 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
362 mutex_unlock(&reg_mutex);
363
364 return val & AR7240_MDIO_CTRL_DATA_M;
365 }
366
367 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
368 unsigned reg_addr, u16 reg_val)
369 {
370 u32 t;
371 int ret;
372
373 if (phy_addr >= AR7240_NUM_PHYS)
374 return -EINVAL;
375
376 mutex_lock(&reg_mutex);
377 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
378 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
379 AR7240_MDIO_CTRL_MASTER_EN |
380 AR7240_MDIO_CTRL_BUSY |
381 AR7240_MDIO_CTRL_CMD_WRITE |
382 reg_val;
383
384 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
385 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
386 AR7240_MDIO_CTRL_BUSY, 0, 5);
387 mutex_unlock(&reg_mutex);
388
389 return ret;
390 }
391
392 static int ar7240sw_capture_stats(struct ar7240sw *as)
393 {
394 struct mii_bus *mii = as->mii_bus;
395 int ret;
396
397 /* Capture the hardware statistics for all ports */
398 ar7240sw_reg_write(mii, AR7240_REG_MIB_FUNCTION0,
399 (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
400
401 /* Wait for the capturing to complete. */
402 ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
403 AR7240_MIB_BUSY, 0, 10);
404 return ret;
405 }
406
407 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
408 {
409 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
410 AR7240_PORT_CTRL_STATE_DISABLED);
411 }
412
413 static int ar7240sw_reset(struct ar7240sw *as)
414 {
415 struct mii_bus *mii = as->mii_bus;
416 int ret;
417 int i;
418
419 /* Set all ports to disabled state. */
420 for (i = 0; i < AR7240_NUM_PORTS; i++)
421 ar7240sw_disable_port(as, i);
422
423 /* Wait for transmit queues to drain. */
424 msleep(2);
425
426 /* Reset the switch. */
427 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
428 AR7240_MASK_CTRL_SOFT_RESET);
429
430 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
431 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
432 return ret;
433 }
434
435 static void ar7240sw_setup(struct ar7240sw *as)
436 {
437 struct mii_bus *mii = as->mii_bus;
438
439 /* Enable CPU port, and disable mirror port */
440 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
441 AR7240_CPU_PORT_EN |
442 (15 << AR7240_MIRROR_PORT_S));
443
444 /* Setup TAG priority mapping */
445 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
446
447 /* Enable ARP frame acknowledge */
448 ar7240sw_reg_set(mii, AR7240_REG_AT_CTRL, AR7240_AT_CTRL_ARP_EN);
449
450 /* Enable Broadcast frames transmitted to the CPU */
451 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
452 AR7240_FLOOD_MASK_BROAD_TO_CPU);
453
454 /* setup MTU */
455 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
456 1536);
457
458 /* setup Service TAG */
459 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
460 }
461
462 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
463 {
464 struct mii_bus *mii = as->mii_bus;
465 u32 ctrl;
466 u32 dest_ports;
467 u32 vlan;
468
469 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
470 AR7240_PORT_CTRL_SINGLE_VLAN;
471
472 if (port == AR7240_PORT_CPU) {
473 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
474 AR7240_PORT_STATUS_SPEED_1000 |
475 AR7240_PORT_STATUS_TXFLOW |
476 AR7240_PORT_STATUS_RXFLOW |
477 AR7240_PORT_STATUS_TXMAC |
478 AR7240_PORT_STATUS_RXMAC |
479 AR7240_PORT_STATUS_DUPLEX);
480 } else {
481 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
482 AR7240_PORT_STATUS_LINK_AUTO);
483 }
484
485 /* Set the default VID for this port */
486 if (as->vlan) {
487 vlan = as->vlan_id[as->pvid[port]];
488 vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
489 AR7240_PORT_VLAN_MODE_S;
490 } else {
491 vlan = port;
492 vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
493 AR7240_PORT_VLAN_MODE_S;
494 }
495
496 if (as->vlan && (as->vlan_tagged & BIT(port))) {
497 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
498 AR7240_PORT_CTRL_VLAN_MODE_S;
499 } else {
500 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
501 AR7240_PORT_CTRL_VLAN_MODE_S;
502 }
503
504 if (!portmask) {
505 if (port == AR7240_PORT_CPU)
506 portmask = AR7240_PORT_MASK_BUT(AR7240_PORT_CPU);
507 else
508 portmask = AR7240_PORT_MASK(AR7240_PORT_CPU);
509 }
510
511 /* allow the port to talk to all other ports, but exclude its
512 * own ID to prevent frames from being reflected back to the
513 * port that they came from */
514 dest_ports = AR7240_PORT_MASK_BUT(port);
515
516 /* set default VID and and destination ports for this VLAN */
517 vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
518
519 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
520 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
521 }
522
523 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
524 {
525 struct mii_bus *mii = as->mii_bus;
526 u32 t;
527
528 t = (addr[4] << 8) | addr[5];
529 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
530
531 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
532 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
533
534 return 0;
535 }
536
537 static int
538 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
539 struct switch_val *val)
540 {
541 struct ar7240sw *as = sw_to_ar7240(dev);
542 as->vlan_id[val->port_vlan] = val->value.i;
543 return 0;
544 }
545
546 static int
547 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
548 struct switch_val *val)
549 {
550 struct ar7240sw *as = sw_to_ar7240(dev);
551 val->value.i = as->vlan_id[val->port_vlan];
552 return 0;
553 }
554
555 static int
556 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
557 {
558 struct ar7240sw *as = sw_to_ar7240(dev);
559
560 /* make sure no invalid PVIDs get set */
561
562 if (vlan >= dev->vlans)
563 return -EINVAL;
564
565 as->pvid[port] = vlan;
566 return 0;
567 }
568
569 static int
570 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
571 {
572 struct ar7240sw *as = sw_to_ar7240(dev);
573 *vlan = as->pvid[port];
574 return 0;
575 }
576
577 static int
578 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
579 {
580 struct ar7240sw *as = sw_to_ar7240(dev);
581 u8 ports = as->vlan_table[val->port_vlan];
582 int i;
583
584 val->len = 0;
585 for (i = 0; i < AR7240_NUM_PORTS; i++) {
586 struct switch_port *p;
587
588 if (!(ports & (1 << i)))
589 continue;
590
591 p = &val->value.ports[val->len++];
592 p->id = i;
593 if (as->vlan_tagged & (1 << i))
594 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
595 else
596 p->flags = 0;
597 }
598 return 0;
599 }
600
601 static int
602 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
603 {
604 struct ar7240sw *as = sw_to_ar7240(dev);
605 u8 *vt = &as->vlan_table[val->port_vlan];
606 int i, j;
607
608 *vt = 0;
609 for (i = 0; i < val->len; i++) {
610 struct switch_port *p = &val->value.ports[i];
611
612 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
613 as->vlan_tagged |= (1 << p->id);
614 else {
615 as->vlan_tagged &= ~(1 << p->id);
616 as->pvid[p->id] = val->port_vlan;
617
618 /* make sure that an untagged port does not
619 * appear in other vlans */
620 for (j = 0; j < AR7240_MAX_VLANS; j++) {
621 if (j == val->port_vlan)
622 continue;
623 as->vlan_table[j] &= ~(1 << p->id);
624 }
625 }
626
627 *vt |= 1 << p->id;
628 }
629 return 0;
630 }
631
632 static int
633 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
634 struct switch_val *val)
635 {
636 struct ar7240sw *as = sw_to_ar7240(dev);
637 as->vlan = !!val->value.i;
638 return 0;
639 }
640
641 static int
642 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
643 struct switch_val *val)
644 {
645 struct ar7240sw *as = sw_to_ar7240(dev);
646 val->value.i = as->vlan;
647 return 0;
648 }
649
650
651 static void
652 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
653 {
654 struct mii_bus *mii = as->mii_bus;
655
656 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
657 return;
658
659 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
660 val &= AR7240_VTUDATA_MEMBER;
661 val |= AR7240_VTUDATA_VALID;
662 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
663 }
664 op |= AR7240_VTU_ACTIVE;
665 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
666 }
667
668 static int
669 ar7240_hw_apply(struct switch_dev *dev)
670 {
671 struct ar7240sw *as = sw_to_ar7240(dev);
672 u8 portmask[AR7240_NUM_PORTS];
673 int i, j;
674
675 /* flush all vlan translation unit entries */
676 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
677
678 memset(portmask, 0, sizeof(portmask));
679 if (as->vlan) {
680 /* calculate the port destination masks and load vlans
681 * into the vlan translation unit */
682 for (j = 0; j < AR7240_MAX_VLANS; j++) {
683 u8 vp = as->vlan_table[j];
684
685 if (!vp)
686 continue;
687
688 for (i = 0; i < AR7240_NUM_PORTS; i++) {
689 u8 mask = (1 << i);
690 if (vp & mask)
691 portmask[i] |= vp & ~mask;
692 }
693
694 ar7240_vtu_op(as,
695 AR7240_VTU_OP_LOAD |
696 (as->vlan_id[j] << AR7240_VTU_VID_S),
697 as->vlan_table[j]);
698 }
699 } else {
700 /* vlan disabled:
701 * isolate all ports, but connect them to the cpu port */
702 for (i = 0; i < AR7240_NUM_PORTS; i++) {
703 if (i == AR7240_PORT_CPU)
704 continue;
705
706 portmask[i] = 1 << AR7240_PORT_CPU;
707 portmask[AR7240_PORT_CPU] |= (1 << i);
708 }
709 }
710
711 /* update the port destination mask registers and tag settings */
712 for (i = 0; i < AR7240_NUM_PORTS; i++)
713 ar7240sw_setup_port(as, i, portmask[i]);
714
715 return 0;
716 }
717
718 static int
719 ar7240_reset_switch(struct switch_dev *dev)
720 {
721 struct ar7240sw *as = sw_to_ar7240(dev);
722 ar7240sw_reset(as);
723 return 0;
724 }
725
726 static struct switch_attr ar7240_globals[] = {
727 {
728 .type = SWITCH_TYPE_INT,
729 .name = "enable_vlan",
730 .description = "Enable VLAN mode",
731 .set = ar7240_set_vlan,
732 .get = ar7240_get_vlan,
733 .max = 1
734 },
735 };
736
737 static struct switch_attr ar7240_port[] = {
738 };
739
740 static struct switch_attr ar7240_vlan[] = {
741 {
742 .type = SWITCH_TYPE_INT,
743 .name = "vid",
744 .description = "VLAN ID",
745 .set = ar7240_set_vid,
746 .get = ar7240_get_vid,
747 .max = 4094,
748 },
749 };
750
751 static const struct switch_dev_ops ar7240_ops = {
752 .attr_global = {
753 .attr = ar7240_globals,
754 .n_attr = ARRAY_SIZE(ar7240_globals),
755 },
756 .attr_port = {
757 .attr = ar7240_port,
758 .n_attr = ARRAY_SIZE(ar7240_port),
759 },
760 .attr_vlan = {
761 .attr = ar7240_vlan,
762 .n_attr = ARRAY_SIZE(ar7240_vlan),
763 },
764 .get_port_pvid = ar7240_get_pvid,
765 .set_port_pvid = ar7240_set_pvid,
766 .get_vlan_ports = ar7240_get_ports,
767 .set_vlan_ports = ar7240_set_ports,
768 .apply_config = ar7240_hw_apply,
769 .reset_switch = ar7240_reset_switch,
770 };
771
772 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
773 {
774 struct mii_bus *mii = ag->mii_bus;
775 struct ar7240sw *as;
776 struct switch_dev *swdev;
777 u32 ctrl;
778 u16 phy_id1;
779 u16 phy_id2;
780 u8 ver;
781 int i;
782
783 as = kzalloc(sizeof(*as), GFP_KERNEL);
784 if (!as)
785 return NULL;
786
787 ar7240sw_init(as, mii);
788
789 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
790
791 ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M;
792 if (ver != 1) {
793 pr_err("%s: unsupported chip, ctrl=%08x\n",
794 ag->dev->name, ctrl);
795 return NULL;
796 }
797
798 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
799 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
800 if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) {
801 pr_err("%s: unknown phy id '%04x:%04x'\n",
802 ag->dev->name, phy_id1, phy_id2);
803 return NULL;
804 }
805
806 swdev = &as->swdev;
807 swdev->name = "AR7240 built-in switch";
808 swdev->ports = AR7240_NUM_PORTS;
809 swdev->cpu_port = AR7240_PORT_CPU;
810 swdev->vlans = AR7240_MAX_VLANS;
811 swdev->ops = &ar7240_ops;
812
813 if (register_switch(&as->swdev, ag->dev) < 0) {
814 kfree(as);
815 return NULL;
816 }
817
818 pr_info("%s: Found an AR7240 built-in switch\n", ag->dev->name);
819
820 /* initialize defaults */
821 for (i = 0; i < AR7240_MAX_VLANS; i++)
822 as->vlan_id[i] = i;
823
824 as->vlan_table[0] = AR7240_PORT_MASK_ALL;
825
826 return as;
827 }
828
829 void ag71xx_ar7240_start(struct ag71xx *ag)
830 {
831 struct ar7240sw *as = ag->phy_priv;
832
833 ar7240sw_reset(as);
834 ar7240sw_setup(as);
835
836 ag->speed = SPEED_1000;
837 ag->link = 1;
838 ag->duplex = 1;
839
840 ar7240_set_addr(as, ag->dev->dev_addr);
841 ar7240_hw_apply(&as->swdev);
842 }
843
844 void ag71xx_ar7240_stop(struct ag71xx *ag)
845 {
846 }
847
848 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
849 {
850 struct ar7240sw *as;
851
852 as = ar7240_probe(ag);
853 if (!as)
854 return -ENODEV;
855
856 ag->phy_priv = as;
857 ar7240sw_reset(as);
858
859 return 0;
860 }
861
862 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
863 {
864 struct ar7240sw *as = ag->phy_priv;
865
866 if (!as)
867 return;
868
869 unregister_switch(&as->swdev);
870 kfree(as);
871 ag->phy_priv = NULL;
872 }