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ar71xx: reinitialize global switch settings after reset on ar7240
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
29
30 #define AR7240_REG_MAC_ADDR0 0x20
31 #define AR7240_REG_MAC_ADDR1 0x24
32
33 #define AR7240_REG_FLOOD_MASK 0x2c
34 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
35
36 #define AR7240_REG_GLOBAL_CTRL 0x30
37 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
38
39 #define AR7240_REG_VTU 0x0040
40 #define AR7240_VTU_OP BITM(3)
41 #define AR7240_VTU_OP_NOOP 0x0
42 #define AR7240_VTU_OP_FLUSH 0x1
43 #define AR7240_VTU_OP_LOAD 0x2
44 #define AR7240_VTU_OP_PURGE 0x3
45 #define AR7240_VTU_OP_REMOVE_PORT 0x4
46 #define AR7240_VTU_ACTIVE BIT(3)
47 #define AR7240_VTU_FULL BIT(4)
48 #define AR7240_VTU_PORT BITS(8, 4)
49 #define AR7240_VTU_PORT_S 8
50 #define AR7240_VTU_VID BITS(16, 12)
51 #define AR7240_VTU_VID_S 16
52 #define AR7240_VTU_PRIO BITS(28, 3)
53 #define AR7240_VTU_PRIO_S 28
54 #define AR7240_VTU_PRIO_EN BIT(31)
55
56 #define AR7240_REG_VTU_DATA 0x0044
57 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
58 #define AR7240_VTUDATA_VALID BIT(11)
59
60 #define AR7240_REG_ATU 0x50
61 #define AR7240_ATU_FLUSH_ALL 0x1
62
63 #define AR7240_REG_AT_CTRL 0x5c
64 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
65 #define AR7240_AT_CTRL_AGE_EN BIT(17)
66 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
67 #define AR7240_AT_CTRL_ARP_EN BIT(20)
68
69 #define AR7240_REG_TAG_PRIORITY 0x70
70
71 #define AR7240_REG_SERVICE_TAG 0x74
72 #define AR7240_SERVICE_TAG_M BITM(16)
73
74 #define AR7240_REG_CPU_PORT 0x78
75 #define AR7240_MIRROR_PORT_S 4
76 #define AR7240_CPU_PORT_EN BIT(8)
77
78 #define AR7240_REG_MIB_FUNCTION0 0x80
79 #define AR7240_MIB_TIMER_M BITM(16)
80 #define AR7240_MIB_AT_HALF_EN BIT(16)
81 #define AR7240_MIB_BUSY BIT(17)
82 #define AR7240_MIB_FUNC_S 24
83 #define AR7240_MIB_FUNC_NO_OP 0x0
84 #define AR7240_MIB_FUNC_FLUSH 0x1
85 #define AR7240_MIB_FUNC_CAPTURE 0x3
86
87 #define AR7240_REG_MDIO_CTRL 0x98
88 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
89 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
90 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
91 #define AR7240_MDIO_CTRL_CMD_WRITE 0
92 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
93 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
94 #define AR7240_MDIO_CTRL_BUSY BIT(31)
95
96 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
97
98 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
99 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
100 #define AR7240_PORT_STATUS_SPEED_10 0
101 #define AR7240_PORT_STATUS_SPEED_100 1
102 #define AR7240_PORT_STATUS_SPEED_1000 2
103 #define AR7240_PORT_STATUS_TXMAC BIT(2)
104 #define AR7240_PORT_STATUS_RXMAC BIT(3)
105 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
106 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
107 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
108 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
109 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
110 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
111
112 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
113 #define AR7240_PORT_CTRL_STATE_M BITM(3)
114 #define AR7240_PORT_CTRL_STATE_DISABLED 0
115 #define AR7240_PORT_CTRL_STATE_BLOCK 1
116 #define AR7240_PORT_CTRL_STATE_LISTEN 2
117 #define AR7240_PORT_CTRL_STATE_LEARN 3
118 #define AR7240_PORT_CTRL_STATE_FORWARD 4
119 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
120 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
121 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
122 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
123 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
124 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
125 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
126 #define AR7240_PORT_CTRL_HEADER BIT(11)
127 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
128 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
129 #define AR7240_PORT_CTRL_LEARN BIT(14)
130 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
131 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
132 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
133
134 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
135
136 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
137 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
138 #define AR7240_PORT_VLAN_MODE_S 30
139 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
140 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
141 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
142 #define AR7240_PORT_VLAN_MODE_SECURE 3
143
144
145 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
146
147 #define AR7240_STATS_RXBROAD 0x00
148 #define AR7240_STATS_RXPAUSE 0x04
149 #define AR7240_STATS_RXMULTI 0x08
150 #define AR7240_STATS_RXFCSERR 0x0c
151 #define AR7240_STATS_RXALIGNERR 0x10
152 #define AR7240_STATS_RXRUNT 0x14
153 #define AR7240_STATS_RXFRAGMENT 0x18
154 #define AR7240_STATS_RX64BYTE 0x1c
155 #define AR7240_STATS_RX128BYTE 0x20
156 #define AR7240_STATS_RX256BYTE 0x24
157 #define AR7240_STATS_RX512BYTE 0x28
158 #define AR7240_STATS_RX1024BYTE 0x2c
159 #define AR7240_STATS_RX1518BYTE 0x30
160 #define AR7240_STATS_RXMAXBYTE 0x34
161 #define AR7240_STATS_RXTOOLONG 0x38
162 #define AR7240_STATS_RXGOODBYTE 0x3c
163 #define AR7240_STATS_RXBADBYTE 0x44
164 #define AR7240_STATS_RXOVERFLOW 0x4c
165 #define AR7240_STATS_FILTERED 0x50
166 #define AR7240_STATS_TXBROAD 0x54
167 #define AR7240_STATS_TXPAUSE 0x58
168 #define AR7240_STATS_TXMULTI 0x5c
169 #define AR7240_STATS_TXUNDERRUN 0x60
170 #define AR7240_STATS_TX64BYTE 0x64
171 #define AR7240_STATS_TX128BYTE 0x68
172 #define AR7240_STATS_TX256BYTE 0x6c
173 #define AR7240_STATS_TX512BYTE 0x70
174 #define AR7240_STATS_TX1024BYTE 0x74
175 #define AR7240_STATS_TX1518BYTE 0x78
176 #define AR7240_STATS_TXMAXBYTE 0x7c
177 #define AR7240_STATS_TXOVERSIZE 0x80
178 #define AR7240_STATS_TXBYTE 0x84
179 #define AR7240_STATS_TXCOLLISION 0x8c
180 #define AR7240_STATS_TXABORTCOL 0x90
181 #define AR7240_STATS_TXMULTICOL 0x94
182 #define AR7240_STATS_TXSINGLECOL 0x98
183 #define AR7240_STATS_TXEXCDEFER 0x9c
184 #define AR7240_STATS_TXDEFER 0xa0
185 #define AR7240_STATS_TXLATECOL 0xa4
186
187 #define AR7240_PORT_CPU 0
188 #define AR7240_NUM_PORTS 6
189 #define AR7240_NUM_PHYS 5
190
191 #define AR7240_PHY_ID1 0x004d
192 #define AR7240_PHY_ID2 0xd041
193
194 #define AR7240_PORT_MASK(_port) BIT((_port))
195 #define AR7240_PORT_MASK_ALL BITM(AR7240_NUM_PORTS)
196 #define AR7240_PORT_MASK_BUT(_port) (AR7240_PORT_MASK_ALL & ~BIT((_port)))
197
198 #define AR7240_MAX_VLANS 16
199
200 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
201
202 struct ar7240sw {
203 struct mii_bus *mii_bus;
204 struct switch_dev swdev;
205 bool vlan;
206 u16 vlan_id[AR7240_MAX_VLANS];
207 u8 vlan_table[AR7240_MAX_VLANS];
208 u8 vlan_tagged;
209 u16 pvid[AR7240_NUM_PORTS];
210 };
211
212 struct ar7240sw_hw_stat {
213 char string[ETH_GSTRING_LEN];
214 int sizeof_stat;
215 int reg;
216 };
217
218 static DEFINE_MUTEX(reg_mutex);
219
220 static inline void ar7240sw_init(struct ar7240sw *as, struct mii_bus *mii)
221 {
222 as->mii_bus = mii;
223 }
224
225 static inline u16 mk_phy_addr(u32 reg)
226 {
227 return 0x17 & ((reg >> 4) | 0x10);
228 }
229
230 static inline u16 mk_phy_reg(u32 reg)
231 {
232 return (reg << 1) & 0x1e;
233 }
234
235 static inline u16 mk_high_addr(u32 reg)
236 {
237 return (reg >> 7) & 0x1ff;
238 }
239
240 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
241 {
242 unsigned long flags;
243 u16 phy_addr;
244 u16 phy_reg;
245 u32 hi, lo;
246
247 reg = (reg & 0xfffffffc) >> 2;
248 phy_addr = mk_phy_addr(reg);
249 phy_reg = mk_phy_reg(reg);
250
251 local_irq_save(flags);
252 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
253 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
254 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
255 local_irq_restore(flags);
256
257 return (hi << 16) | lo;
258 }
259
260 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
261 {
262 unsigned long flags;
263 u16 phy_addr;
264 u16 phy_reg;
265
266 reg = (reg & 0xfffffffc) >> 2;
267 phy_addr = mk_phy_addr(reg);
268 phy_reg = mk_phy_reg(reg);
269
270 local_irq_save(flags);
271 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
272 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
273 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
274 local_irq_restore(flags);
275 }
276
277 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
278 {
279 u32 ret;
280
281 mutex_lock(&reg_mutex);
282 ret = __ar7240sw_reg_read(mii, reg_addr);
283 mutex_unlock(&reg_mutex);
284
285 return ret;
286 }
287
288 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
289 {
290 mutex_lock(&reg_mutex);
291 __ar7240sw_reg_write(mii, reg_addr, reg_val);
292 mutex_unlock(&reg_mutex);
293 }
294
295 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
296 {
297 u32 t;
298
299 mutex_lock(&reg_mutex);
300 t = __ar7240sw_reg_read(mii, reg);
301 t &= ~mask;
302 t |= val;
303 __ar7240sw_reg_write(mii, reg, t);
304 mutex_unlock(&reg_mutex);
305
306 return t;
307 }
308
309 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
310 {
311 u32 t;
312
313 mutex_lock(&reg_mutex);
314 t = __ar7240sw_reg_read(mii, reg);
315 t |= val;
316 __ar7240sw_reg_write(mii, reg, t);
317 mutex_unlock(&reg_mutex);
318 }
319
320 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
321 unsigned timeout)
322 {
323 int i;
324
325 for (i = 0; i < timeout; i++) {
326 u32 t;
327
328 t = __ar7240sw_reg_read(mii, reg);
329 if ((t & mask) == val)
330 return 0;
331
332 msleep(1);
333 }
334
335 return -ETIMEDOUT;
336 }
337
338 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
339 unsigned timeout)
340 {
341 int ret;
342
343 mutex_lock(&reg_mutex);
344 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
345 mutex_unlock(&reg_mutex);
346 return ret;
347 }
348
349 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
350 unsigned reg_addr)
351 {
352 u32 t, val = 0xffff;
353 int err;
354
355 if (phy_addr >= AR7240_NUM_PHYS)
356 return 0xffff;
357
358 mutex_lock(&reg_mutex);
359 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
360 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
361 AR7240_MDIO_CTRL_MASTER_EN |
362 AR7240_MDIO_CTRL_BUSY |
363 AR7240_MDIO_CTRL_CMD_READ;
364
365 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
366 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
367 AR7240_MDIO_CTRL_BUSY, 0, 5);
368 if (!err)
369 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
370 mutex_unlock(&reg_mutex);
371
372 return val & AR7240_MDIO_CTRL_DATA_M;
373 }
374
375 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
376 unsigned reg_addr, u16 reg_val)
377 {
378 u32 t;
379 int ret;
380
381 if (phy_addr >= AR7240_NUM_PHYS)
382 return -EINVAL;
383
384 mutex_lock(&reg_mutex);
385 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
386 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
387 AR7240_MDIO_CTRL_MASTER_EN |
388 AR7240_MDIO_CTRL_BUSY |
389 AR7240_MDIO_CTRL_CMD_WRITE |
390 reg_val;
391
392 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
393 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
394 AR7240_MDIO_CTRL_BUSY, 0, 5);
395 mutex_unlock(&reg_mutex);
396
397 return ret;
398 }
399
400 static int ar7240sw_capture_stats(struct ar7240sw *as)
401 {
402 struct mii_bus *mii = as->mii_bus;
403 int ret;
404
405 /* Capture the hardware statistics for all ports */
406 ar7240sw_reg_write(mii, AR7240_REG_MIB_FUNCTION0,
407 (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
408
409 /* Wait for the capturing to complete. */
410 ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
411 AR7240_MIB_BUSY, 0, 10);
412 return ret;
413 }
414
415 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
416 {
417 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
418 AR7240_PORT_CTRL_STATE_DISABLED);
419 }
420
421 static void ar7240sw_setup(struct ar7240sw *as)
422 {
423 struct mii_bus *mii = as->mii_bus;
424
425 /* Enable CPU port, and disable mirror port */
426 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
427 AR7240_CPU_PORT_EN |
428 (15 << AR7240_MIRROR_PORT_S));
429
430 /* Setup TAG priority mapping */
431 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
432
433 /* Enable ARP frame acknowledge, aging, MAC replacing */
434 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
435 0x2b /* 5 min age time */ |
436 AR7240_AT_CTRL_AGE_EN |
437 AR7240_AT_CTRL_ARP_EN |
438 AR7240_AT_CTRL_LEARN_CHANGE);
439
440 /* Enable Broadcast frames transmitted to the CPU */
441 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
442 AR7240_FLOOD_MASK_BROAD_TO_CPU);
443
444 /* setup MTU */
445 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
446 1536);
447
448 /* setup Service TAG */
449 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
450 }
451
452 static int ar7240sw_reset(struct ar7240sw *as)
453 {
454 struct mii_bus *mii = as->mii_bus;
455 int ret;
456 int i;
457
458 /* Set all ports to disabled state. */
459 for (i = 0; i < AR7240_NUM_PORTS; i++)
460 ar7240sw_disable_port(as, i);
461
462 /* Wait for transmit queues to drain. */
463 msleep(2);
464
465 /* Reset the switch. */
466 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
467 AR7240_MASK_CTRL_SOFT_RESET);
468
469 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
470 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
471
472 ar7240sw_setup(as);
473 return ret;
474 }
475
476 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
477 {
478 struct mii_bus *mii = as->mii_bus;
479 u32 ctrl;
480 u32 dest_ports;
481 u32 vlan;
482
483 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
484 AR7240_PORT_CTRL_SINGLE_VLAN;
485
486 if (port == AR7240_PORT_CPU) {
487 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
488 AR7240_PORT_STATUS_SPEED_1000 |
489 AR7240_PORT_STATUS_TXFLOW |
490 AR7240_PORT_STATUS_RXFLOW |
491 AR7240_PORT_STATUS_TXMAC |
492 AR7240_PORT_STATUS_RXMAC |
493 AR7240_PORT_STATUS_DUPLEX);
494 } else {
495 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
496 AR7240_PORT_STATUS_LINK_AUTO);
497 }
498
499 /* Set the default VID for this port */
500 if (as->vlan) {
501 vlan = as->vlan_id[as->pvid[port]];
502 vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
503 AR7240_PORT_VLAN_MODE_S;
504 } else {
505 vlan = port;
506 vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
507 AR7240_PORT_VLAN_MODE_S;
508 }
509
510 if (as->vlan && (as->vlan_tagged & BIT(port))) {
511 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
512 AR7240_PORT_CTRL_VLAN_MODE_S;
513 } else {
514 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
515 AR7240_PORT_CTRL_VLAN_MODE_S;
516 }
517
518 if (!portmask) {
519 if (port == AR7240_PORT_CPU)
520 portmask = AR7240_PORT_MASK_BUT(AR7240_PORT_CPU);
521 else
522 portmask = AR7240_PORT_MASK(AR7240_PORT_CPU);
523 }
524
525 /* allow the port to talk to all other ports, but exclude its
526 * own ID to prevent frames from being reflected back to the
527 * port that they came from */
528 dest_ports = AR7240_PORT_MASK_BUT(port);
529
530 /* set default VID and and destination ports for this VLAN */
531 vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
532
533 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
534 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
535 }
536
537 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
538 {
539 struct mii_bus *mii = as->mii_bus;
540 u32 t;
541
542 t = (addr[4] << 8) | addr[5];
543 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
544
545 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
546 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
547
548 return 0;
549 }
550
551 static int
552 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
553 struct switch_val *val)
554 {
555 struct ar7240sw *as = sw_to_ar7240(dev);
556 as->vlan_id[val->port_vlan] = val->value.i;
557 return 0;
558 }
559
560 static int
561 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
562 struct switch_val *val)
563 {
564 struct ar7240sw *as = sw_to_ar7240(dev);
565 val->value.i = as->vlan_id[val->port_vlan];
566 return 0;
567 }
568
569 static int
570 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
571 {
572 struct ar7240sw *as = sw_to_ar7240(dev);
573
574 /* make sure no invalid PVIDs get set */
575
576 if (vlan >= dev->vlans)
577 return -EINVAL;
578
579 as->pvid[port] = vlan;
580 return 0;
581 }
582
583 static int
584 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
585 {
586 struct ar7240sw *as = sw_to_ar7240(dev);
587 *vlan = as->pvid[port];
588 return 0;
589 }
590
591 static int
592 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
593 {
594 struct ar7240sw *as = sw_to_ar7240(dev);
595 u8 ports = as->vlan_table[val->port_vlan];
596 int i;
597
598 val->len = 0;
599 for (i = 0; i < AR7240_NUM_PORTS; i++) {
600 struct switch_port *p;
601
602 if (!(ports & (1 << i)))
603 continue;
604
605 p = &val->value.ports[val->len++];
606 p->id = i;
607 if (as->vlan_tagged & (1 << i))
608 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
609 else
610 p->flags = 0;
611 }
612 return 0;
613 }
614
615 static int
616 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
617 {
618 struct ar7240sw *as = sw_to_ar7240(dev);
619 u8 *vt = &as->vlan_table[val->port_vlan];
620 int i, j;
621
622 *vt = 0;
623 for (i = 0; i < val->len; i++) {
624 struct switch_port *p = &val->value.ports[i];
625
626 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
627 as->vlan_tagged |= (1 << p->id);
628 else {
629 as->vlan_tagged &= ~(1 << p->id);
630 as->pvid[p->id] = val->port_vlan;
631
632 /* make sure that an untagged port does not
633 * appear in other vlans */
634 for (j = 0; j < AR7240_MAX_VLANS; j++) {
635 if (j == val->port_vlan)
636 continue;
637 as->vlan_table[j] &= ~(1 << p->id);
638 }
639 }
640
641 *vt |= 1 << p->id;
642 }
643 return 0;
644 }
645
646 static int
647 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
648 struct switch_val *val)
649 {
650 struct ar7240sw *as = sw_to_ar7240(dev);
651 as->vlan = !!val->value.i;
652 return 0;
653 }
654
655 static int
656 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
657 struct switch_val *val)
658 {
659 struct ar7240sw *as = sw_to_ar7240(dev);
660 val->value.i = as->vlan;
661 return 0;
662 }
663
664
665 static void
666 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
667 {
668 struct mii_bus *mii = as->mii_bus;
669
670 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
671 return;
672
673 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
674 val &= AR7240_VTUDATA_MEMBER;
675 val |= AR7240_VTUDATA_VALID;
676 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
677 }
678 op |= AR7240_VTU_ACTIVE;
679 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
680 }
681
682 static int
683 ar7240_hw_apply(struct switch_dev *dev)
684 {
685 struct ar7240sw *as = sw_to_ar7240(dev);
686 u8 portmask[AR7240_NUM_PORTS];
687 int i, j;
688
689 /* flush all vlan translation unit entries */
690 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
691
692 memset(portmask, 0, sizeof(portmask));
693 if (as->vlan) {
694 /* calculate the port destination masks and load vlans
695 * into the vlan translation unit */
696 for (j = 0; j < AR7240_MAX_VLANS; j++) {
697 u8 vp = as->vlan_table[j];
698
699 if (!vp)
700 continue;
701
702 for (i = 0; i < AR7240_NUM_PORTS; i++) {
703 u8 mask = (1 << i);
704 if (vp & mask)
705 portmask[i] |= vp & ~mask;
706 }
707
708 ar7240_vtu_op(as,
709 AR7240_VTU_OP_LOAD |
710 (as->vlan_id[j] << AR7240_VTU_VID_S),
711 as->vlan_table[j]);
712 }
713 } else {
714 /* vlan disabled:
715 * isolate all ports, but connect them to the cpu port */
716 for (i = 0; i < AR7240_NUM_PORTS; i++) {
717 if (i == AR7240_PORT_CPU)
718 continue;
719
720 portmask[i] = 1 << AR7240_PORT_CPU;
721 portmask[AR7240_PORT_CPU] |= (1 << i);
722 }
723 }
724
725 /* update the port destination mask registers and tag settings */
726 for (i = 0; i < AR7240_NUM_PORTS; i++)
727 ar7240sw_setup_port(as, i, portmask[i]);
728
729 return 0;
730 }
731
732 static int
733 ar7240_reset_switch(struct switch_dev *dev)
734 {
735 struct ar7240sw *as = sw_to_ar7240(dev);
736 ar7240sw_reset(as);
737 return 0;
738 }
739
740 static struct switch_attr ar7240_globals[] = {
741 {
742 .type = SWITCH_TYPE_INT,
743 .name = "enable_vlan",
744 .description = "Enable VLAN mode",
745 .set = ar7240_set_vlan,
746 .get = ar7240_get_vlan,
747 .max = 1
748 },
749 };
750
751 static struct switch_attr ar7240_port[] = {
752 };
753
754 static struct switch_attr ar7240_vlan[] = {
755 {
756 .type = SWITCH_TYPE_INT,
757 .name = "vid",
758 .description = "VLAN ID",
759 .set = ar7240_set_vid,
760 .get = ar7240_get_vid,
761 .max = 4094,
762 },
763 };
764
765 static const struct switch_dev_ops ar7240_ops = {
766 .attr_global = {
767 .attr = ar7240_globals,
768 .n_attr = ARRAY_SIZE(ar7240_globals),
769 },
770 .attr_port = {
771 .attr = ar7240_port,
772 .n_attr = ARRAY_SIZE(ar7240_port),
773 },
774 .attr_vlan = {
775 .attr = ar7240_vlan,
776 .n_attr = ARRAY_SIZE(ar7240_vlan),
777 },
778 .get_port_pvid = ar7240_get_pvid,
779 .set_port_pvid = ar7240_set_pvid,
780 .get_vlan_ports = ar7240_get_ports,
781 .set_vlan_ports = ar7240_set_ports,
782 .apply_config = ar7240_hw_apply,
783 .reset_switch = ar7240_reset_switch,
784 };
785
786 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
787 {
788 struct mii_bus *mii = ag->mii_bus;
789 struct ar7240sw *as;
790 struct switch_dev *swdev;
791 u32 ctrl;
792 u16 phy_id1;
793 u16 phy_id2;
794 u8 ver;
795 int i;
796
797 as = kzalloc(sizeof(*as), GFP_KERNEL);
798 if (!as)
799 return NULL;
800
801 ar7240sw_init(as, mii);
802
803 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
804
805 ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M;
806 if (ver != 1) {
807 pr_err("%s: unsupported chip, ctrl=%08x\n",
808 ag->dev->name, ctrl);
809 return NULL;
810 }
811
812 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
813 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
814 if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) {
815 pr_err("%s: unknown phy id '%04x:%04x'\n",
816 ag->dev->name, phy_id1, phy_id2);
817 return NULL;
818 }
819
820 swdev = &as->swdev;
821 swdev->name = "AR7240 built-in switch";
822 swdev->ports = AR7240_NUM_PORTS;
823 swdev->cpu_port = AR7240_PORT_CPU;
824 swdev->vlans = AR7240_MAX_VLANS;
825 swdev->ops = &ar7240_ops;
826
827 if (register_switch(&as->swdev, ag->dev) < 0) {
828 kfree(as);
829 return NULL;
830 }
831
832 pr_info("%s: Found an AR7240 built-in switch\n", ag->dev->name);
833
834 /* initialize defaults */
835 for (i = 0; i < AR7240_MAX_VLANS; i++)
836 as->vlan_id[i] = i;
837
838 as->vlan_table[0] = AR7240_PORT_MASK_ALL;
839
840 return as;
841 }
842
843 static void link_function(struct work_struct *work) {
844 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
845 unsigned long flags;
846 int i;
847 int status = 0;
848
849 for (i = 0; i < 4; i++) {
850 int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
851 if(link & BMSR_LSTATUS) {
852 status = 1;
853 break;
854 }
855 }
856
857 spin_lock_irqsave(&ag->lock, flags);
858 if(status != ag->link) {
859 ag->link = status;
860 ag71xx_link_adjust(ag);
861 }
862 spin_unlock_irqrestore(&ag->lock, flags);
863
864 schedule_delayed_work(&ag->link_work, HZ / 2);
865 }
866
867 void ag71xx_ar7240_start(struct ag71xx *ag)
868 {
869 struct ar7240sw *as = ag->phy_priv;
870
871 ar7240sw_reset(as);
872
873 ag->speed = SPEED_1000;
874 ag->duplex = 1;
875
876 ar7240_set_addr(as, ag->dev->dev_addr);
877 ar7240_hw_apply(&as->swdev);
878
879 schedule_delayed_work(&ag->link_work, HZ / 10);
880 }
881
882 void ag71xx_ar7240_stop(struct ag71xx *ag)
883 {
884 cancel_delayed_work_sync(&ag->link_work);
885 }
886
887 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
888 {
889 struct ar7240sw *as;
890
891 as = ar7240_probe(ag);
892 if (!as)
893 return -ENODEV;
894
895 ag->phy_priv = as;
896 ar7240sw_reset(as);
897
898 INIT_DELAYED_WORK(&ag->link_work, link_function);
899
900 return 0;
901 }
902
903 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
904 {
905 struct ar7240sw *as = ag->phy_priv;
906
907 if (!as)
908 return;
909
910 unregister_switch(&as->swdev);
911 kfree(as);
912 ag->phy_priv = NULL;
913 }
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