01f9c03feed1e4c34f24757d2f73958c2f5be6e7
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 ( NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR )
25
26 static int ag71xx_debug = -1;
27
28 module_param(ag71xx_debug, int, 0);
29 MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40 ag->dev->name,
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49 ag->dev->name,
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86 kfree(ring->buf);
87
88 if (ring->descs)
89 dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
90 ring->descs, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
94 {
95 int err;
96
97 ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
98 &ring->descs_dma,
99 GFP_ATOMIC);
100 if (!ring->descs) {
101 err = -ENOMEM;
102 goto err;
103 }
104
105 ring->size = size;
106
107 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
108 if (!ring->buf) {
109 err = -ENOMEM;
110 goto err;
111 }
112
113 return 0;
114
115 err:
116 return err;
117 }
118
119 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
120 {
121 struct ag71xx_ring *ring = &ag->tx_ring;
122 struct net_device *dev = ag->dev;
123
124 while (ring->curr != ring->dirty) {
125 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
126
127 if (!ag71xx_desc_empty(&ring->descs[i])) {
128 ring->descs[i].ctrl = 0;
129 dev->stats.tx_errors++;
130 }
131
132 if (ring->buf[i].skb)
133 dev_kfree_skb_any(ring->buf[i].skb);
134
135 ring->buf[i].skb = NULL;
136
137 ring->dirty++;
138 }
139
140 /* flush descriptors */
141 wmb();
142
143 }
144
145 static void ag71xx_ring_tx_init(struct ag71xx *ag)
146 {
147 struct ag71xx_ring *ring = &ag->tx_ring;
148 int i;
149
150 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
151 ring->descs[i].next = (u32) (ring->descs_dma +
152 sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
153
154 ring->descs[i].ctrl = DESC_EMPTY;
155 ring->buf[i].skb = NULL;
156 }
157
158 /* flush descriptors */
159 wmb();
160
161 ring->curr = 0;
162 ring->dirty = 0;
163 }
164
165 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
166 {
167 struct ag71xx_ring *ring = &ag->rx_ring;
168 int i;
169
170 if (!ring->buf)
171 return;
172
173 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
174 if (ring->buf[i].skb)
175 kfree_skb(ring->buf[i].skb);
176
177 }
178
179 static int ag71xx_ring_rx_init(struct ag71xx *ag)
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 unsigned int i;
183 int ret;
184
185 ret = 0;
186 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
187 ring->descs[i].next = (u32) (ring->descs_dma +
188 sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
189
190 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
191 struct sk_buff *skb;
192
193 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
194 if (!skb) {
195 ret = -ENOMEM;
196 break;
197 }
198
199 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
200 DMA_FROM_DEVICE);
201
202 skb->dev = ag->dev;
203 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
204
205 ring->buf[i].skb = skb;
206 ring->descs[i].data = virt_to_phys(skb->data);
207 ring->descs[i].ctrl = DESC_EMPTY;
208 }
209
210 /* flush descriptors */
211 wmb();
212
213 ring->curr = 0;
214 ring->dirty = 0;
215
216 return ret;
217 }
218
219 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
220 {
221 struct ag71xx_ring *ring = &ag->rx_ring;
222 unsigned int count;
223
224 count = 0;
225 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
226 unsigned int i;
227
228 i = ring->dirty % AG71XX_RX_RING_SIZE;
229
230 if (ring->buf[i].skb == NULL) {
231 struct sk_buff *skb;
232
233 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
234 if (skb == NULL)
235 break;
236
237 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
238 DMA_FROM_DEVICE);
239
240 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
241 skb->dev = ag->dev;
242
243 ring->buf[i].skb = skb;
244 ring->descs[i].data = virt_to_phys(skb->data);
245 }
246
247 ring->descs[i].ctrl = DESC_EMPTY;
248 count++;
249 }
250
251 /* flush descriptors */
252 wmb();
253
254 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
255
256 return count;
257 }
258
259 static int ag71xx_rings_init(struct ag71xx *ag)
260 {
261 int ret;
262
263 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
264 if (ret)
265 return ret;
266
267 ag71xx_ring_tx_init(ag);
268
269 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
270 if (ret)
271 return ret;
272
273 ret = ag71xx_ring_rx_init(ag);
274 return ret;
275 }
276
277 static void ag71xx_rings_cleanup(struct ag71xx *ag)
278 {
279 ag71xx_ring_rx_clean(ag);
280 ag71xx_ring_free(&ag->rx_ring);
281
282 ag71xx_ring_tx_clean(ag);
283 ag71xx_ring_free(&ag->tx_ring);
284 }
285
286 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
287 {
288 u32 t;
289
290 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
291 | (((u32) mac[2]) << 8) | ((u32) mac[3]);
292
293 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
294
295 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
296 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
297 }
298
299 #define AR71XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
300 MAC_CFG1_SRX | MAC_CFG1_STX)
301 #define AR71XX_FIFO_CFG5_INIT 0x0007ffef
302
303 #define AR91XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
304 MAC_CFG1_SRX | MAC_CFG1_STX | \
305 MAC_CFG1_TFC | MAC_CFG1_RFC)
306 #define AR91XX_FIFO_CFG5_INIT 0x0007efef
307
308 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
309
310 static void ag71xx_dma_reset(struct ag71xx *ag)
311 {
312 int i;
313
314 ag71xx_dump_dma_regs(ag);
315
316 /* stop RX and TX */
317 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
318 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
319
320 /* clear descriptor addresses */
321 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
322 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
323
324 /* clear pending RX/TX interrupts */
325 for (i = 0; i < 256; i++) {
326 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
327 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
328 }
329
330 /* clear pending errors */
331 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
332 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
333
334 if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
335 printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
336 ag->dev->name);
337
338 if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
339 printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
340 ag->dev->name);
341
342 ag71xx_dump_dma_regs(ag);
343 }
344
345 static void ag71xx_hw_init(struct ag71xx *ag)
346 {
347 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
348
349 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
350 udelay(20);
351
352 ar71xx_device_stop(pdata->reset_bit);
353 mdelay(100);
354 ar71xx_device_start(pdata->reset_bit);
355 mdelay(100);
356
357 /* setup MAC configuration registers */
358 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
359 pdata->is_ar91xx ? AR91XX_MAC_CFG1_INIT : AR71XX_MAC_CFG1_INIT);
360 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
361 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
362
363 /* setup max frame length */
364 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
365
366 /* setup MII interface type */
367 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
368
369 /* setup FIFO configuration registers */
370 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
371 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
372 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
373 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
374 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5,
375 pdata->is_ar91xx ? AR91XX_FIFO_CFG5_INIT
376 : AR71XX_FIFO_CFG5_INIT);
377
378 ag71xx_dma_reset(ag);
379 }
380
381 static void ag71xx_hw_start(struct ag71xx *ag)
382 {
383 /* start RX engine */
384 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
385
386 /* enable interrupts */
387 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
388 }
389
390 static void ag71xx_hw_stop(struct ag71xx *ag)
391 {
392 /* disable all interrupts */
393 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
394
395 ag71xx_dma_reset(ag);
396 }
397
398 static int ag71xx_open(struct net_device *dev)
399 {
400 struct ag71xx *ag = netdev_priv(dev);
401 int ret;
402
403 ret = ag71xx_rings_init(ag);
404 if (ret)
405 goto err;
406
407 napi_enable(&ag->napi);
408
409 netif_carrier_off(dev);
410 ag71xx_phy_start(ag);
411
412 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
413 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
414
415 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
416
417 ag71xx_hw_start(ag);
418
419 netif_start_queue(dev);
420
421 return 0;
422
423 err:
424 ag71xx_rings_cleanup(ag);
425 return ret;
426 }
427
428 static int ag71xx_stop(struct net_device *dev)
429 {
430 struct ag71xx *ag = netdev_priv(dev);
431 unsigned long flags;
432
433 spin_lock_irqsave(&ag->lock, flags);
434
435 netif_stop_queue(dev);
436
437 ag71xx_hw_stop(ag);
438
439 netif_carrier_off(dev);
440 ag71xx_phy_stop(ag);
441
442 napi_disable(&ag->napi);
443 del_timer_sync(&ag->oom_timer);
444
445 spin_unlock_irqrestore(&ag->lock, flags);
446
447 ag71xx_rings_cleanup(ag);
448
449 return 0;
450 }
451
452 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
453 {
454 struct ag71xx *ag = netdev_priv(dev);
455 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
456 struct ag71xx_ring *ring = &ag->tx_ring;
457 struct ag71xx_desc *desc;
458 unsigned long flags;
459 int i;
460
461 i = ring->curr % AG71XX_TX_RING_SIZE;
462 desc = &ring->descs[i];
463
464 spin_lock_irqsave(&ag->lock, flags);
465 pdata->ddr_flush();
466 spin_unlock_irqrestore(&ag->lock, flags);
467
468 if (!ag71xx_desc_empty(desc))
469 goto err_drop;
470
471 if (skb->len <= 0) {
472 DBG("%s: packet len is too small\n", ag->dev->name);
473 goto err_drop;
474 }
475
476 dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
477
478 ring->buf[i].skb = skb;
479
480 /* setup descriptor fields */
481 desc->data = virt_to_phys(skb->data);
482 desc->ctrl = (skb->len & DESC_PKTLEN_M);
483
484 /* flush descriptor */
485 wmb();
486
487 ring->curr++;
488 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
489 DBG("%s: tx queue full\n", ag->dev->name);
490 netif_stop_queue(dev);
491 }
492
493 DBG("%s: packet injected into TX queue\n", ag->dev->name);
494
495 /* enable TX engine */
496 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
497
498 dev->trans_start = jiffies;
499
500 return 0;
501
502 err_drop:
503 dev->stats.tx_dropped++;
504
505 dev_kfree_skb(skb);
506 return 0;
507 }
508
509 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
510 {
511 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
512 struct ag71xx *ag = netdev_priv(dev);
513 int ret;
514
515 switch (cmd) {
516 case SIOCETHTOOL:
517 if (ag->phy_dev == NULL)
518 break;
519
520 spin_lock_irq(&ag->lock);
521 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
522 spin_unlock_irq(&ag->lock);
523 return ret;
524
525 case SIOCSIFHWADDR:
526 if (copy_from_user
527 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
528 return -EFAULT;
529 return 0;
530
531 case SIOCGIFHWADDR:
532 if (copy_to_user
533 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
534 return -EFAULT;
535 return 0;
536
537 case SIOCGMIIPHY:
538 case SIOCGMIIREG:
539 case SIOCSMIIREG:
540 if (ag->phy_dev == NULL)
541 break;
542
543 return phy_mii_ioctl(ag->phy_dev, data, cmd);
544
545 default:
546 break;
547 }
548
549 return -EOPNOTSUPP;
550 }
551
552 static void ag71xx_oom_timer_handler(unsigned long data)
553 {
554 struct net_device *dev = (struct net_device *) data;
555 struct ag71xx *ag = netdev_priv(dev);
556
557 netif_rx_schedule(dev, &ag->napi);
558 }
559
560 static void ag71xx_tx_timeout(struct net_device *dev)
561 {
562 struct ag71xx *ag = netdev_priv(dev);
563
564 if (netif_msg_tx_err(ag))
565 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
566
567 schedule_work(&ag->restart_work);
568 }
569
570 static void ag71xx_restart_work_func(struct work_struct *work)
571 {
572 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
573
574 ag71xx_stop(ag->dev);
575 ag71xx_open(ag->dev);
576 }
577
578 static void ag71xx_tx_packets(struct ag71xx *ag)
579 {
580 struct ag71xx_ring *ring = &ag->tx_ring;
581 unsigned int sent;
582
583 DBG("%s: processing TX ring\n", ag->dev->name);
584
585 sent = 0;
586 while (ring->dirty != ring->curr) {
587 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
588 struct ag71xx_desc *desc = &ring->descs[i];
589 struct sk_buff *skb = ring->buf[i].skb;
590
591 if (!ag71xx_desc_empty(desc))
592 break;
593
594 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
595
596 ag->dev->stats.tx_bytes += skb->len;
597 ag->dev->stats.tx_packets++;
598
599 dev_kfree_skb_any(skb);
600 ring->buf[i].skb = NULL;
601
602 ring->dirty++;
603 sent++;
604 }
605
606 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
607
608 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
609 netif_wake_queue(ag->dev);
610
611 }
612
613 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
614 {
615 struct net_device *dev = ag->dev;
616 struct ag71xx_ring *ring = &ag->rx_ring;
617 int done = 0;
618
619 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
620 dev->name, limit, ring->curr, ring->dirty);
621
622 while (done < limit) {
623 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
624 struct ag71xx_desc *desc = &ring->descs[i];
625 struct sk_buff *skb;
626 int pktlen;
627
628 if (ag71xx_desc_empty(desc))
629 break;
630
631 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
632 ag71xx_assert(0);
633 break;
634 }
635
636 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
637
638 skb = ring->buf[i].skb;
639 pktlen = ag71xx_desc_pktlen(desc);
640 pktlen -= ETH_FCS_LEN;
641
642 skb_put(skb, pktlen);
643
644 skb->dev = dev;
645 skb->protocol = eth_type_trans(skb, dev);
646 skb->ip_summed = CHECKSUM_NONE;
647
648 netif_receive_skb(skb);
649
650 dev->last_rx = jiffies;
651 dev->stats.rx_packets++;
652 dev->stats.rx_bytes += pktlen;
653
654 ring->buf[i].skb = NULL;
655 done++;
656
657 ring->curr++;
658 }
659
660 ag71xx_ring_rx_refill(ag);
661
662 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
663 dev->name, ring->curr, ring->dirty, done);
664
665 return done;
666 }
667
668 static int ag71xx_poll(struct napi_struct *napi, int limit)
669 {
670 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
671 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
672 struct net_device *dev = ag->dev;
673 struct ag71xx_ring *rx_ring;
674 unsigned long flags;
675 u32 status;
676 int done;
677
678 pdata->ddr_flush();
679 ag71xx_tx_packets(ag);
680
681 DBG("%s: processing RX ring\n", dev->name);
682 done = ag71xx_rx_packets(ag, limit);
683
684 rx_ring = &ag->rx_ring;
685 if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
686 goto oom;
687
688 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
689 if (unlikely(status & RX_STATUS_OF)) {
690 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
691 dev->stats.rx_fifo_errors++;
692
693 /* restart RX */
694 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
695 }
696
697 if (done < limit) {
698 if (status & RX_STATUS_PR)
699 goto more;
700
701 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
702 if (status & TX_STATUS_PS)
703 goto more;
704
705 DBG("%s: disable polling mode, done=%d, limit=%d\n",
706 dev->name, done, limit);
707
708 netif_rx_complete(dev, napi);
709
710 /* enable interrupts */
711 spin_lock_irqsave(&ag->lock, flags);
712 ag71xx_int_enable(ag, AG71XX_INT_POLL);
713 spin_unlock_irqrestore(&ag->lock, flags);
714 return 0;
715 }
716
717 more:
718 DBG("%s: stay in polling mode, done=%d, limit=%d\n",
719 dev->name, done, limit);
720 return 1;
721
722 oom:
723 if (netif_msg_rx_err(ag))
724 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
725
726 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
727 netif_rx_complete(dev, napi);
728 return 0;
729 }
730
731 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
732 {
733 struct net_device *dev = dev_id;
734 struct ag71xx *ag = netdev_priv(dev);
735 u32 status;
736
737 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
738 ag71xx_dump_intr(ag, "raw", status);
739
740 if (unlikely(!status))
741 return IRQ_NONE;
742
743 if (unlikely(status & AG71XX_INT_ERR)) {
744 if (status & AG71XX_INT_TX_BE) {
745 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
746 dev_err(&dev->dev, "TX BUS error\n");
747 }
748 if (status & AG71XX_INT_RX_BE) {
749 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
750 dev_err(&dev->dev, "RX BUS error\n");
751 }
752 }
753
754 if (likely(status & AG71XX_INT_POLL)) {
755 ag71xx_int_disable(ag, AG71XX_INT_POLL);
756 DBG("%s: enable polling mode\n", dev->name);
757 netif_rx_schedule(dev, &ag->napi);
758 }
759
760 return IRQ_HANDLED;
761 }
762
763 static void ag71xx_set_multicast_list(struct net_device *dev)
764 {
765 /* TODO */
766 }
767
768 static int __init ag71xx_probe(struct platform_device *pdev)
769 {
770 struct net_device *dev;
771 struct resource *res;
772 struct ag71xx *ag;
773 struct ag71xx_platform_data *pdata;
774 int err;
775
776 pdata = pdev->dev.platform_data;
777 if (!pdata) {
778 dev_err(&pdev->dev, "no platform data specified\n");
779 err = -ENXIO;
780 goto err_out;
781 }
782
783 dev = alloc_etherdev(sizeof(*ag));
784 if (!dev) {
785 dev_err(&pdev->dev, "alloc_etherdev failed\n");
786 err = -ENOMEM;
787 goto err_out;
788 }
789
790 SET_NETDEV_DEV(dev, &pdev->dev);
791
792 ag = netdev_priv(dev);
793 ag->pdev = pdev;
794 ag->dev = dev;
795 ag->mii_bus = &ag71xx_mdio_bus->mii_bus;
796 ag->msg_enable = netif_msg_init(ag71xx_debug,
797 AG71XX_DEFAULT_MSG_ENABLE);
798 spin_lock_init(&ag->lock);
799
800 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
801 if (!res) {
802 dev_err(&pdev->dev, "no mac_base resource found\n");
803 err = -ENXIO;
804 goto err_out;
805 }
806
807 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
808 if (!ag->mac_base) {
809 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
810 err = -ENOMEM;
811 goto err_free_dev;
812 }
813
814 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
815 if (!res) {
816 dev_err(&pdev->dev, "no mac_base2 resource found\n");
817 err = -ENXIO;
818 goto err_unmap_base1;
819 }
820
821 ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
822 if (!ag->mac_base) {
823 dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
824 err = -ENOMEM;
825 goto err_unmap_base1;
826 }
827
828 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
829 if (!res) {
830 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
831 err = -ENXIO;
832 goto err_unmap_base2;
833 }
834
835 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
836 if (!ag->mii_ctrl) {
837 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
838 err = -ENOMEM;
839 goto err_unmap_base2;
840 }
841
842 dev->irq = platform_get_irq(pdev, 0);
843 err = request_irq(dev->irq, ag71xx_interrupt,
844 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
845 dev->name, dev);
846 if (err) {
847 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
848 goto err_unmap_mii_ctrl;
849 }
850
851 dev->base_addr = (unsigned long)ag->mac_base;
852 dev->open = ag71xx_open;
853 dev->stop = ag71xx_stop;
854 dev->hard_start_xmit = ag71xx_hard_start_xmit;
855 dev->set_multicast_list = ag71xx_set_multicast_list;
856 dev->do_ioctl = ag71xx_do_ioctl;
857 dev->ethtool_ops = &ag71xx_ethtool_ops;
858
859 dev->tx_timeout = ag71xx_tx_timeout;
860 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
861
862 init_timer(&ag->oom_timer);
863 ag->oom_timer.data = (unsigned long) dev;
864 ag->oom_timer.function = ag71xx_oom_timer_handler;
865
866 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
867
868 if (is_valid_ether_addr(pdata->mac_addr))
869 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
870 else {
871 dev->dev_addr[0] = 0xde;
872 dev->dev_addr[1] = 0xad;
873 get_random_bytes(&dev->dev_addr[2], 3);
874 dev->dev_addr[5] = pdev->id & 0xff;
875 }
876
877 err = register_netdev(dev);
878 if (err) {
879 dev_err(&pdev->dev, "unable to register net device\n");
880 goto err_free_irq;
881 }
882
883 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
884 dev->name, dev->base_addr, dev->irq);
885
886 ag71xx_dump_regs(ag);
887
888 ag71xx_hw_init(ag);
889
890 ag71xx_dump_regs(ag);
891
892 /* Reset the mdio bus explicitly */
893 if (ag->mii_bus) {
894 mutex_lock(&ag->mii_bus->mdio_lock);
895 ag->mii_bus->reset(ag->mii_bus);
896 mutex_unlock(&ag->mii_bus->mdio_lock);
897 }
898
899 err = ag71xx_phy_connect(ag);
900 if (err)
901 goto err_unregister_netdev;
902
903 platform_set_drvdata(pdev, dev);
904
905 return 0;
906
907 err_unregister_netdev:
908 unregister_netdev(dev);
909 err_free_irq:
910 free_irq(dev->irq, dev);
911 err_unmap_mii_ctrl:
912 iounmap(ag->mii_ctrl);
913 err_unmap_base2:
914 iounmap(ag->mac_base2);
915 err_unmap_base1:
916 iounmap(ag->mac_base);
917 err_free_dev:
918 kfree(dev);
919 err_out:
920 platform_set_drvdata(pdev, NULL);
921 return err;
922 }
923
924 static int __exit ag71xx_remove(struct platform_device *pdev)
925 {
926 struct net_device *dev = platform_get_drvdata(pdev);
927
928 if (dev) {
929 struct ag71xx *ag = netdev_priv(dev);
930
931 ag71xx_phy_disconnect(ag);
932 unregister_netdev(dev);
933 free_irq(dev->irq, dev);
934 iounmap(ag->mii_ctrl);
935 iounmap(ag->mac_base2);
936 iounmap(ag->mac_base);
937 kfree(dev);
938 platform_set_drvdata(pdev, NULL);
939 }
940
941 return 0;
942 }
943
944 static struct platform_driver ag71xx_driver = {
945 .probe = ag71xx_probe,
946 .remove = __exit_p(ag71xx_remove),
947 .driver = {
948 .name = AG71XX_DRV_NAME,
949 }
950 };
951
952 static int __init ag71xx_module_init(void)
953 {
954 int ret;
955
956 ret = ag71xx_mdio_driver_init();
957 if (ret)
958 goto err_out;
959
960 ret = platform_driver_register(&ag71xx_driver);
961 if (ret)
962 goto err_mdio_exit;
963
964 return 0;
965
966 err_mdio_exit:
967 ag71xx_mdio_driver_exit();
968 err_out:
969 return ret;
970 }
971
972 static void __exit ag71xx_module_exit(void)
973 {
974 platform_driver_unregister(&ag71xx_driver);
975 ag71xx_mdio_driver_exit();
976 }
977
978 module_init(ag71xx_module_init);
979 module_exit(ag71xx_module_exit);
980
981 MODULE_VERSION(AG71XX_DRV_VERSION);
982 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
983 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
984 MODULE_LICENSE("GPL v2");
985 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);