[ar71xx] cosmetic changes in the ag71xx driver
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 ( NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR )
25
26 static int ag71xx_debug = -1;
27
28 module_param(ag71xx_debug, int, 0);
29 MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_regs(struct ag71xx *ag)
32 {
33 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
36 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
37 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
38 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
39 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
40 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
41 ag->dev->name,
42 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
43 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
44 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
45 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
46 ag->dev->name,
47 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
48 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
49 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
50 DBG("%s: fifo_cfg3=%08x, fifo_cfg3=%08x, fifo_cfg5=%08x\n",
51 ag->dev->name,
52 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
53 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
54 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
55 }
56
57 static void ag71xx_ring_free(struct ag71xx_ring *ring)
58 {
59 kfree(ring->buf);
60
61 if (ring->descs)
62 dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
63 ring->descs, ring->descs_dma);
64 }
65
66 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
67 {
68 int err;
69
70 ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
71 &ring->descs_dma,
72 GFP_ATOMIC);
73 if (!ring->descs) {
74 err = -ENOMEM;
75 goto err;
76 }
77
78 ring->size = size;
79
80 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
81 if (!ring->buf) {
82 err = -ENOMEM;
83 goto err;
84 }
85
86 return 0;
87
88 err:
89 return err;
90 }
91
92 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
93 {
94 struct ag71xx_ring *ring = &ag->tx_ring;
95 struct net_device *dev = ag->dev;
96
97 while (ring->curr != ring->dirty) {
98 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
99
100 if (!ag71xx_desc_empty(&ring->descs[i])) {
101 ring->descs[i].ctrl = 0;
102 dev->stats.tx_errors++;
103 }
104
105 if (ring->buf[i].skb)
106 dev_kfree_skb_any(ring->buf[i].skb);
107
108 ring->buf[i].skb = NULL;
109
110 ring->dirty++;
111 }
112
113 /* flush descriptors */
114 wmb();
115
116 }
117
118 static void ag71xx_ring_tx_init(struct ag71xx *ag)
119 {
120 struct ag71xx_ring *ring = &ag->tx_ring;
121 int i;
122
123 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
124 ring->descs[i].next = (u32) (ring->descs_dma +
125 sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
126
127 ring->descs[i].ctrl = DESC_EMPTY;
128 ring->buf[i].skb = NULL;
129 }
130
131 /* flush descriptors */
132 wmb();
133
134 ring->curr = 0;
135 ring->dirty = 0;
136 }
137
138 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
139 {
140 struct ag71xx_ring *ring = &ag->rx_ring;
141 int i;
142
143 if (!ring->buf)
144 return;
145
146 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
147 if (ring->buf[i].skb)
148 kfree_skb(ring->buf[i].skb);
149
150 }
151
152 static int ag71xx_ring_rx_init(struct ag71xx *ag)
153 {
154 struct ag71xx_ring *ring = &ag->rx_ring;
155 unsigned int i;
156 int ret;
157
158 ret = 0;
159 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
160 ring->descs[i].next = (u32) (ring->descs_dma +
161 sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
162
163 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
164 struct sk_buff *skb;
165
166 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
167 if (!skb) {
168 ret = -ENOMEM;
169 break;
170 }
171
172 skb->dev = ag->dev;
173 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
174
175 ring->buf[i].skb = skb;
176 ring->descs[i].data = virt_to_phys(skb->data);
177 ring->descs[i].ctrl = DESC_EMPTY;
178 }
179
180 /* flush descriptors */
181 wmb();
182
183 ring->curr = 0;
184 ring->dirty = 0;
185
186 return ret;
187 }
188
189 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
190 {
191 struct ag71xx_ring *ring = &ag->rx_ring;
192 unsigned int count;
193
194 count = 0;
195 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
196 unsigned int i;
197
198 i = ring->dirty % AG71XX_RX_RING_SIZE;
199
200 if (ring->buf[i].skb == NULL) {
201 struct sk_buff *skb;
202
203 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
204 if (skb == NULL) {
205 printk(KERN_ERR "%s: no memory for skb\n",
206 ag->dev->name);
207 break;
208 }
209
210 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
211 skb->dev = ag->dev;
212 ring->buf[i].skb = skb;
213 ring->descs[i].data = virt_to_phys(skb->data);
214 }
215
216 ring->descs[i].ctrl = DESC_EMPTY;
217 count++;
218 }
219
220 /* flush descriptors */
221 wmb();
222
223 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
224
225 return count;
226 }
227
228 static int ag71xx_rings_init(struct ag71xx *ag)
229 {
230 int ret;
231
232 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
233 if (ret)
234 return ret;
235
236 ag71xx_ring_tx_init(ag);
237
238 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
239 if (ret)
240 return ret;
241
242 ret = ag71xx_ring_rx_init(ag);
243 return ret;
244 }
245
246 static void ag71xx_rings_cleanup(struct ag71xx *ag)
247 {
248 ag71xx_ring_rx_clean(ag);
249 ag71xx_ring_free(&ag->rx_ring);
250
251 ag71xx_ring_tx_clean(ag);
252 ag71xx_ring_free(&ag->tx_ring);
253 }
254
255 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
256 {
257 u32 t;
258
259 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
260 | (((u32) mac[2]) << 8) | ((u32) mac[2]);
261
262 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
263
264 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
265 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
266 }
267
268 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | MAC_CFG1_SRX \
269 | MAC_CFG1_STX)
270
271 static void ag71xx_hw_init(struct ag71xx *ag)
272 {
273 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
274
275 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
276 udelay(20);
277
278 ar71xx_device_stop(pdata->reset_bit);
279 mdelay(100);
280 ar71xx_device_start(pdata->reset_bit);
281 mdelay(100);
282
283 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
284
285 /* TODO: set max packet size */
286
287 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
288 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
289
290 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, 0x00001f00);
291
292 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
293
294 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
295 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
296 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
297 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, 0x0007ffef);
298 }
299
300 static void ag71xx_hw_start(struct ag71xx *ag)
301 {
302 /* start RX engine */
303 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
304
305 /* enable interrupts */
306 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
307 }
308
309 static void ag71xx_hw_stop(struct ag71xx *ag)
310 {
311 /* stop RX and TX */
312 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
313 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
314
315 /* disable all interrupts */
316 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
317 }
318
319 static int ag71xx_open(struct net_device *dev)
320 {
321 struct ag71xx *ag = netdev_priv(dev);
322 int ret;
323
324 ret = ag71xx_rings_init(ag);
325 if (ret)
326 goto err;
327
328 napi_enable(&ag->napi);
329
330 netif_carrier_off(dev);
331 ag71xx_phy_start(ag);
332
333 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
334 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
335
336 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
337
338 ag71xx_hw_start(ag);
339
340 netif_start_queue(dev);
341
342 return 0;
343
344 err:
345 ag71xx_rings_cleanup(ag);
346 return ret;
347 }
348
349 static int ag71xx_stop(struct net_device *dev)
350 {
351 struct ag71xx *ag = netdev_priv(dev);
352 unsigned long flags;
353
354 spin_lock_irqsave(&ag->lock, flags);
355
356 netif_stop_queue(dev);
357
358 ag71xx_hw_stop(ag);
359
360 netif_carrier_off(dev);
361 ag71xx_phy_stop(ag);
362
363 napi_disable(&ag->napi);
364
365 spin_unlock_irqrestore(&ag->lock, flags);
366
367 ag71xx_rings_cleanup(ag);
368
369 return 0;
370 }
371
372 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
373 {
374 struct ag71xx *ag = netdev_priv(dev);
375 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
376 struct ag71xx_ring *ring = &ag->tx_ring;
377 struct ag71xx_desc *desc;
378 unsigned long flags;
379 int i;
380
381 i = ring->curr % AG71XX_TX_RING_SIZE;
382 desc = &ring->descs[i];
383
384 spin_lock_irqsave(&ag->lock, flags);
385 ar71xx_ddr_flush(pdata->flush_reg);
386 spin_unlock_irqrestore(&ag->lock, flags);
387
388 if (!ag71xx_desc_empty(desc))
389 goto err_drop;
390
391 if (skb->len <= 0) {
392 DBG("%s: packet len is too small\n", ag->dev->name);
393 goto err_drop;
394 }
395
396 dma_cache_wback_inv((unsigned long)skb->data, skb->len);
397
398 ring->buf[i].skb = skb;
399
400 /* setup descriptor fields */
401 desc->data = virt_to_phys(skb->data);
402 desc->ctrl = (skb->len & DESC_PKTLEN_M);
403
404 /* flush descriptor */
405 wmb();
406
407 ring->curr++;
408 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
409 DBG("%s: tx queue full\n", ag->dev->name);
410 netif_stop_queue(dev);
411 }
412
413 DBG("%s: packet injected into TX queue\n", ag->dev->name);
414
415 /* enable TX engine */
416 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
417
418 dev->trans_start = jiffies;
419
420 return 0;
421
422 err_drop:
423 dev->stats.tx_dropped++;
424
425 dev_kfree_skb(skb);
426 return 0;
427 }
428
429 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
430 {
431 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
432 struct ag71xx *ag = netdev_priv(dev);
433 int ret;
434
435 switch (cmd) {
436 case SIOCETHTOOL:
437 if (ag->phy_dev == NULL)
438 break;
439
440 spin_lock_irq(&ag->lock);
441 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
442 spin_unlock_irq(&ag->lock);
443 return ret;
444
445 case SIOCSIFHWADDR:
446 if (copy_from_user
447 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
448 return -EFAULT;
449 return 0;
450
451 case SIOCGIFHWADDR:
452 if (copy_to_user
453 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
454 return -EFAULT;
455 return 0;
456
457 case SIOCGMIIPHY:
458 case SIOCGMIIREG:
459 case SIOCSMIIREG:
460 if (ag->phy_dev == NULL)
461 break;
462
463 return phy_mii_ioctl(ag->phy_dev, data, cmd);
464
465 default:
466 break;
467 }
468
469 return -EOPNOTSUPP;
470 }
471
472 static void ag71xx_tx_packets(struct ag71xx *ag)
473 {
474 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
475 struct ag71xx_ring *ring = &ag->tx_ring;
476 unsigned int sent;
477
478 DBG("%s: processing TX ring\n", ag->dev->name);
479
480 #ifdef AG71XX_NAPI_TX
481 ar71xx_ddr_flush(pdata->flush_reg);
482 #endif
483
484 sent = 0;
485 while (ring->dirty != ring->curr) {
486 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
487 struct ag71xx_desc *desc = &ring->descs[i];
488 struct sk_buff *skb = ring->buf[i].skb;
489
490 if (!ag71xx_desc_empty(desc))
491 break;
492
493 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
494
495 ag->dev->stats.tx_bytes += skb->len;
496 ag->dev->stats.tx_packets++;
497
498 dev_kfree_skb_any(skb);
499 ring->buf[i].skb = NULL;
500
501 ring->dirty++;
502 sent++;
503 }
504
505 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
506
507 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
508 netif_wake_queue(ag->dev);
509
510 }
511
512 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
513 {
514 struct net_device *dev = ag->dev;
515 struct ag71xx_ring *ring = &ag->rx_ring;
516 #ifndef AG71XX_NAPI_TX
517 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
518 unsigned long flags;
519 #endif
520 int done = 0;
521
522 #ifndef AG71XX_NAPI_TX
523 spin_lock_irqsave(&ag->lock, flags);
524 ar71xx_ddr_flush(pdata->flush_reg);
525 spin_unlock_irqrestore(&ag->lock, flags);
526 #endif
527
528 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
529 dev->name, limit, ring->curr, ring->dirty);
530
531 while (done < limit) {
532 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
533 struct ag71xx_desc *desc = &ring->descs[i];
534 struct sk_buff *skb;
535 int pktlen;
536
537 if (ag71xx_desc_empty(desc))
538 break;
539
540 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
541 ag71xx_assert(0);
542 break;
543 }
544
545 skb = ring->buf[i].skb;
546 pktlen = ag71xx_desc_pktlen(desc);
547 pktlen -= ETH_FCS_LEN;
548
549 /* TODO: move it into the refill function */
550 dma_cache_wback_inv((unsigned long)skb->data, pktlen);
551 skb_put(skb, pktlen);
552
553 skb->dev = dev;
554 skb->protocol = eth_type_trans(skb, dev);
555 skb->ip_summed = CHECKSUM_UNNECESSARY;
556
557 netif_receive_skb(skb);
558
559 dev->last_rx = jiffies;
560 dev->stats.rx_packets++;
561 dev->stats.rx_bytes += pktlen;
562
563 ring->buf[i].skb = NULL;
564 done++;
565
566 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
567
568 ring->curr++;
569 if ((ring->curr - ring->dirty) > (AG71XX_RX_RING_SIZE / 4))
570 ag71xx_ring_rx_refill(ag);
571 }
572
573 ag71xx_ring_rx_refill(ag);
574
575 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
576 dev->name, ring->curr, ring->dirty, done);
577
578 return done;
579 }
580
581 static int ag71xx_poll(struct napi_struct *napi, int limit)
582 {
583 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
584 #ifdef AG71XX_NAPI_TX
585 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
586 #endif
587 struct net_device *dev = ag->dev;
588 unsigned long flags;
589 u32 status;
590 int done;
591
592 #ifdef AG71XX_NAPI_TX
593 ar71xx_ddr_flush(pdata->flush_reg);
594 ag71xx_tx_packets(ag);
595 #endif
596
597 DBG("%s: processing RX ring\n", dev->name);
598 done = ag71xx_rx_packets(ag, limit);
599
600 /* TODO: add OOM handler */
601
602 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
603 status &= AG71XX_INT_POLL;
604
605 if ((done < limit) && (!status)) {
606 DBG("%s: disable polling mode, done=%d, status=%x\n",
607 dev->name, done, status);
608
609 netif_rx_complete(dev, napi);
610
611 /* enable interrupts */
612 spin_lock_irqsave(&ag->lock, flags);
613 ag71xx_int_enable(ag, AG71XX_INT_POLL);
614 spin_unlock_irqrestore(&ag->lock, flags);
615 return 0;
616 }
617
618 if (status & AG71XX_INT_RX_OF) {
619 if (netif_msg_rx_err(ag))
620 printk(KERN_ALERT "%s: rx owerflow, restarting dma\n",
621 dev->name);
622
623 /* ack interrupt */
624 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
625 /* restart RX */
626 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
627 }
628
629 DBG("%s: stay in polling mode, done=%d, status=%x\n",
630 dev->name, done, status);
631 return 1;
632 }
633
634 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
635 {
636 struct net_device *dev = dev_id;
637 struct ag71xx *ag = netdev_priv(dev);
638 u32 status;
639
640 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
641 status &= ag71xx_rr(ag, AG71XX_REG_INT_ENABLE);
642
643 if (unlikely(!status))
644 return IRQ_NONE;
645
646 if (unlikely(status & AG71XX_INT_ERR)) {
647 if (status & AG71XX_INT_TX_BE) {
648 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
649 dev_err(&dev->dev, "TX BUS error\n");
650 }
651 if (status & AG71XX_INT_RX_BE) {
652 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
653 dev_err(&dev->dev, "RX BUS error\n");
654 }
655 }
656
657 #if 0
658 if (unlikely(status & AG71XX_INT_TX_UR)) {
659 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_UR);
660 DBG("%s: TX underrun\n", dev->name);
661 }
662 #endif
663
664 #ifndef AG71XX_NAPI_TX
665 if (likely(status & AG71XX_INT_TX_PS))
666 ag71xx_tx_packets(ag);
667 #endif
668
669 if (likely(status & AG71XX_INT_POLL)) {
670 ag71xx_int_disable(ag, AG71XX_INT_POLL);
671 DBG("%s: enable polling mode\n", dev->name);
672 netif_rx_schedule(dev, &ag->napi);
673 }
674
675 return IRQ_HANDLED;
676 }
677
678 static void ag71xx_set_multicast_list(struct net_device *dev)
679 {
680 /* TODO */
681 }
682
683 static int __init ag71xx_probe(struct platform_device *pdev)
684 {
685 struct net_device *dev;
686 struct resource *res;
687 struct ag71xx *ag;
688 struct ag71xx_platform_data *pdata;
689 int err;
690
691 pdata = pdev->dev.platform_data;
692 if (!pdata) {
693 dev_err(&pdev->dev, "no platform data specified\n");
694 err = -ENXIO;
695 goto err_out;
696 }
697
698 dev = alloc_etherdev(sizeof(*ag));
699 if (!dev) {
700 dev_err(&pdev->dev, "alloc_etherdev failed\n");
701 err = -ENOMEM;
702 goto err_out;
703 }
704
705 SET_NETDEV_DEV(dev, &pdev->dev);
706
707 ag = netdev_priv(dev);
708 ag->pdev = pdev;
709 ag->dev = dev;
710 ag->mii_bus = &ag71xx_mdio_bus->mii_bus;
711 ag->msg_enable = netif_msg_init(ag71xx_debug,
712 AG71XX_DEFAULT_MSG_ENABLE);
713 spin_lock_init(&ag->lock);
714
715 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
716 if (!res) {
717 dev_err(&pdev->dev, "no mac_base resource found\n");
718 err = -ENXIO;
719 goto err_out;
720 }
721
722 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
723 if (!ag->mac_base) {
724 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
725 err = -ENOMEM;
726 goto err_free_dev;
727 }
728
729 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
730 if (!res) {
731 dev_err(&pdev->dev, "no mac_base2 resource found\n");
732 err = -ENXIO;
733 goto err_unmap_base1;
734 }
735
736 ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
737 if (!ag->mac_base) {
738 dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
739 err = -ENOMEM;
740 goto err_unmap_base1;
741 }
742
743 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
744 if (!res) {
745 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
746 err = -ENXIO;
747 goto err_unmap_base2;
748 }
749
750 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
751 if (!ag->mii_ctrl) {
752 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
753 err = -ENOMEM;
754 goto err_unmap_base2;
755 }
756
757 dev->irq = platform_get_irq(pdev, 0);
758 err = request_irq(dev->irq, ag71xx_interrupt,
759 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
760 dev->name, dev);
761 if (err) {
762 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
763 goto err_unmap_mii_ctrl;
764 }
765
766 dev->base_addr = (unsigned long)ag->mac_base;
767 dev->open = ag71xx_open;
768 dev->stop = ag71xx_stop;
769 dev->hard_start_xmit = ag71xx_hard_start_xmit;
770 dev->set_multicast_list = ag71xx_set_multicast_list;
771 dev->do_ioctl = ag71xx_do_ioctl;
772 dev->ethtool_ops = &ag71xx_ethtool_ops;
773
774 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
775
776 if (is_valid_ether_addr(pdata->mac_addr))
777 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
778 else {
779 dev->dev_addr[0] = 0xde;
780 dev->dev_addr[1] = 0xad;
781 get_random_bytes(&dev->dev_addr[2], 3);
782 dev->dev_addr[5] = pdev->id & 0xff;
783 }
784
785 err = register_netdev(dev);
786 if (err) {
787 dev_err(&pdev->dev, "unable to register net device\n");
788 goto err_free_irq;
789 }
790
791 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
792 dev->name, dev->base_addr, dev->irq);
793
794 ag71xx_dump_regs(ag);
795
796 ag71xx_hw_init(ag);
797
798 ag71xx_dump_regs(ag);
799
800 /* Reset the mdio bus explicitly */
801 if (ag->mii_bus) {
802 mutex_lock(&ag->mii_bus->mdio_lock);
803 ag->mii_bus->reset(ag->mii_bus);
804 mutex_unlock(&ag->mii_bus->mdio_lock);
805 }
806
807 err = ag71xx_phy_connect(ag);
808 if (err)
809 goto err_unregister_netdev;
810
811 platform_set_drvdata(pdev, dev);
812
813 return 0;
814
815 err_unregister_netdev:
816 unregister_netdev(dev);
817 err_free_irq:
818 free_irq(dev->irq, dev);
819 err_unmap_mii_ctrl:
820 iounmap(ag->mii_ctrl);
821 err_unmap_base2:
822 iounmap(ag->mac_base2);
823 err_unmap_base1:
824 iounmap(ag->mac_base);
825 err_free_dev:
826 kfree(dev);
827 err_out:
828 platform_set_drvdata(pdev, NULL);
829 return err;
830 }
831
832 static int __exit ag71xx_remove(struct platform_device *pdev)
833 {
834 struct net_device *dev = platform_get_drvdata(pdev);
835
836 if (dev) {
837 struct ag71xx *ag = netdev_priv(dev);
838
839 ag71xx_phy_disconnect(ag);
840 unregister_netdev(dev);
841 free_irq(dev->irq, dev);
842 iounmap(ag->mii_ctrl);
843 iounmap(ag->mac_base2);
844 iounmap(ag->mac_base);
845 kfree(dev);
846 platform_set_drvdata(pdev, NULL);
847 }
848
849 return 0;
850 }
851
852 static struct platform_driver ag71xx_driver = {
853 .probe = ag71xx_probe,
854 .remove = __exit_p(ag71xx_remove),
855 .driver = {
856 .name = AG71XX_DRV_NAME,
857 }
858 };
859
860 static int __init ag71xx_module_init(void)
861 {
862 int ret;
863
864 ret = ag71xx_mdio_driver_init();
865 if (ret)
866 goto err_out;
867
868 ret = platform_driver_register(&ag71xx_driver);
869 if (ret)
870 goto err_mdio_exit;
871
872 return 0;
873
874 err_mdio_exit:
875 ag71xx_mdio_driver_exit();
876 err_out:
877 return ret;
878 }
879
880 static void __exit ag71xx_module_exit(void)
881 {
882 platform_driver_unregister(&ag71xx_driver);
883 }
884
885 module_init(ag71xx_module_init);
886 module_exit(ag71xx_module_exit);
887
888 MODULE_VERSION(AG71XX_DRV_VERSION);
889 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
890 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
891 MODULE_LICENSE("GPL v2");
892 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);