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[ar71xx] ag71xx driver: don't flush ddr on tx path
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 ( NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR )
25
26 static int ag71xx_debug = -1;
27
28 module_param(ag71xx_debug, int, 0);
29 MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40 ag->dev->name,
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49 ag->dev->name,
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86 kfree(ring->buf);
87
88 if (ring->descs)
89 dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
90 ring->descs, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
94 {
95 int err;
96
97 ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
98 &ring->descs_dma,
99 GFP_ATOMIC);
100 if (!ring->descs) {
101 err = -ENOMEM;
102 goto err;
103 }
104
105 ring->size = size;
106
107 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
108 if (!ring->buf) {
109 err = -ENOMEM;
110 goto err;
111 }
112
113 return 0;
114
115 err:
116 return err;
117 }
118
119 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
120 {
121 struct ag71xx_ring *ring = &ag->tx_ring;
122 struct net_device *dev = ag->dev;
123
124 while (ring->curr != ring->dirty) {
125 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
126
127 if (!ag71xx_desc_empty(&ring->descs[i])) {
128 ring->descs[i].ctrl = 0;
129 dev->stats.tx_errors++;
130 }
131
132 if (ring->buf[i].skb)
133 dev_kfree_skb_any(ring->buf[i].skb);
134
135 ring->buf[i].skb = NULL;
136
137 ring->dirty++;
138 }
139
140 /* flush descriptors */
141 wmb();
142
143 }
144
145 static void ag71xx_ring_tx_init(struct ag71xx *ag)
146 {
147 struct ag71xx_ring *ring = &ag->tx_ring;
148 int i;
149
150 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
151 ring->descs[i].next = (u32) (ring->descs_dma +
152 sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
153
154 ring->descs[i].ctrl = DESC_EMPTY;
155 ring->buf[i].skb = NULL;
156 }
157
158 /* flush descriptors */
159 wmb();
160
161 ring->curr = 0;
162 ring->dirty = 0;
163 }
164
165 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
166 {
167 struct ag71xx_ring *ring = &ag->rx_ring;
168 int i;
169
170 if (!ring->buf)
171 return;
172
173 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
174 if (ring->buf[i].skb)
175 kfree_skb(ring->buf[i].skb);
176
177 }
178
179 static int ag71xx_ring_rx_init(struct ag71xx *ag)
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 unsigned int i;
183 int ret;
184
185 ret = 0;
186 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
187 ring->descs[i].next = (u32) (ring->descs_dma +
188 sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
189
190 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
191 struct sk_buff *skb;
192
193 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
194 if (!skb) {
195 ret = -ENOMEM;
196 break;
197 }
198
199 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
200 DMA_FROM_DEVICE);
201
202 skb->dev = ag->dev;
203 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
204
205 ring->buf[i].skb = skb;
206 ring->descs[i].data = virt_to_phys(skb->data);
207 ring->descs[i].ctrl = DESC_EMPTY;
208 }
209
210 /* flush descriptors */
211 wmb();
212
213 ring->curr = 0;
214 ring->dirty = 0;
215
216 return ret;
217 }
218
219 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
220 {
221 struct ag71xx_ring *ring = &ag->rx_ring;
222 unsigned int count;
223
224 count = 0;
225 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
226 unsigned int i;
227
228 i = ring->dirty % AG71XX_RX_RING_SIZE;
229
230 if (ring->buf[i].skb == NULL) {
231 struct sk_buff *skb;
232
233 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
234 if (skb == NULL)
235 break;
236
237 dma_map_single(NULL, skb->data, AG71XX_RX_PKT_SIZE,
238 DMA_FROM_DEVICE);
239
240 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
241 skb->dev = ag->dev;
242
243 ring->buf[i].skb = skb;
244 ring->descs[i].data = virt_to_phys(skb->data);
245 }
246
247 ring->descs[i].ctrl = DESC_EMPTY;
248 count++;
249 }
250
251 /* flush descriptors */
252 wmb();
253
254 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
255
256 return count;
257 }
258
259 static int ag71xx_rings_init(struct ag71xx *ag)
260 {
261 int ret;
262
263 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
264 if (ret)
265 return ret;
266
267 ag71xx_ring_tx_init(ag);
268
269 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
270 if (ret)
271 return ret;
272
273 ret = ag71xx_ring_rx_init(ag);
274 return ret;
275 }
276
277 static void ag71xx_rings_cleanup(struct ag71xx *ag)
278 {
279 ag71xx_ring_rx_clean(ag);
280 ag71xx_ring_free(&ag->rx_ring);
281
282 ag71xx_ring_tx_clean(ag);
283 ag71xx_ring_free(&ag->tx_ring);
284 }
285
286 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
287 {
288 u32 t;
289
290 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
291 | (((u32) mac[2]) << 8) | ((u32) mac[3]);
292
293 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
294
295 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
296 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
297 }
298
299 static void ag71xx_dma_reset(struct ag71xx *ag)
300 {
301 int i;
302
303 ag71xx_dump_dma_regs(ag);
304
305 /* stop RX and TX */
306 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
307 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
308
309 /* clear descriptor addresses */
310 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
311 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
312
313 /* clear pending RX/TX interrupts */
314 for (i = 0; i < 256; i++) {
315 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
316 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
317 }
318
319 /* clear pending errors */
320 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
321 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
322
323 if (ag71xx_rr(ag, AG71XX_REG_RX_STATUS))
324 printk(KERN_ALERT "%s: unable to clear DMA Rx status\n",
325 ag->dev->name);
326
327 if (ag71xx_rr(ag, AG71XX_REG_TX_STATUS))
328 printk(KERN_ALERT "%s: unable to clear DMA Tx status\n",
329 ag->dev->name);
330
331 ag71xx_dump_dma_regs(ag);
332 }
333
334 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
335 MAC_CFG1_SRX | MAC_CFG1_STX)
336
337 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
338
339 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
340 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
341 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
342 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
343 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
344 FIFO_CFG4_VT)
345
346 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
347 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
348 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
349 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
350 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
351 FIFO_CFG5_17 | FIFO_CFG5_SF)
352
353 static void ag71xx_hw_init(struct ag71xx *ag)
354 {
355 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
356
357 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
358 udelay(20);
359
360 ar71xx_device_stop(pdata->reset_bit);
361 mdelay(100);
362 ar71xx_device_start(pdata->reset_bit);
363 mdelay(100);
364
365 /* setup MAC configuration registers */
366 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
367 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
368 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
369
370 /* setup max frame length */
371 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
372
373 /* setup MII interface type */
374 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
375
376 /* setup FIFO configuration registers */
377 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
378 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
379 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
380 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
381 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
382
383 ag71xx_dma_reset(ag);
384 }
385
386 static void ag71xx_hw_start(struct ag71xx *ag)
387 {
388 /* start RX engine */
389 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
390
391 /* enable interrupts */
392 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
393 }
394
395 static void ag71xx_hw_stop(struct ag71xx *ag)
396 {
397 /* disable all interrupts */
398 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
399
400 ag71xx_dma_reset(ag);
401 }
402
403 static int ag71xx_open(struct net_device *dev)
404 {
405 struct ag71xx *ag = netdev_priv(dev);
406 int ret;
407
408 ret = ag71xx_rings_init(ag);
409 if (ret)
410 goto err;
411
412 napi_enable(&ag->napi);
413
414 netif_carrier_off(dev);
415 ag71xx_phy_start(ag);
416
417 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
418 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
419
420 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
421
422 ag71xx_hw_start(ag);
423
424 netif_start_queue(dev);
425
426 return 0;
427
428 err:
429 ag71xx_rings_cleanup(ag);
430 return ret;
431 }
432
433 static int ag71xx_stop(struct net_device *dev)
434 {
435 struct ag71xx *ag = netdev_priv(dev);
436 unsigned long flags;
437
438 spin_lock_irqsave(&ag->lock, flags);
439
440 netif_stop_queue(dev);
441
442 ag71xx_hw_stop(ag);
443
444 netif_carrier_off(dev);
445 ag71xx_phy_stop(ag);
446
447 napi_disable(&ag->napi);
448 del_timer_sync(&ag->oom_timer);
449
450 spin_unlock_irqrestore(&ag->lock, flags);
451
452 ag71xx_rings_cleanup(ag);
453
454 return 0;
455 }
456
457 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
458 {
459 struct ag71xx *ag = netdev_priv(dev);
460 struct ag71xx_ring *ring = &ag->tx_ring;
461 struct ag71xx_desc *desc;
462 int i;
463
464 i = ring->curr % AG71XX_TX_RING_SIZE;
465 desc = &ring->descs[i];
466
467 if (!ag71xx_desc_empty(desc))
468 goto err_drop;
469
470 ag71xx_add_ar8216_header(ag, skb);
471
472 if (skb->len <= 0) {
473 DBG("%s: packet len is too small\n", ag->dev->name);
474 goto err_drop;
475 }
476
477 dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
478
479 ring->buf[i].skb = skb;
480
481 /* setup descriptor fields */
482 desc->data = virt_to_phys(skb->data);
483 desc->ctrl = (skb->len & DESC_PKTLEN_M);
484
485 /* flush descriptor */
486 wmb();
487
488 ring->curr++;
489 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
490 DBG("%s: tx queue full\n", ag->dev->name);
491 netif_stop_queue(dev);
492 }
493
494 DBG("%s: packet injected into TX queue\n", ag->dev->name);
495
496 /* enable TX engine */
497 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
498
499 dev->trans_start = jiffies;
500
501 return 0;
502
503 err_drop:
504 dev->stats.tx_dropped++;
505
506 dev_kfree_skb(skb);
507 return 0;
508 }
509
510 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
511 {
512 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
513 struct ag71xx *ag = netdev_priv(dev);
514 int ret;
515
516 switch (cmd) {
517 case SIOCETHTOOL:
518 if (ag->phy_dev == NULL)
519 break;
520
521 spin_lock_irq(&ag->lock);
522 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
523 spin_unlock_irq(&ag->lock);
524 return ret;
525
526 case SIOCSIFHWADDR:
527 if (copy_from_user
528 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
529 return -EFAULT;
530 return 0;
531
532 case SIOCGIFHWADDR:
533 if (copy_to_user
534 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
535 return -EFAULT;
536 return 0;
537
538 case SIOCGMIIPHY:
539 case SIOCGMIIREG:
540 case SIOCSMIIREG:
541 if (ag->phy_dev == NULL)
542 break;
543
544 return phy_mii_ioctl(ag->phy_dev, data, cmd);
545
546 default:
547 break;
548 }
549
550 return -EOPNOTSUPP;
551 }
552
553 static void ag71xx_oom_timer_handler(unsigned long data)
554 {
555 struct net_device *dev = (struct net_device *) data;
556 struct ag71xx *ag = netdev_priv(dev);
557
558 netif_rx_schedule(dev, &ag->napi);
559 }
560
561 static void ag71xx_tx_timeout(struct net_device *dev)
562 {
563 struct ag71xx *ag = netdev_priv(dev);
564
565 if (netif_msg_tx_err(ag))
566 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
567
568 schedule_work(&ag->restart_work);
569 }
570
571 static void ag71xx_restart_work_func(struct work_struct *work)
572 {
573 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
574
575 ag71xx_stop(ag->dev);
576 ag71xx_open(ag->dev);
577 }
578
579 static void ag71xx_tx_packets(struct ag71xx *ag)
580 {
581 struct ag71xx_ring *ring = &ag->tx_ring;
582 unsigned int sent;
583
584 DBG("%s: processing TX ring\n", ag->dev->name);
585
586 sent = 0;
587 while (ring->dirty != ring->curr) {
588 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
589 struct ag71xx_desc *desc = &ring->descs[i];
590 struct sk_buff *skb = ring->buf[i].skb;
591
592 if (!ag71xx_desc_empty(desc))
593 break;
594
595 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
596
597 ag->dev->stats.tx_bytes += skb->len;
598 ag->dev->stats.tx_packets++;
599
600 dev_kfree_skb_any(skb);
601 ring->buf[i].skb = NULL;
602
603 ring->dirty++;
604 sent++;
605 }
606
607 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
608
609 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
610 netif_wake_queue(ag->dev);
611
612 }
613
614 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
615 {
616 struct net_device *dev = ag->dev;
617 struct ag71xx_ring *ring = &ag->rx_ring;
618 int done = 0;
619
620 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
621 dev->name, limit, ring->curr, ring->dirty);
622
623 while (done < limit) {
624 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
625 struct ag71xx_desc *desc = &ring->descs[i];
626 struct sk_buff *skb;
627 int pktlen;
628
629 if (ag71xx_desc_empty(desc))
630 break;
631
632 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
633 ag71xx_assert(0);
634 break;
635 }
636
637 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
638
639 skb = ring->buf[i].skb;
640 pktlen = ag71xx_desc_pktlen(desc);
641 pktlen -= ETH_FCS_LEN;
642
643 skb_put(skb, pktlen);
644
645 skb->dev = dev;
646 skb->ip_summed = CHECKSUM_NONE;
647
648 dev->last_rx = jiffies;
649 dev->stats.rx_packets++;
650 dev->stats.rx_bytes += pktlen;
651
652 if (ag71xx_remove_ar8216_header(ag, skb) != 0) {
653 dev->stats.rx_dropped++;
654 kfree_skb(skb);
655 } else {
656 skb->protocol = eth_type_trans(skb, dev);
657 netif_receive_skb(skb);
658 }
659
660 ring->buf[i].skb = NULL;
661 done++;
662
663 ring->curr++;
664 }
665
666 ag71xx_ring_rx_refill(ag);
667
668 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
669 dev->name, ring->curr, ring->dirty, done);
670
671 return done;
672 }
673
674 static int ag71xx_poll(struct napi_struct *napi, int limit)
675 {
676 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
677 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
678 struct net_device *dev = ag->dev;
679 struct ag71xx_ring *rx_ring;
680 unsigned long flags;
681 u32 status;
682 int done;
683
684 pdata->ddr_flush();
685 ag71xx_tx_packets(ag);
686
687 DBG("%s: processing RX ring\n", dev->name);
688 done = ag71xx_rx_packets(ag, limit);
689
690 rx_ring = &ag->rx_ring;
691 if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL)
692 goto oom;
693
694 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
695 if (unlikely(status & RX_STATUS_OF)) {
696 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
697 dev->stats.rx_fifo_errors++;
698
699 /* restart RX */
700 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
701 }
702
703 if (done < limit) {
704 if (status & RX_STATUS_PR)
705 goto more;
706
707 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
708 if (status & TX_STATUS_PS)
709 goto more;
710
711 DBG("%s: disable polling mode, done=%d, limit=%d\n",
712 dev->name, done, limit);
713
714 netif_rx_complete(dev, napi);
715
716 /* enable interrupts */
717 spin_lock_irqsave(&ag->lock, flags);
718 ag71xx_int_enable(ag, AG71XX_INT_POLL);
719 spin_unlock_irqrestore(&ag->lock, flags);
720 return done;
721 }
722
723 more:
724 DBG("%s: stay in polling mode, done=%d, limit=%d\n",
725 dev->name, done, limit);
726 return done;
727
728 oom:
729 if (netif_msg_rx_err(ag))
730 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
731
732 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
733 netif_rx_complete(dev, napi);
734 return 0;
735 }
736
737 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
738 {
739 struct net_device *dev = dev_id;
740 struct ag71xx *ag = netdev_priv(dev);
741 u32 status;
742
743 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
744 ag71xx_dump_intr(ag, "raw", status);
745
746 if (unlikely(!status))
747 return IRQ_NONE;
748
749 if (unlikely(status & AG71XX_INT_ERR)) {
750 if (status & AG71XX_INT_TX_BE) {
751 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
752 dev_err(&dev->dev, "TX BUS error\n");
753 }
754 if (status & AG71XX_INT_RX_BE) {
755 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
756 dev_err(&dev->dev, "RX BUS error\n");
757 }
758 }
759
760 if (likely(status & AG71XX_INT_POLL)) {
761 ag71xx_int_disable(ag, AG71XX_INT_POLL);
762 DBG("%s: enable polling mode\n", dev->name);
763 netif_rx_schedule(dev, &ag->napi);
764 }
765
766 return IRQ_HANDLED;
767 }
768
769 static void ag71xx_set_multicast_list(struct net_device *dev)
770 {
771 /* TODO */
772 }
773
774 static int __init ag71xx_probe(struct platform_device *pdev)
775 {
776 struct net_device *dev;
777 struct resource *res;
778 struct ag71xx *ag;
779 struct ag71xx_platform_data *pdata;
780 int err;
781
782 pdata = pdev->dev.platform_data;
783 if (!pdata) {
784 dev_err(&pdev->dev, "no platform data specified\n");
785 err = -ENXIO;
786 goto err_out;
787 }
788
789 dev = alloc_etherdev(sizeof(*ag));
790 if (!dev) {
791 dev_err(&pdev->dev, "alloc_etherdev failed\n");
792 err = -ENOMEM;
793 goto err_out;
794 }
795
796 SET_NETDEV_DEV(dev, &pdev->dev);
797
798 ag = netdev_priv(dev);
799 ag->pdev = pdev;
800 ag->dev = dev;
801 ag->mii_bus = ag71xx_mdio_bus->mii_bus;
802 ag->msg_enable = netif_msg_init(ag71xx_debug,
803 AG71XX_DEFAULT_MSG_ENABLE);
804 spin_lock_init(&ag->lock);
805
806 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
807 if (!res) {
808 dev_err(&pdev->dev, "no mac_base resource found\n");
809 err = -ENXIO;
810 goto err_out;
811 }
812
813 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
814 if (!ag->mac_base) {
815 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
816 err = -ENOMEM;
817 goto err_free_dev;
818 }
819
820 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
821 if (!res) {
822 dev_err(&pdev->dev, "no mac_base2 resource found\n");
823 err = -ENXIO;
824 goto err_unmap_base1;
825 }
826
827 ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
828 if (!ag->mac_base) {
829 dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
830 err = -ENOMEM;
831 goto err_unmap_base1;
832 }
833
834 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
835 if (!res) {
836 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
837 err = -ENXIO;
838 goto err_unmap_base2;
839 }
840
841 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
842 if (!ag->mii_ctrl) {
843 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
844 err = -ENOMEM;
845 goto err_unmap_base2;
846 }
847
848 dev->irq = platform_get_irq(pdev, 0);
849 err = request_irq(dev->irq, ag71xx_interrupt,
850 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
851 dev->name, dev);
852 if (err) {
853 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
854 goto err_unmap_mii_ctrl;
855 }
856
857 dev->base_addr = (unsigned long)ag->mac_base;
858 dev->open = ag71xx_open;
859 dev->stop = ag71xx_stop;
860 dev->hard_start_xmit = ag71xx_hard_start_xmit;
861 dev->set_multicast_list = ag71xx_set_multicast_list;
862 dev->do_ioctl = ag71xx_do_ioctl;
863 dev->ethtool_ops = &ag71xx_ethtool_ops;
864
865 dev->tx_timeout = ag71xx_tx_timeout;
866 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
867
868 init_timer(&ag->oom_timer);
869 ag->oom_timer.data = (unsigned long) dev;
870 ag->oom_timer.function = ag71xx_oom_timer_handler;
871
872 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
873
874 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
875
876 err = register_netdev(dev);
877 if (err) {
878 dev_err(&pdev->dev, "unable to register net device\n");
879 goto err_free_irq;
880 }
881
882 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
883 dev->name, dev->base_addr, dev->irq);
884
885 ag71xx_dump_regs(ag);
886
887 ag71xx_hw_init(ag);
888
889 ag71xx_dump_regs(ag);
890
891 /* Reset the mdio bus explicitly */
892 if (ag->mii_bus) {
893 mutex_lock(&ag->mii_bus->mdio_lock);
894 ag->mii_bus->reset(ag->mii_bus);
895 mutex_unlock(&ag->mii_bus->mdio_lock);
896 }
897
898 err = ag71xx_phy_connect(ag);
899 if (err)
900 goto err_unregister_netdev;
901
902 platform_set_drvdata(pdev, dev);
903
904 return 0;
905
906 err_unregister_netdev:
907 unregister_netdev(dev);
908 err_free_irq:
909 free_irq(dev->irq, dev);
910 err_unmap_mii_ctrl:
911 iounmap(ag->mii_ctrl);
912 err_unmap_base2:
913 iounmap(ag->mac_base2);
914 err_unmap_base1:
915 iounmap(ag->mac_base);
916 err_free_dev:
917 kfree(dev);
918 err_out:
919 platform_set_drvdata(pdev, NULL);
920 return err;
921 }
922
923 static int __exit ag71xx_remove(struct platform_device *pdev)
924 {
925 struct net_device *dev = platform_get_drvdata(pdev);
926
927 if (dev) {
928 struct ag71xx *ag = netdev_priv(dev);
929
930 ag71xx_phy_disconnect(ag);
931 unregister_netdev(dev);
932 free_irq(dev->irq, dev);
933 iounmap(ag->mii_ctrl);
934 iounmap(ag->mac_base2);
935 iounmap(ag->mac_base);
936 kfree(dev);
937 platform_set_drvdata(pdev, NULL);
938 }
939
940 return 0;
941 }
942
943 static struct platform_driver ag71xx_driver = {
944 .probe = ag71xx_probe,
945 .remove = __exit_p(ag71xx_remove),
946 .driver = {
947 .name = AG71XX_DRV_NAME,
948 }
949 };
950
951 static int __init ag71xx_module_init(void)
952 {
953 int ret;
954
955 ret = ag71xx_mdio_driver_init();
956 if (ret)
957 goto err_out;
958
959 ret = platform_driver_register(&ag71xx_driver);
960 if (ret)
961 goto err_mdio_exit;
962
963 return 0;
964
965 err_mdio_exit:
966 ag71xx_mdio_driver_exit();
967 err_out:
968 return ret;
969 }
970
971 static void __exit ag71xx_module_exit(void)
972 {
973 platform_driver_unregister(&ag71xx_driver);
974 ag71xx_mdio_driver_exit();
975 }
976
977 module_init(ag71xx_module_init);
978 module_exit(ag71xx_module_exit);
979
980 MODULE_VERSION(AG71XX_DRV_VERSION);
981 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
982 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
983 MODULE_LICENSE("GPL v2");
984 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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