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[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 ( NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR )
25
26 static int ag71xx_debug = -1;
27
28 module_param(ag71xx_debug, int, 0);
29 MODULE_PARM_DESC(ag71xx_debug, "Debug level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_regs(struct ag71xx *ag)
32 {
33 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
36 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
37 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
38 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
39 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
40 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
41 ag->dev->name,
42 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
43 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
44 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
45 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
46 ag->dev->name,
47 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
48 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
49 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
50 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
51 ag->dev->name,
52 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
53 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
54 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
55 }
56
57 static void ag71xx_ring_free(struct ag71xx_ring *ring)
58 {
59 kfree(ring->buf);
60
61 if (ring->descs)
62 dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
63 ring->descs, ring->descs_dma);
64 }
65
66 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
67 {
68 int err;
69
70 ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
71 &ring->descs_dma,
72 GFP_ATOMIC);
73 if (!ring->descs) {
74 err = -ENOMEM;
75 goto err;
76 }
77
78 ring->size = size;
79
80 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
81 if (!ring->buf) {
82 err = -ENOMEM;
83 goto err;
84 }
85
86 return 0;
87
88 err:
89 return err;
90 }
91
92 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
93 {
94 struct ag71xx_ring *ring = &ag->tx_ring;
95 struct net_device *dev = ag->dev;
96
97 while (ring->curr != ring->dirty) {
98 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
99
100 if (!ag71xx_desc_empty(&ring->descs[i])) {
101 ring->descs[i].ctrl = 0;
102 dev->stats.tx_errors++;
103 }
104
105 if (ring->buf[i].skb)
106 dev_kfree_skb_any(ring->buf[i].skb);
107
108 ring->buf[i].skb = NULL;
109
110 ring->dirty++;
111 }
112
113 /* flush descriptors */
114 wmb();
115
116 }
117
118 static void ag71xx_ring_tx_init(struct ag71xx *ag)
119 {
120 struct ag71xx_ring *ring = &ag->tx_ring;
121 int i;
122
123 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
124 ring->descs[i].next = (u32) (ring->descs_dma +
125 sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
126
127 ring->descs[i].ctrl = DESC_EMPTY;
128 ring->buf[i].skb = NULL;
129 }
130
131 /* flush descriptors */
132 wmb();
133
134 ring->curr = 0;
135 ring->dirty = 0;
136 }
137
138 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
139 {
140 struct ag71xx_ring *ring = &ag->rx_ring;
141 int i;
142
143 if (!ring->buf)
144 return;
145
146 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
147 if (ring->buf[i].skb)
148 kfree_skb(ring->buf[i].skb);
149
150 }
151
152 static int ag71xx_ring_rx_init(struct ag71xx *ag)
153 {
154 struct ag71xx_ring *ring = &ag->rx_ring;
155 unsigned int i;
156 int ret;
157
158 ret = 0;
159 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
160 ring->descs[i].next = (u32) (ring->descs_dma +
161 sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
162
163 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
164 struct sk_buff *skb;
165
166 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
167 if (!skb) {
168 ret = -ENOMEM;
169 break;
170 }
171
172 skb->dev = ag->dev;
173 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
174
175 ring->buf[i].skb = skb;
176 ring->descs[i].data = virt_to_phys(skb->data);
177 ring->descs[i].ctrl = DESC_EMPTY;
178 }
179
180 /* flush descriptors */
181 wmb();
182
183 ring->curr = 0;
184 ring->dirty = 0;
185
186 return ret;
187 }
188
189 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
190 {
191 struct ag71xx_ring *ring = &ag->rx_ring;
192 unsigned int count;
193
194 count = 0;
195 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
196 unsigned int i;
197
198 i = ring->dirty % AG71XX_RX_RING_SIZE;
199
200 if (ring->buf[i].skb == NULL) {
201 struct sk_buff *skb;
202
203 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
204 if (skb == NULL) {
205 printk(KERN_ERR "%s: no memory for skb\n",
206 ag->dev->name);
207 break;
208 }
209
210 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
211 skb->dev = ag->dev;
212 ring->buf[i].skb = skb;
213 ring->descs[i].data = virt_to_phys(skb->data);
214 }
215
216 ring->descs[i].ctrl = DESC_EMPTY;
217 count++;
218 }
219
220 /* flush descriptors */
221 wmb();
222
223 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
224
225 return count;
226 }
227
228 static int ag71xx_rings_init(struct ag71xx *ag)
229 {
230 int ret;
231
232 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
233 if (ret)
234 return ret;
235
236 ag71xx_ring_tx_init(ag);
237
238 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
239 if (ret)
240 return ret;
241
242 ret = ag71xx_ring_rx_init(ag);
243 return ret;
244 }
245
246 static void ag71xx_rings_cleanup(struct ag71xx *ag)
247 {
248 ag71xx_ring_rx_clean(ag);
249 ag71xx_ring_free(&ag->rx_ring);
250
251 ag71xx_ring_tx_clean(ag);
252 ag71xx_ring_free(&ag->tx_ring);
253 }
254
255 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
256 {
257 u32 t;
258
259 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
260 | (((u32) mac[2]) << 8) | ((u32) mac[3]);
261
262 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
263
264 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
265 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
266 }
267
268 #define AR71XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
269 MAC_CFG1_SRX | MAC_CFG1_STX)
270 #define AR71XX_FIFO_CFG5_INIT 0x0007ffef
271
272 #define AR91XX_MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
273 MAC_CFG1_SRX | MAC_CFG1_STX | \
274 MAC_CFG1_TFC | MAC_CFG1_RFC)
275 #define AR91XX_FIFO_CFG5_INIT 0x0007efef
276
277 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
278
279 static void ag71xx_hw_init(struct ag71xx *ag)
280 {
281 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
282
283 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
284 udelay(20);
285
286 ar71xx_device_stop(pdata->reset_bit);
287 mdelay(100);
288 ar71xx_device_start(pdata->reset_bit);
289 mdelay(100);
290
291 /* setup MII interface type */
292 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
293
294 /* setup MAC configuration registers */
295 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1,
296 pdata->is_ar91xx ? AR91XX_MAC_CFG1_INIT : AR71XX_MAC_CFG1_INIT);
297 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
298 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
299
300 /* setup max frame length */
301 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
302
303 /* setup FIFO configuration registers */
304 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
305 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
306 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
307 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
308 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5,
309 pdata->is_ar91xx ? AR91XX_FIFO_CFG5_INIT
310 : AR71XX_FIFO_CFG5_INIT);
311 }
312
313 static void ag71xx_hw_start(struct ag71xx *ag)
314 {
315 /* start RX engine */
316 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
317
318 /* enable interrupts */
319 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
320 }
321
322 static void ag71xx_hw_stop(struct ag71xx *ag)
323 {
324 /* stop RX and TX */
325 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
326 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
327
328 /* disable all interrupts */
329 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
330 }
331
332 static int ag71xx_open(struct net_device *dev)
333 {
334 struct ag71xx *ag = netdev_priv(dev);
335 int ret;
336
337 ret = ag71xx_rings_init(ag);
338 if (ret)
339 goto err;
340
341 napi_enable(&ag->napi);
342
343 netif_carrier_off(dev);
344 ag71xx_phy_start(ag);
345
346 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
347 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
348
349 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
350
351 ag71xx_hw_start(ag);
352
353 netif_start_queue(dev);
354
355 return 0;
356
357 err:
358 ag71xx_rings_cleanup(ag);
359 return ret;
360 }
361
362 static int ag71xx_stop(struct net_device *dev)
363 {
364 struct ag71xx *ag = netdev_priv(dev);
365 unsigned long flags;
366
367 spin_lock_irqsave(&ag->lock, flags);
368
369 netif_stop_queue(dev);
370
371 ag71xx_hw_stop(ag);
372
373 netif_carrier_off(dev);
374 ag71xx_phy_stop(ag);
375
376 napi_disable(&ag->napi);
377
378 spin_unlock_irqrestore(&ag->lock, flags);
379
380 ag71xx_rings_cleanup(ag);
381
382 return 0;
383 }
384
385 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
386 {
387 struct ag71xx *ag = netdev_priv(dev);
388 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
389 struct ag71xx_ring *ring = &ag->tx_ring;
390 struct ag71xx_desc *desc;
391 unsigned long flags;
392 int i;
393
394 i = ring->curr % AG71XX_TX_RING_SIZE;
395 desc = &ring->descs[i];
396
397 spin_lock_irqsave(&ag->lock, flags);
398 pdata->ddr_flush();
399 spin_unlock_irqrestore(&ag->lock, flags);
400
401 if (!ag71xx_desc_empty(desc))
402 goto err_drop;
403
404 if (skb->len <= 0) {
405 DBG("%s: packet len is too small\n", ag->dev->name);
406 goto err_drop;
407 }
408
409 dma_cache_wback_inv((unsigned long)skb->data, skb->len);
410
411 ring->buf[i].skb = skb;
412
413 /* setup descriptor fields */
414 desc->data = virt_to_phys(skb->data);
415 desc->ctrl = (skb->len & DESC_PKTLEN_M);
416
417 /* flush descriptor */
418 wmb();
419
420 ring->curr++;
421 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
422 DBG("%s: tx queue full\n", ag->dev->name);
423 netif_stop_queue(dev);
424 }
425
426 DBG("%s: packet injected into TX queue\n", ag->dev->name);
427
428 /* enable TX engine */
429 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
430
431 dev->trans_start = jiffies;
432
433 return 0;
434
435 err_drop:
436 dev->stats.tx_dropped++;
437
438 dev_kfree_skb(skb);
439 return 0;
440 }
441
442 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
443 {
444 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
445 struct ag71xx *ag = netdev_priv(dev);
446 int ret;
447
448 switch (cmd) {
449 case SIOCETHTOOL:
450 if (ag->phy_dev == NULL)
451 break;
452
453 spin_lock_irq(&ag->lock);
454 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
455 spin_unlock_irq(&ag->lock);
456 return ret;
457
458 case SIOCSIFHWADDR:
459 if (copy_from_user
460 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
461 return -EFAULT;
462 return 0;
463
464 case SIOCGIFHWADDR:
465 if (copy_to_user
466 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
467 return -EFAULT;
468 return 0;
469
470 case SIOCGMIIPHY:
471 case SIOCGMIIREG:
472 case SIOCSMIIREG:
473 if (ag->phy_dev == NULL)
474 break;
475
476 return phy_mii_ioctl(ag->phy_dev, data, cmd);
477
478 default:
479 break;
480 }
481
482 return -EOPNOTSUPP;
483 }
484
485 static void ag71xx_tx_packets(struct ag71xx *ag)
486 {
487 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
488 struct ag71xx_ring *ring = &ag->tx_ring;
489 unsigned int sent;
490
491 DBG("%s: processing TX ring\n", ag->dev->name);
492
493 #ifdef AG71XX_NAPI_TX
494 pdata->ddr_flush();
495 #endif
496
497 sent = 0;
498 while (ring->dirty != ring->curr) {
499 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
500 struct ag71xx_desc *desc = &ring->descs[i];
501 struct sk_buff *skb = ring->buf[i].skb;
502
503 if (!ag71xx_desc_empty(desc))
504 break;
505
506 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
507
508 ag->dev->stats.tx_bytes += skb->len;
509 ag->dev->stats.tx_packets++;
510
511 dev_kfree_skb_any(skb);
512 ring->buf[i].skb = NULL;
513
514 ring->dirty++;
515 sent++;
516 }
517
518 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
519
520 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
521 netif_wake_queue(ag->dev);
522
523 }
524
525 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
526 {
527 struct net_device *dev = ag->dev;
528 struct ag71xx_ring *ring = &ag->rx_ring;
529 #ifndef AG71XX_NAPI_TX
530 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
531 unsigned long flags;
532 #endif
533 int done = 0;
534
535 #ifndef AG71XX_NAPI_TX
536 spin_lock_irqsave(&ag->lock, flags);
537 pdata->ddr_flush();
538 spin_unlock_irqrestore(&ag->lock, flags);
539 #endif
540
541 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
542 dev->name, limit, ring->curr, ring->dirty);
543
544 while (done < limit) {
545 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
546 struct ag71xx_desc *desc = &ring->descs[i];
547 struct sk_buff *skb;
548 int pktlen;
549
550 if (ag71xx_desc_empty(desc))
551 break;
552
553 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
554 ag71xx_assert(0);
555 break;
556 }
557
558 skb = ring->buf[i].skb;
559 pktlen = ag71xx_desc_pktlen(desc);
560 pktlen -= ETH_FCS_LEN;
561
562 /* TODO: move it into the refill function */
563 dma_cache_wback_inv((unsigned long)skb->data, pktlen);
564 skb_put(skb, pktlen);
565
566 skb->dev = dev;
567 skb->protocol = eth_type_trans(skb, dev);
568 skb->ip_summed = CHECKSUM_UNNECESSARY;
569
570 netif_receive_skb(skb);
571
572 dev->last_rx = jiffies;
573 dev->stats.rx_packets++;
574 dev->stats.rx_bytes += pktlen;
575
576 ring->buf[i].skb = NULL;
577 done++;
578
579 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
580
581 ring->curr++;
582 if ((ring->curr - ring->dirty) > (AG71XX_RX_RING_SIZE / 4))
583 ag71xx_ring_rx_refill(ag);
584 }
585
586 ag71xx_ring_rx_refill(ag);
587
588 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
589 dev->name, ring->curr, ring->dirty, done);
590
591 return done;
592 }
593
594 static int ag71xx_poll(struct napi_struct *napi, int limit)
595 {
596 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
597 #ifdef AG71XX_NAPI_TX
598 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
599 #endif
600 struct net_device *dev = ag->dev;
601 unsigned long flags;
602 u32 status;
603 int done;
604
605 #ifdef AG71XX_NAPI_TX
606 pdata->ddr_flush();
607 ag71xx_tx_packets(ag);
608 #endif
609
610 DBG("%s: processing RX ring\n", dev->name);
611 done = ag71xx_rx_packets(ag, limit);
612
613 /* TODO: add OOM handler */
614
615 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
616 status &= AG71XX_INT_POLL;
617
618 if ((done < limit) && (!status)) {
619 DBG("%s: disable polling mode, done=%d, status=%x\n",
620 dev->name, done, status);
621
622 netif_rx_complete(dev, napi);
623
624 /* enable interrupts */
625 spin_lock_irqsave(&ag->lock, flags);
626 ag71xx_int_enable(ag, AG71XX_INT_POLL);
627 spin_unlock_irqrestore(&ag->lock, flags);
628 return 0;
629 }
630
631 if (status & AG71XX_INT_RX_OF) {
632 if (netif_msg_rx_err(ag))
633 printk(KERN_ALERT "%s: rx owerflow, restarting dma\n",
634 dev->name);
635
636 /* ack interrupt */
637 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
638 /* restart RX */
639 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
640 }
641
642 DBG("%s: stay in polling mode, done=%d, status=%x\n",
643 dev->name, done, status);
644 return 1;
645 }
646
647 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
648 {
649 struct net_device *dev = dev_id;
650 struct ag71xx *ag = netdev_priv(dev);
651 u32 status;
652
653 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
654 status &= ag71xx_rr(ag, AG71XX_REG_INT_ENABLE);
655
656 if (unlikely(!status))
657 return IRQ_NONE;
658
659 if (unlikely(status & AG71XX_INT_ERR)) {
660 if (status & AG71XX_INT_TX_BE) {
661 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
662 dev_err(&dev->dev, "TX BUS error\n");
663 }
664 if (status & AG71XX_INT_RX_BE) {
665 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
666 dev_err(&dev->dev, "RX BUS error\n");
667 }
668 }
669
670 #if 0
671 if (unlikely(status & AG71XX_INT_TX_UR)) {
672 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_UR);
673 DBG("%s: TX underrun\n", dev->name);
674 }
675 #endif
676
677 #ifndef AG71XX_NAPI_TX
678 if (likely(status & AG71XX_INT_TX_PS))
679 ag71xx_tx_packets(ag);
680 #endif
681
682 if (likely(status & AG71XX_INT_POLL)) {
683 ag71xx_int_disable(ag, AG71XX_INT_POLL);
684 DBG("%s: enable polling mode\n", dev->name);
685 netif_rx_schedule(dev, &ag->napi);
686 }
687
688 return IRQ_HANDLED;
689 }
690
691 static void ag71xx_set_multicast_list(struct net_device *dev)
692 {
693 /* TODO */
694 }
695
696 static int __init ag71xx_probe(struct platform_device *pdev)
697 {
698 struct net_device *dev;
699 struct resource *res;
700 struct ag71xx *ag;
701 struct ag71xx_platform_data *pdata;
702 int err;
703
704 pdata = pdev->dev.platform_data;
705 if (!pdata) {
706 dev_err(&pdev->dev, "no platform data specified\n");
707 err = -ENXIO;
708 goto err_out;
709 }
710
711 dev = alloc_etherdev(sizeof(*ag));
712 if (!dev) {
713 dev_err(&pdev->dev, "alloc_etherdev failed\n");
714 err = -ENOMEM;
715 goto err_out;
716 }
717
718 SET_NETDEV_DEV(dev, &pdev->dev);
719
720 ag = netdev_priv(dev);
721 ag->pdev = pdev;
722 ag->dev = dev;
723 ag->mii_bus = &ag71xx_mdio_bus->mii_bus;
724 ag->msg_enable = netif_msg_init(ag71xx_debug,
725 AG71XX_DEFAULT_MSG_ENABLE);
726 spin_lock_init(&ag->lock);
727
728 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
729 if (!res) {
730 dev_err(&pdev->dev, "no mac_base resource found\n");
731 err = -ENXIO;
732 goto err_out;
733 }
734
735 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
736 if (!ag->mac_base) {
737 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
738 err = -ENOMEM;
739 goto err_free_dev;
740 }
741
742 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
743 if (!res) {
744 dev_err(&pdev->dev, "no mac_base2 resource found\n");
745 err = -ENXIO;
746 goto err_unmap_base1;
747 }
748
749 ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
750 if (!ag->mac_base) {
751 dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
752 err = -ENOMEM;
753 goto err_unmap_base1;
754 }
755
756 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
757 if (!res) {
758 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
759 err = -ENXIO;
760 goto err_unmap_base2;
761 }
762
763 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
764 if (!ag->mii_ctrl) {
765 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
766 err = -ENOMEM;
767 goto err_unmap_base2;
768 }
769
770 dev->irq = platform_get_irq(pdev, 0);
771 err = request_irq(dev->irq, ag71xx_interrupt,
772 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
773 dev->name, dev);
774 if (err) {
775 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
776 goto err_unmap_mii_ctrl;
777 }
778
779 dev->base_addr = (unsigned long)ag->mac_base;
780 dev->open = ag71xx_open;
781 dev->stop = ag71xx_stop;
782 dev->hard_start_xmit = ag71xx_hard_start_xmit;
783 dev->set_multicast_list = ag71xx_set_multicast_list;
784 dev->do_ioctl = ag71xx_do_ioctl;
785 dev->ethtool_ops = &ag71xx_ethtool_ops;
786
787 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
788
789 if (is_valid_ether_addr(pdata->mac_addr))
790 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
791 else {
792 dev->dev_addr[0] = 0xde;
793 dev->dev_addr[1] = 0xad;
794 get_random_bytes(&dev->dev_addr[2], 3);
795 dev->dev_addr[5] = pdev->id & 0xff;
796 }
797
798 err = register_netdev(dev);
799 if (err) {
800 dev_err(&pdev->dev, "unable to register net device\n");
801 goto err_free_irq;
802 }
803
804 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
805 dev->name, dev->base_addr, dev->irq);
806
807 ag71xx_dump_regs(ag);
808
809 ag71xx_hw_init(ag);
810
811 ag71xx_dump_regs(ag);
812
813 /* Reset the mdio bus explicitly */
814 if (ag->mii_bus) {
815 mutex_lock(&ag->mii_bus->mdio_lock);
816 ag->mii_bus->reset(ag->mii_bus);
817 mutex_unlock(&ag->mii_bus->mdio_lock);
818 }
819
820 err = ag71xx_phy_connect(ag);
821 if (err)
822 goto err_unregister_netdev;
823
824 platform_set_drvdata(pdev, dev);
825
826 return 0;
827
828 err_unregister_netdev:
829 unregister_netdev(dev);
830 err_free_irq:
831 free_irq(dev->irq, dev);
832 err_unmap_mii_ctrl:
833 iounmap(ag->mii_ctrl);
834 err_unmap_base2:
835 iounmap(ag->mac_base2);
836 err_unmap_base1:
837 iounmap(ag->mac_base);
838 err_free_dev:
839 kfree(dev);
840 err_out:
841 platform_set_drvdata(pdev, NULL);
842 return err;
843 }
844
845 static int __exit ag71xx_remove(struct platform_device *pdev)
846 {
847 struct net_device *dev = platform_get_drvdata(pdev);
848
849 if (dev) {
850 struct ag71xx *ag = netdev_priv(dev);
851
852 ag71xx_phy_disconnect(ag);
853 unregister_netdev(dev);
854 free_irq(dev->irq, dev);
855 iounmap(ag->mii_ctrl);
856 iounmap(ag->mac_base2);
857 iounmap(ag->mac_base);
858 kfree(dev);
859 platform_set_drvdata(pdev, NULL);
860 }
861
862 return 0;
863 }
864
865 static struct platform_driver ag71xx_driver = {
866 .probe = ag71xx_probe,
867 .remove = __exit_p(ag71xx_remove),
868 .driver = {
869 .name = AG71XX_DRV_NAME,
870 }
871 };
872
873 static int __init ag71xx_module_init(void)
874 {
875 int ret;
876
877 ret = ag71xx_mdio_driver_init();
878 if (ret)
879 goto err_out;
880
881 ret = platform_driver_register(&ag71xx_driver);
882 if (ret)
883 goto err_mdio_exit;
884
885 return 0;
886
887 err_mdio_exit:
888 ag71xx_mdio_driver_exit();
889 err_out:
890 return ret;
891 }
892
893 static void __exit ag71xx_module_exit(void)
894 {
895 platform_driver_unregister(&ag71xx_driver);
896 ag71xx_mdio_driver_exit();
897 }
898
899 module_init(ag71xx_module_init);
900 module_exit(ag71xx_module_exit);
901
902 MODULE_VERSION(AG71XX_DRV_VERSION);
903 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
904 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
905 MODULE_LICENSE("GPL v2");
906 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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