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ar71xx: ag71xx: prepare to make ring sizes configurable
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 (NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
32 {
33 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
34 ag->dev->name,
35 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
36 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
37 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
38
39 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
40 ag->dev->name,
41 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
42 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
43 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
44 }
45
46 static void ag71xx_dump_regs(struct ag71xx *ag)
47 {
48 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
49 ag->dev->name,
50 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
51 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
52 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
53 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
54 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
55 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
58 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
59 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
60 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
63 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
65 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
70 }
71
72 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
73 {
74 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
75 ag->dev->name, label, intr,
76 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
77 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
78 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
79 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
80 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
81 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
82 }
83
84 static void ag71xx_ring_free(struct ag71xx_ring *ring)
85 {
86 kfree(ring->buf);
87
88 if (ring->descs_cpu)
89 dma_free_coherent(NULL, ring->size * ring->desc_size,
90 ring->descs_cpu, ring->descs_dma);
91 }
92
93 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
94 {
95 int err;
96 int i;
97
98 ring->desc_size = sizeof(struct ag71xx_desc);
99 if (ring->desc_size % cache_line_size()) {
100 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
101 ring, ring->desc_size,
102 roundup(ring->desc_size, cache_line_size()));
103 ring->desc_size = roundup(ring->desc_size, cache_line_size());
104 }
105
106 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
107 &ring->descs_dma, GFP_ATOMIC);
108 if (!ring->descs_cpu) {
109 err = -ENOMEM;
110 goto err;
111 }
112
113
114 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
115 if (!ring->buf) {
116 err = -ENOMEM;
117 goto err;
118 }
119
120 for (i = 0; i < ring->size; i++) {
121 int idx = i * ring->desc_size;
122 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
123 DBG("ag71xx: ring %p, desc %d at %p\n",
124 ring, i, ring->buf[i].desc);
125 }
126
127 return 0;
128
129 err:
130 return err;
131 }
132
133 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
134 {
135 struct ag71xx_ring *ring = &ag->tx_ring;
136 struct net_device *dev = ag->dev;
137
138 while (ring->curr != ring->dirty) {
139 u32 i = ring->dirty % ring->size;
140
141 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
142 ring->buf[i].desc->ctrl = 0;
143 dev->stats.tx_errors++;
144 }
145
146 if (ring->buf[i].skb)
147 dev_kfree_skb_any(ring->buf[i].skb);
148
149 ring->buf[i].skb = NULL;
150
151 ring->dirty++;
152 }
153
154 /* flush descriptors */
155 wmb();
156
157 }
158
159 static void ag71xx_ring_tx_init(struct ag71xx *ag)
160 {
161 struct ag71xx_ring *ring = &ag->tx_ring;
162 int i;
163
164 for (i = 0; i < ring->size; i++) {
165 ring->buf[i].desc->next = (u32) (ring->descs_dma +
166 ring->desc_size * ((i + 1) % ring->size));
167
168 ring->buf[i].desc->ctrl = DESC_EMPTY;
169 ring->buf[i].skb = NULL;
170 }
171
172 /* flush descriptors */
173 wmb();
174
175 ring->curr = 0;
176 ring->dirty = 0;
177 }
178
179 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 int i;
183
184 if (!ring->buf)
185 return;
186
187 for (i = 0; i < ring->size; i++)
188 if (ring->buf[i].skb) {
189 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
190 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
191 kfree_skb(ring->buf[i].skb);
192 }
193 }
194
195 static int ag71xx_rx_reserve(struct ag71xx *ag)
196 {
197 int reserve = 0;
198
199 if (ag71xx_get_pdata(ag)->is_ar724x) {
200 if (!ag71xx_has_ar8216(ag))
201 reserve = 2;
202
203 if (ag->phy_dev)
204 reserve += 4 - (ag->phy_dev->pkt_align % 4);
205
206 reserve %= 4;
207 }
208
209 return reserve + AG71XX_RX_PKT_RESERVE;
210 }
211
212
213 static int ag71xx_ring_rx_init(struct ag71xx *ag)
214 {
215 struct ag71xx_ring *ring = &ag->rx_ring;
216 unsigned int reserve = ag71xx_rx_reserve(ag);
217 unsigned int i;
218 int ret;
219
220 ret = 0;
221 for (i = 0; i < ring->size; i++) {
222 ring->buf[i].desc->next = (u32) (ring->descs_dma +
223 ring->desc_size * ((i + 1) % ring->size));
224
225 DBG("ag71xx: RX desc at %p, next is %08x\n",
226 ring->buf[i].desc,
227 ring->buf[i].desc->next);
228 }
229
230 for (i = 0; i < ring->size; i++) {
231 struct sk_buff *skb;
232 dma_addr_t dma_addr;
233
234 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
235 if (!skb) {
236 ret = -ENOMEM;
237 break;
238 }
239
240 skb->dev = ag->dev;
241 skb_reserve(skb, reserve);
242
243 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
244 AG71XX_RX_PKT_SIZE,
245 DMA_FROM_DEVICE);
246 ring->buf[i].skb = skb;
247 ring->buf[i].dma_addr = dma_addr;
248 ring->buf[i].desc->data = (u32) dma_addr;
249 ring->buf[i].desc->ctrl = DESC_EMPTY;
250 }
251
252 /* flush descriptors */
253 wmb();
254
255 ring->curr = 0;
256 ring->dirty = 0;
257
258 return ret;
259 }
260
261 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
262 {
263 struct ag71xx_ring *ring = &ag->rx_ring;
264 unsigned int reserve = ag71xx_rx_reserve(ag);
265 unsigned int count;
266
267 count = 0;
268 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
269 unsigned int i;
270
271 i = ring->dirty % ring->size;
272
273 if (ring->buf[i].skb == NULL) {
274 dma_addr_t dma_addr;
275 struct sk_buff *skb;
276
277 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve);
278 if (skb == NULL)
279 break;
280
281 skb_reserve(skb, reserve);
282 skb->dev = ag->dev;
283
284 dma_addr = dma_map_single(&ag->dev->dev, skb->data,
285 AG71XX_RX_PKT_SIZE,
286 DMA_FROM_DEVICE);
287
288 ring->buf[i].skb = skb;
289 ring->buf[i].dma_addr = dma_addr;
290 ring->buf[i].desc->data = (u32) dma_addr;
291 }
292
293 ring->buf[i].desc->ctrl = DESC_EMPTY;
294 count++;
295 }
296
297 /* flush descriptors */
298 wmb();
299
300 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
301
302 return count;
303 }
304
305 static int ag71xx_rings_init(struct ag71xx *ag)
306 {
307 int ret;
308
309 ret = ag71xx_ring_alloc(&ag->tx_ring);
310 if (ret)
311 return ret;
312
313 ag71xx_ring_tx_init(ag);
314
315 ret = ag71xx_ring_alloc(&ag->rx_ring);
316 if (ret)
317 return ret;
318
319 ret = ag71xx_ring_rx_init(ag);
320 return ret;
321 }
322
323 static void ag71xx_rings_cleanup(struct ag71xx *ag)
324 {
325 ag71xx_ring_rx_clean(ag);
326 ag71xx_ring_free(&ag->rx_ring);
327
328 ag71xx_ring_tx_clean(ag);
329 ag71xx_ring_free(&ag->tx_ring);
330 }
331
332 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
333 {
334 switch (ag->speed) {
335 case SPEED_1000:
336 return "1000";
337 case SPEED_100:
338 return "100";
339 case SPEED_10:
340 return "10";
341 }
342
343 return "?";
344 }
345
346 static void ag71xx_dma_reset(struct ag71xx *ag)
347 {
348 u32 val;
349 int i;
350
351 ag71xx_dump_dma_regs(ag);
352
353 /* stop RX and TX */
354 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
355 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
356
357 /*
358 * give the hardware some time to really stop all rx/tx activity
359 * clearing the descriptors too early causes random memory corruption
360 */
361 mdelay(1);
362
363 /* clear descriptor addresses */
364 ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0);
365 ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0);
366
367 /* clear pending RX/TX interrupts */
368 for (i = 0; i < 256; i++) {
369 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
370 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
371 }
372
373 /* clear pending errors */
374 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
375 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
376
377 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
378 if (val)
379 printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n",
380 ag->dev->name, val);
381
382 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
383
384 /* mask out reserved bits */
385 val &= ~0xff000000;
386
387 if (val)
388 printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n",
389 ag->dev->name, val);
390
391 ag71xx_dump_dma_regs(ag);
392 }
393
394 static void ag71xx_hw_start(struct ag71xx *ag)
395 {
396 /* start RX engine */
397 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
398
399 /* enable interrupts */
400 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
401 }
402
403 static void ag71xx_hw_stop(struct ag71xx *ag)
404 {
405 /* disable all interrupts */
406 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
407
408 ag71xx_dma_reset(ag);
409 }
410
411 void ag71xx_link_adjust(struct ag71xx *ag)
412 {
413 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
414 u32 cfg2;
415 u32 ifctl;
416 u32 fifo5;
417 u32 mii_speed;
418
419 if (!ag->link) {
420 ag71xx_hw_stop(ag);
421 netif_carrier_off(ag->dev);
422 if (netif_msg_link(ag))
423 printk(KERN_INFO "%s: link down\n", ag->dev->name);
424 return;
425 }
426
427 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
428 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
429 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
430
431 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
432 ifctl &= ~(MAC_IFCTL_SPEED);
433
434 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
435 fifo5 &= ~FIFO_CFG5_BM;
436
437 switch (ag->speed) {
438 case SPEED_1000:
439 mii_speed = MII_CTRL_SPEED_1000;
440 cfg2 |= MAC_CFG2_IF_1000;
441 fifo5 |= FIFO_CFG5_BM;
442 break;
443 case SPEED_100:
444 mii_speed = MII_CTRL_SPEED_100;
445 cfg2 |= MAC_CFG2_IF_10_100;
446 ifctl |= MAC_IFCTL_SPEED;
447 break;
448 case SPEED_10:
449 mii_speed = MII_CTRL_SPEED_10;
450 cfg2 |= MAC_CFG2_IF_10_100;
451 break;
452 default:
453 BUG();
454 return;
455 }
456
457 if (pdata->is_ar91xx)
458 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
459 else if (pdata->is_ar724x)
460 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
461 else
462 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
463
464 if (pdata->set_pll)
465 pdata->set_pll(ag->speed);
466
467 ag71xx_mii_ctrl_set_speed(ag, mii_speed);
468
469 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
470 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
471 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
472
473 ag71xx_hw_start(ag);
474
475 netif_carrier_on(ag->dev);
476 if (netif_msg_link(ag))
477 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
478 ag->dev->name,
479 ag71xx_speed_str(ag),
480 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
481
482 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
483 ag->dev->name,
484 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
485 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
486 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
487
488 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
489 ag->dev->name,
490 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
491 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
492 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
493
494 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n",
495 ag->dev->name,
496 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
497 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
498 ag71xx_mii_ctrl_rr(ag));
499 }
500
501 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
502 {
503 u32 t;
504
505 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
506 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
507
508 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
509
510 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
511 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
512 }
513
514 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
515 MAC_CFG1_SRX | MAC_CFG1_STX)
516
517 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
518
519 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
520 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
521 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
522 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
523 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
524 FIFO_CFG4_VT)
525
526 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
527 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
528 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
529 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
530 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
531 FIFO_CFG5_17 | FIFO_CFG5_SF)
532
533 static void ag71xx_hw_init(struct ag71xx *ag)
534 {
535 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
536
537 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
538 udelay(20);
539
540 ar71xx_device_stop(pdata->reset_bit);
541 mdelay(100);
542 ar71xx_device_start(pdata->reset_bit);
543 mdelay(100);
544
545 /* setup MAC configuration registers */
546 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
547
548 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
549 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
550
551 /* setup max frame length */
552 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN);
553
554 /* setup MII interface type */
555 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
556
557 /* setup FIFO configuration registers */
558 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
559 if (pdata->is_ar724x) {
560 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
561 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
562 } else {
563 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
564 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
565 }
566 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
567 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
568
569 ag71xx_dma_reset(ag);
570 }
571
572 static int ag71xx_open(struct net_device *dev)
573 {
574 struct ag71xx *ag = netdev_priv(dev);
575 int ret;
576
577 ret = ag71xx_rings_init(ag);
578 if (ret)
579 goto err;
580
581 napi_enable(&ag->napi);
582
583 netif_carrier_off(dev);
584 ag71xx_phy_start(ag);
585
586 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
587 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
588
589 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
590
591 netif_start_queue(dev);
592
593 return 0;
594
595 err:
596 ag71xx_rings_cleanup(ag);
597 return ret;
598 }
599
600 static int ag71xx_stop(struct net_device *dev)
601 {
602 struct ag71xx *ag = netdev_priv(dev);
603 unsigned long flags;
604
605 netif_carrier_off(dev);
606 ag71xx_phy_stop(ag);
607
608 spin_lock_irqsave(&ag->lock, flags);
609
610 netif_stop_queue(dev);
611
612 ag71xx_hw_stop(ag);
613
614 napi_disable(&ag->napi);
615 del_timer_sync(&ag->oom_timer);
616
617 spin_unlock_irqrestore(&ag->lock, flags);
618
619 ag71xx_rings_cleanup(ag);
620
621 return 0;
622 }
623
624 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
625 struct net_device *dev)
626 {
627 struct ag71xx *ag = netdev_priv(dev);
628 struct ag71xx_ring *ring = &ag->tx_ring;
629 struct ag71xx_desc *desc;
630 dma_addr_t dma_addr;
631 int i;
632
633 i = ring->curr % ring->size;
634 desc = ring->buf[i].desc;
635
636 if (!ag71xx_desc_empty(desc))
637 goto err_drop;
638
639 if (ag71xx_has_ar8216(ag))
640 ag71xx_add_ar8216_header(ag, skb);
641
642 if (skb->len <= 0) {
643 DBG("%s: packet len is too small\n", ag->dev->name);
644 goto err_drop;
645 }
646
647 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
648 DMA_TO_DEVICE);
649
650 ring->buf[i].skb = skb;
651 ring->buf[i].timestamp = jiffies;
652
653 /* setup descriptor fields */
654 desc->data = (u32) dma_addr;
655 desc->ctrl = (skb->len & DESC_PKTLEN_M);
656
657 /* flush descriptor */
658 wmb();
659
660 ring->curr++;
661 if (ring->curr == (ring->dirty + ring->size)) {
662 DBG("%s: tx queue full\n", ag->dev->name);
663 netif_stop_queue(dev);
664 }
665
666 DBG("%s: packet injected into TX queue\n", ag->dev->name);
667
668 /* enable TX engine */
669 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
670
671 return NETDEV_TX_OK;
672
673 err_drop:
674 dev->stats.tx_dropped++;
675
676 dev_kfree_skb(skb);
677 return NETDEV_TX_OK;
678 }
679
680 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
681 {
682 struct ag71xx *ag = netdev_priv(dev);
683 int ret;
684
685 switch (cmd) {
686 case SIOCETHTOOL:
687 if (ag->phy_dev == NULL)
688 break;
689
690 spin_lock_irq(&ag->lock);
691 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
692 spin_unlock_irq(&ag->lock);
693 return ret;
694
695 case SIOCSIFHWADDR:
696 if (copy_from_user
697 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
698 return -EFAULT;
699 return 0;
700
701 case SIOCGIFHWADDR:
702 if (copy_to_user
703 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
704 return -EFAULT;
705 return 0;
706
707 case SIOCGMIIPHY:
708 case SIOCGMIIREG:
709 case SIOCSMIIREG:
710 if (ag->phy_dev == NULL)
711 break;
712
713 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
714
715 default:
716 break;
717 }
718
719 return -EOPNOTSUPP;
720 }
721
722 static void ag71xx_oom_timer_handler(unsigned long data)
723 {
724 struct net_device *dev = (struct net_device *) data;
725 struct ag71xx *ag = netdev_priv(dev);
726
727 napi_schedule(&ag->napi);
728 }
729
730 static void ag71xx_tx_timeout(struct net_device *dev)
731 {
732 struct ag71xx *ag = netdev_priv(dev);
733
734 if (netif_msg_tx_err(ag))
735 printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name);
736
737 schedule_work(&ag->restart_work);
738 }
739
740 static void ag71xx_restart_work_func(struct work_struct *work)
741 {
742 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
743 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
744
745 ag71xx_stop(ag->dev);
746
747 if (pdata->is_ar724x)
748 ag71xx_hw_init(ag);
749
750 ag71xx_open(ag->dev);
751 }
752
753 static int ag71xx_tx_packets(struct ag71xx *ag)
754 {
755 struct ag71xx_ring *ring = &ag->tx_ring;
756 int sent;
757
758 DBG("%s: processing TX ring\n", ag->dev->name);
759
760 sent = 0;
761 while (ring->dirty != ring->curr) {
762 unsigned int i = ring->dirty % ring->size;
763 struct ag71xx_desc *desc = ring->buf[i].desc;
764 struct sk_buff *skb = ring->buf[i].skb;
765
766 if (!ag71xx_desc_empty(desc))
767 break;
768
769 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
770
771 ag->dev->stats.tx_bytes += skb->len;
772 ag->dev->stats.tx_packets++;
773
774 dev_kfree_skb_any(skb);
775 ring->buf[i].skb = NULL;
776
777 ring->dirty++;
778 sent++;
779 }
780
781 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
782
783 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
784 netif_wake_queue(ag->dev);
785
786 return sent;
787 }
788
789 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
790 {
791 struct net_device *dev = ag->dev;
792 struct ag71xx_ring *ring = &ag->rx_ring;
793 int done = 0;
794
795 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
796 dev->name, limit, ring->curr, ring->dirty);
797
798 while (done < limit) {
799 unsigned int i = ring->curr % ring->size;
800 struct ag71xx_desc *desc = ring->buf[i].desc;
801 struct sk_buff *skb;
802 int pktlen;
803 int err = 0;
804
805 if (ag71xx_desc_empty(desc))
806 break;
807
808 if ((ring->dirty + ring->size) == ring->curr) {
809 ag71xx_assert(0);
810 break;
811 }
812
813 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
814
815 skb = ring->buf[i].skb;
816 pktlen = ag71xx_desc_pktlen(desc);
817 pktlen -= ETH_FCS_LEN;
818
819 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
820 AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE);
821
822 dev->last_rx = jiffies;
823 dev->stats.rx_packets++;
824 dev->stats.rx_bytes += pktlen;
825
826 skb_put(skb, pktlen);
827 if (ag71xx_has_ar8216(ag))
828 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
829
830 if (err) {
831 dev->stats.rx_dropped++;
832 kfree_skb(skb);
833 } else {
834 skb->dev = dev;
835 skb->ip_summed = CHECKSUM_NONE;
836 if (ag->phy_dev) {
837 ag->phy_dev->netif_receive_skb(skb);
838 } else {
839 skb->protocol = eth_type_trans(skb, dev);
840 netif_receive_skb(skb);
841 }
842 }
843
844 ring->buf[i].skb = NULL;
845 done++;
846
847 ring->curr++;
848 }
849
850 ag71xx_ring_rx_refill(ag);
851
852 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
853 dev->name, ring->curr, ring->dirty, done);
854
855 return done;
856 }
857
858 static int ag71xx_poll(struct napi_struct *napi, int limit)
859 {
860 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
861 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
862 struct net_device *dev = ag->dev;
863 struct ag71xx_ring *rx_ring;
864 unsigned long flags;
865 u32 status;
866 int tx_done;
867 int rx_done;
868
869 pdata->ddr_flush();
870 tx_done = ag71xx_tx_packets(ag);
871
872 DBG("%s: processing RX ring\n", dev->name);
873 rx_done = ag71xx_rx_packets(ag, limit);
874
875 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
876
877 rx_ring = &ag->rx_ring;
878 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].skb == NULL)
879 goto oom;
880
881 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
882 if (unlikely(status & RX_STATUS_OF)) {
883 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
884 dev->stats.rx_fifo_errors++;
885
886 /* restart RX */
887 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
888 }
889
890 if (rx_done < limit) {
891 if (status & RX_STATUS_PR)
892 goto more;
893
894 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
895 if (status & TX_STATUS_PS)
896 goto more;
897
898 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
899 dev->name, rx_done, tx_done, limit);
900
901 napi_complete(napi);
902
903 /* enable interrupts */
904 spin_lock_irqsave(&ag->lock, flags);
905 ag71xx_int_enable(ag, AG71XX_INT_POLL);
906 spin_unlock_irqrestore(&ag->lock, flags);
907 return rx_done;
908 }
909
910 more:
911 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
912 dev->name, rx_done, tx_done, limit);
913 return rx_done;
914
915 oom:
916 if (netif_msg_rx_err(ag))
917 printk(KERN_DEBUG "%s: out of memory\n", dev->name);
918
919 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
920 napi_complete(napi);
921 return 0;
922 }
923
924 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
925 {
926 struct net_device *dev = dev_id;
927 struct ag71xx *ag = netdev_priv(dev);
928 u32 status;
929
930 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
931 ag71xx_dump_intr(ag, "raw", status);
932
933 if (unlikely(!status))
934 return IRQ_NONE;
935
936 if (unlikely(status & AG71XX_INT_ERR)) {
937 if (status & AG71XX_INT_TX_BE) {
938 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
939 dev_err(&dev->dev, "TX BUS error\n");
940 }
941 if (status & AG71XX_INT_RX_BE) {
942 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
943 dev_err(&dev->dev, "RX BUS error\n");
944 }
945 }
946
947 if (likely(status & AG71XX_INT_POLL)) {
948 ag71xx_int_disable(ag, AG71XX_INT_POLL);
949 DBG("%s: enable polling mode\n", dev->name);
950 napi_schedule(&ag->napi);
951 }
952
953 ag71xx_debugfs_update_int_stats(ag, status);
954
955 return IRQ_HANDLED;
956 }
957
958 static void ag71xx_set_multicast_list(struct net_device *dev)
959 {
960 /* TODO */
961 }
962
963 #ifdef CONFIG_NET_POLL_CONTROLLER
964 /*
965 * Polling 'interrupt' - used by things like netconsole to send skbs
966 * without having to re-enable interrupts. It's not called while
967 * the interrupt routine is executing.
968 */
969 static void ag71xx_netpoll(struct net_device *dev)
970 {
971 disable_irq(dev->irq);
972 ag71xx_interrupt(dev->irq, dev);
973 enable_irq(dev->irq);
974 }
975 #endif
976
977 static const struct net_device_ops ag71xx_netdev_ops = {
978 .ndo_open = ag71xx_open,
979 .ndo_stop = ag71xx_stop,
980 .ndo_start_xmit = ag71xx_hard_start_xmit,
981 .ndo_set_multicast_list = ag71xx_set_multicast_list,
982 .ndo_do_ioctl = ag71xx_do_ioctl,
983 .ndo_tx_timeout = ag71xx_tx_timeout,
984 .ndo_change_mtu = eth_change_mtu,
985 .ndo_set_mac_address = eth_mac_addr,
986 .ndo_validate_addr = eth_validate_addr,
987 #ifdef CONFIG_NET_POLL_CONTROLLER
988 .ndo_poll_controller = ag71xx_netpoll,
989 #endif
990 };
991
992 static int __devinit ag71xx_probe(struct platform_device *pdev)
993 {
994 struct net_device *dev;
995 struct resource *res;
996 struct ag71xx *ag;
997 struct ag71xx_platform_data *pdata;
998 int err;
999
1000 pdata = pdev->dev.platform_data;
1001 if (!pdata) {
1002 dev_err(&pdev->dev, "no platform data specified\n");
1003 err = -ENXIO;
1004 goto err_out;
1005 }
1006
1007 if (pdata->mii_bus_dev == NULL) {
1008 dev_err(&pdev->dev, "no MII bus device specified\n");
1009 err = -EINVAL;
1010 goto err_out;
1011 }
1012
1013 dev = alloc_etherdev(sizeof(*ag));
1014 if (!dev) {
1015 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1016 err = -ENOMEM;
1017 goto err_out;
1018 }
1019
1020 SET_NETDEV_DEV(dev, &pdev->dev);
1021
1022 ag = netdev_priv(dev);
1023 ag->pdev = pdev;
1024 ag->dev = dev;
1025 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1026 AG71XX_DEFAULT_MSG_ENABLE);
1027 spin_lock_init(&ag->lock);
1028
1029 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1030 if (!res) {
1031 dev_err(&pdev->dev, "no mac_base resource found\n");
1032 err = -ENXIO;
1033 goto err_out;
1034 }
1035
1036 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1037 if (!ag->mac_base) {
1038 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1039 err = -ENOMEM;
1040 goto err_free_dev;
1041 }
1042
1043 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
1044 if (!res) {
1045 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
1046 err = -ENXIO;
1047 goto err_unmap_base;
1048 }
1049
1050 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
1051 if (!ag->mii_ctrl) {
1052 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
1053 err = -ENOMEM;
1054 goto err_unmap_base;
1055 }
1056
1057 dev->irq = platform_get_irq(pdev, 0);
1058 err = request_irq(dev->irq, ag71xx_interrupt,
1059 IRQF_DISABLED,
1060 dev->name, dev);
1061 if (err) {
1062 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1063 goto err_unmap_mii_ctrl;
1064 }
1065
1066 dev->base_addr = (unsigned long)ag->mac_base;
1067 dev->netdev_ops = &ag71xx_netdev_ops;
1068 dev->ethtool_ops = &ag71xx_ethtool_ops;
1069
1070 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1071
1072 init_timer(&ag->oom_timer);
1073 ag->oom_timer.data = (unsigned long) dev;
1074 ag->oom_timer.function = ag71xx_oom_timer_handler;
1075
1076 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1077 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1078
1079 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1080
1081 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1082
1083 err = register_netdev(dev);
1084 if (err) {
1085 dev_err(&pdev->dev, "unable to register net device\n");
1086 goto err_free_irq;
1087 }
1088
1089 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
1090 dev->name, dev->base_addr, dev->irq);
1091
1092 ag71xx_dump_regs(ag);
1093
1094 ag71xx_hw_init(ag);
1095
1096 ag71xx_dump_regs(ag);
1097
1098 err = ag71xx_phy_connect(ag);
1099 if (err)
1100 goto err_unregister_netdev;
1101
1102 err = ag71xx_debugfs_init(ag);
1103 if (err)
1104 goto err_phy_disconnect;
1105
1106 platform_set_drvdata(pdev, dev);
1107
1108 return 0;
1109
1110 err_phy_disconnect:
1111 ag71xx_phy_disconnect(ag);
1112 err_unregister_netdev:
1113 unregister_netdev(dev);
1114 err_free_irq:
1115 free_irq(dev->irq, dev);
1116 err_unmap_mii_ctrl:
1117 iounmap(ag->mii_ctrl);
1118 err_unmap_base:
1119 iounmap(ag->mac_base);
1120 err_free_dev:
1121 kfree(dev);
1122 err_out:
1123 platform_set_drvdata(pdev, NULL);
1124 return err;
1125 }
1126
1127 static int __devexit ag71xx_remove(struct platform_device *pdev)
1128 {
1129 struct net_device *dev = platform_get_drvdata(pdev);
1130
1131 if (dev) {
1132 struct ag71xx *ag = netdev_priv(dev);
1133
1134 ag71xx_debugfs_exit(ag);
1135 ag71xx_phy_disconnect(ag);
1136 unregister_netdev(dev);
1137 free_irq(dev->irq, dev);
1138 iounmap(ag->mii_ctrl);
1139 iounmap(ag->mac_base);
1140 kfree(dev);
1141 platform_set_drvdata(pdev, NULL);
1142 }
1143
1144 return 0;
1145 }
1146
1147 static struct platform_driver ag71xx_driver = {
1148 .probe = ag71xx_probe,
1149 .remove = __exit_p(ag71xx_remove),
1150 .driver = {
1151 .name = AG71XX_DRV_NAME,
1152 }
1153 };
1154
1155 static int __init ag71xx_module_init(void)
1156 {
1157 int ret;
1158
1159 ret = ag71xx_debugfs_root_init();
1160 if (ret)
1161 goto err_out;
1162
1163 ret = ag71xx_mdio_driver_init();
1164 if (ret)
1165 goto err_debugfs_exit;
1166
1167 ret = platform_driver_register(&ag71xx_driver);
1168 if (ret)
1169 goto err_mdio_exit;
1170
1171 return 0;
1172
1173 err_mdio_exit:
1174 ag71xx_mdio_driver_exit();
1175 err_debugfs_exit:
1176 ag71xx_debugfs_root_exit();
1177 err_out:
1178 return ret;
1179 }
1180
1181 static void __exit ag71xx_module_exit(void)
1182 {
1183 platform_driver_unregister(&ag71xx_driver);
1184 ag71xx_mdio_driver_exit();
1185 ag71xx_debugfs_root_exit();
1186 }
1187
1188 module_init(ag71xx_module_init);
1189 module_exit(ag71xx_module_exit);
1190
1191 MODULE_VERSION(AG71XX_DRV_VERSION);
1192 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1193 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1194 MODULE_LICENSE("GPL v2");
1195 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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