sync 8.09 with ar71xx changes from trunk
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_phy.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define PLL_SEC_CONFIG 0x18050004
17 #define PLL_ETH0_INT_CLOCK 0x18050010
18 #define PLL_ETH1_INT_CLOCK 0x18050014
19 #define PLL_ETH_EXT_CLOCK 0x18050018
20
21 #define ag71xx_pll_shift(_ag) (((_ag)->pdev->id) ? 19 : 17)
22 #define ag71xx_pll_offset(_ag) (((_ag)->pdev->id) ? PLL_ETH1_INT_CLOCK \
23 : PLL_ETH0_INT_CLOCK)
24
25 static void ag71xx_set_pll(struct ag71xx *ag, u32 pll_val)
26 {
27 void __iomem *pll_reg = ioremap_nocache(ag71xx_pll_offset(ag), 4);
28 void __iomem *pll_cfg = ioremap_nocache(PLL_SEC_CONFIG, 4);
29 u32 s;
30 u32 t;
31
32 s = ag71xx_pll_shift(ag);
33
34 t = __raw_readl(pll_cfg);
35 t &= ~(3 << s);
36 t |= (2 << s);
37 __raw_writel(t, pll_cfg);
38 udelay(100);
39
40 __raw_writel(pll_val, pll_reg);
41
42 t |= (3 << s);
43 __raw_writel(t, pll_cfg);
44 udelay(100);
45
46 t &= ~(3 << s);
47 __raw_writel(t, pll_cfg);
48 udelay(100);
49 DBG("%s: pll_reg %#x: %#x\n", ag->dev->name,
50 (unsigned int)pll_reg, __raw_readl(pll_reg));
51
52 iounmap(pll_cfg);
53 iounmap(pll_reg);
54 }
55
56 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
57 {
58 switch (ag->speed) {
59 case SPEED_1000:
60 return "1000";
61 case SPEED_100:
62 return "100";
63 case SPEED_10:
64 return "10";
65 }
66
67 return "?";
68 }
69
70 #if 1
71 #define PLL_VAL_1000 0x00110000
72 #define PLL_VAL_100 0x00001099
73 #define PLL_VAL_10 0x00991099
74 #else
75 #define PLL_VAL_1000 0x01111000
76 #define PLL_VAL_100 0x09991000
77 #define PLL_VAL_10 0x09991999
78 #endif
79
80 static void ag71xx_phy_link_update(struct ag71xx *ag)
81 {
82 u32 cfg2;
83 u32 ifctl;
84 u32 pll;
85 u32 fifo5;
86 u32 mii_speed;
87
88 if (!ag->link) {
89 netif_carrier_off(ag->dev);
90 if (netif_msg_link(ag))
91 printk(KERN_INFO "%s: link down\n", ag->dev->name);
92 return;
93 }
94
95 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
96 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
97 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
98
99 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
100 ifctl &= ~(MAC_IFCTL_SPEED);
101
102 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
103 fifo5 &= ~FIFO_CFG5_BYTE_PER_CLK;
104
105 switch (ag->speed) {
106 case SPEED_1000:
107 mii_speed = MII_CTRL_SPEED_1000;
108 cfg2 |= MAC_CFG2_IF_1000;
109 pll = PLL_VAL_1000;
110 fifo5 |= FIFO_CFG5_BYTE_PER_CLK;
111 break;
112 case SPEED_100:
113 mii_speed = MII_CTRL_SPEED_100;
114 cfg2 |= MAC_CFG2_IF_10_100;
115 ifctl |= MAC_IFCTL_SPEED;
116 pll = PLL_VAL_100;
117 break;
118 case SPEED_10:
119 mii_speed = MII_CTRL_SPEED_10;
120 cfg2 |= MAC_CFG2_IF_10_100;
121 pll = PLL_VAL_10;
122 break;
123 default:
124 BUG();
125 return;
126 }
127
128 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
129 ag71xx_set_pll(ag, pll);
130 ag71xx_mii_ctrl_set_speed(ag, mii_speed);
131
132 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
133 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
134 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
135
136 netif_carrier_on(ag->dev);
137 if (netif_msg_link(ag))
138 printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n",
139 ag->dev->name,
140 ag71xx_speed_str(ag),
141 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
142
143 DBG("%s: fifo1=%#x, fifo2=%#x, fifo3=%#x, fifo4=%#x, fifo5=%#x\n",
144 ag->dev->name,
145 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
146 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2),
147 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
148 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
149 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
150
151 DBG("%s: mac_cfg2=%#x, ifctl=%#x, mii_ctrl=%#x\n",
152 ag->dev->name,
153 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
154 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
155 ag71xx_mii_ctrl_rr(ag));
156 }
157
158 static void ag71xx_phy_link_adjust(struct net_device *dev)
159 {
160 struct ag71xx *ag = netdev_priv(dev);
161 struct phy_device *phydev = ag->phy_dev;
162 unsigned long flags;
163 int status_change = 0;
164
165 spin_lock_irqsave(&ag->lock, flags);
166
167 if (phydev->link) {
168 if (ag->duplex != phydev->duplex
169 || ag->speed != phydev->speed) {
170 status_change = 1;
171 }
172 }
173
174 if (phydev->link != ag->link) {
175 if (phydev->link)
176 netif_schedule(dev);
177
178 status_change = 1;
179 }
180
181 ag->link = phydev->link;
182 ag->duplex = phydev->duplex;
183 ag->speed = phydev->speed;
184
185 if (status_change)
186 ag71xx_phy_link_update(ag);
187
188 spin_unlock_irqrestore(&ag->lock, flags);
189 }
190
191 void ag71xx_phy_start(struct ag71xx *ag)
192 {
193 if (ag->phy_dev) {
194 phy_start(ag->phy_dev);
195 } else {
196 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
197
198 ag->duplex = pdata->duplex;
199 ag->speed = pdata->speed;
200 ag->link = 1;
201 ag71xx_phy_link_update(ag);
202 }
203 }
204
205 void ag71xx_phy_stop(struct ag71xx *ag)
206 {
207 if (ag->phy_dev) {
208 phy_stop(ag->phy_dev);
209 } else {
210 ag->duplex = -1;
211 ag->link = 0;
212 ag->speed = 0;
213 ag71xx_phy_link_update(ag);
214 }
215 }
216
217 int ag71xx_phy_connect(struct ag71xx *ag)
218 {
219 struct net_device *dev = ag->dev;
220 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
221 struct phy_device *phydev = NULL;
222 int phy_count = 0;
223 int phy_addr;
224
225 if (ag->mii_bus && pdata->phy_mask) {
226 /* TODO: use mutex of the mdio bus? */
227 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
228 if (!(pdata->phy_mask & (1 << phy_addr)))
229 continue;
230
231 if (ag->mii_bus->phy_map[phy_addr] == NULL)
232 continue;
233
234 DBG("%s: PHY found at %s, uid=%08x\n",
235 dev->name,
236 ag->mii_bus->phy_map[phy_addr]->dev.bus_id,
237 ag->mii_bus->phy_map[phy_addr]->phy_id);
238
239 if (phydev == NULL)
240 phydev = ag->mii_bus->phy_map[phy_addr];
241
242 phy_count++;
243 }
244 }
245
246 switch (phy_count) {
247 case 1:
248 ag->phy_dev = phy_connect(dev, phydev->dev.bus_id,
249 &ag71xx_phy_link_adjust, 0, pdata->phy_if_mode);
250
251 if (IS_ERR(ag->phy_dev)) {
252 printk(KERN_ERR "%s: could not connect to PHY at %s\n",
253 dev->name, phydev->dev.bus_id);
254 return PTR_ERR(ag->phy_dev);
255 }
256
257 /* mask with MAC supported features */
258 phydev->supported &= (SUPPORTED_10baseT_Half
259 | SUPPORTED_10baseT_Full
260 | SUPPORTED_100baseT_Half
261 | SUPPORTED_100baseT_Full
262 | SUPPORTED_Autoneg
263 | SUPPORTED_MII
264 | SUPPORTED_TP);
265
266 phydev->advertising = phydev->supported;
267
268 printk(KERN_DEBUG "%s: connected to PHY at %s "
269 "[uid=%08x, driver=%s]\n",
270 dev->name, phydev->dev.bus_id,
271 phydev->phy_id, phydev->drv->name);
272
273 ag->link = 0;
274 ag->speed = 0;
275 ag->duplex = -1;
276 break;
277
278 default:
279 ag->phy_dev = NULL;
280 printk(KERN_DEBUG "%s: connected to %d PHYs\n",
281 dev->name, phy_count);
282 break;
283 }
284
285 return 0;
286 }
287
288 void ag71xx_phy_disconnect(struct ag71xx *ag)
289 {
290 if (ag->phy_dev)
291 phy_disconnect(ag->phy_dev);
292 }