ar71xx: ag71xx remove IRQF_DISABLED
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/if_vlan.h>
29 #include <linux/phy.h>
30 #include <linux/skbuff.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/workqueue.h>
33
34 #include <linux/bitops.h>
35
36 #include <asm/mach-ath79/ar71xx_regs.h>
37 #include <asm/mach-ath79/ath79.h>
38 #include <asm/mach-ath79/ag71xx_platform.h>
39
40 #define AG71XX_DRV_NAME "ag71xx"
41 #define AG71XX_DRV_VERSION "0.5.35"
42
43 #define AG71XX_NAPI_WEIGHT 64
44 #define AG71XX_OOM_REFILL (1 + HZ/10)
45
46 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
47 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
48 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
49
50 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
51 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
52
53 #define AG71XX_TX_MTU_LEN 1540
54
55 #define AG71XX_TX_RING_SPLIT 512
56 #define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \
57 AG71XX_TX_RING_SPLIT)
58 #define AG71XX_TX_RING_SIZE_DEFAULT 48
59 #define AG71XX_RX_RING_SIZE_DEFAULT 128
60
61 #define AG71XX_TX_RING_SIZE_MAX 48
62 #define AG71XX_RX_RING_SIZE_MAX 128
63
64 #ifdef CONFIG_AG71XX_DEBUG
65 #define DBG(fmt, args...) pr_debug(fmt, ## args)
66 #else
67 #define DBG(fmt, args...) do {} while (0)
68 #endif
69
70 #define ag71xx_assert(_cond) \
71 do { \
72 if (_cond) \
73 break; \
74 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
75 BUG(); \
76 } while (0)
77
78 struct ag71xx_desc {
79 u32 data;
80 u32 ctrl;
81 #define DESC_EMPTY BIT(31)
82 #define DESC_MORE BIT(24)
83 #define DESC_PKTLEN_M 0xfff
84 u32 next;
85 u32 pad;
86 } __attribute__((aligned(4)));
87
88 struct ag71xx_buf {
89 union {
90 struct sk_buff *skb;
91 void *rx_buf;
92 };
93 union {
94 dma_addr_t dma_addr;
95 unsigned long timestamp;
96 };
97 unsigned int len;
98 };
99
100 struct ag71xx_ring {
101 struct ag71xx_buf *buf;
102 u8 *descs_cpu;
103 dma_addr_t descs_dma;
104 u16 desc_split;
105 u16 desc_size;
106 unsigned int curr;
107 unsigned int dirty;
108 unsigned int size;
109 };
110
111 struct ag71xx_mdio {
112 struct mii_bus *mii_bus;
113 int mii_irq[PHY_MAX_ADDR];
114 void __iomem *mdio_base;
115 struct ag71xx_mdio_platform_data *pdata;
116 };
117
118 struct ag71xx_int_stats {
119 unsigned long rx_pr;
120 unsigned long rx_be;
121 unsigned long rx_of;
122 unsigned long tx_ps;
123 unsigned long tx_be;
124 unsigned long tx_ur;
125 unsigned long total;
126 };
127
128 struct ag71xx_napi_stats {
129 unsigned long napi_calls;
130 unsigned long rx_count;
131 unsigned long rx_packets;
132 unsigned long rx_packets_max;
133 unsigned long tx_count;
134 unsigned long tx_packets;
135 unsigned long tx_packets_max;
136
137 unsigned long rx[AG71XX_NAPI_WEIGHT + 1];
138 unsigned long tx[AG71XX_NAPI_WEIGHT + 1];
139 };
140
141 struct ag71xx_debug {
142 struct dentry *debugfs_dir;
143
144 struct ag71xx_int_stats int_stats;
145 struct ag71xx_napi_stats napi_stats;
146 };
147
148 struct ag71xx {
149 void __iomem *mac_base;
150
151 spinlock_t lock;
152 struct platform_device *pdev;
153 struct net_device *dev;
154 struct napi_struct napi;
155 u32 msg_enable;
156
157 struct ag71xx_desc *stop_desc;
158 dma_addr_t stop_desc_dma;
159
160 struct ag71xx_ring rx_ring;
161 struct ag71xx_ring tx_ring;
162
163 struct mii_bus *mii_bus;
164 struct phy_device *phy_dev;
165 void *phy_priv;
166
167 unsigned int link;
168 unsigned int speed;
169 int duplex;
170
171 unsigned int max_frame_len;
172 unsigned int desc_pktlen_mask;
173 unsigned int rx_buf_size;
174
175 struct work_struct restart_work;
176 struct delayed_work link_work;
177 struct timer_list oom_timer;
178
179 #ifdef CONFIG_AG71XX_DEBUG_FS
180 struct ag71xx_debug debug;
181 #endif
182 };
183
184 extern struct ethtool_ops ag71xx_ethtool_ops;
185 void ag71xx_link_adjust(struct ag71xx *ag);
186
187 int ag71xx_mdio_driver_init(void) __init;
188 void ag71xx_mdio_driver_exit(void);
189
190 int ag71xx_phy_connect(struct ag71xx *ag);
191 void ag71xx_phy_disconnect(struct ag71xx *ag);
192 void ag71xx_phy_start(struct ag71xx *ag);
193 void ag71xx_phy_stop(struct ag71xx *ag);
194
195 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
196 {
197 return ag->pdev->dev.platform_data;
198 }
199
200 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
201 {
202 return (desc->ctrl & DESC_EMPTY) != 0;
203 }
204
205 static inline struct ag71xx_desc *
206 ag71xx_ring_desc(struct ag71xx_ring *ring, int idx)
207 {
208 return (struct ag71xx_desc *) &ring->descs_cpu[idx * ring->desc_size];
209 }
210
211 /* Register offsets */
212 #define AG71XX_REG_MAC_CFG1 0x0000
213 #define AG71XX_REG_MAC_CFG2 0x0004
214 #define AG71XX_REG_MAC_IPG 0x0008
215 #define AG71XX_REG_MAC_HDX 0x000c
216 #define AG71XX_REG_MAC_MFL 0x0010
217 #define AG71XX_REG_MII_CFG 0x0020
218 #define AG71XX_REG_MII_CMD 0x0024
219 #define AG71XX_REG_MII_ADDR 0x0028
220 #define AG71XX_REG_MII_CTRL 0x002c
221 #define AG71XX_REG_MII_STATUS 0x0030
222 #define AG71XX_REG_MII_IND 0x0034
223 #define AG71XX_REG_MAC_IFCTL 0x0038
224 #define AG71XX_REG_MAC_ADDR1 0x0040
225 #define AG71XX_REG_MAC_ADDR2 0x0044
226 #define AG71XX_REG_FIFO_CFG0 0x0048
227 #define AG71XX_REG_FIFO_CFG1 0x004c
228 #define AG71XX_REG_FIFO_CFG2 0x0050
229 #define AG71XX_REG_FIFO_CFG3 0x0054
230 #define AG71XX_REG_FIFO_CFG4 0x0058
231 #define AG71XX_REG_FIFO_CFG5 0x005c
232 #define AG71XX_REG_FIFO_RAM0 0x0060
233 #define AG71XX_REG_FIFO_RAM1 0x0064
234 #define AG71XX_REG_FIFO_RAM2 0x0068
235 #define AG71XX_REG_FIFO_RAM3 0x006c
236 #define AG71XX_REG_FIFO_RAM4 0x0070
237 #define AG71XX_REG_FIFO_RAM5 0x0074
238 #define AG71XX_REG_FIFO_RAM6 0x0078
239 #define AG71XX_REG_FIFO_RAM7 0x007c
240
241 #define AG71XX_REG_TX_CTRL 0x0180
242 #define AG71XX_REG_TX_DESC 0x0184
243 #define AG71XX_REG_TX_STATUS 0x0188
244 #define AG71XX_REG_RX_CTRL 0x018c
245 #define AG71XX_REG_RX_DESC 0x0190
246 #define AG71XX_REG_RX_STATUS 0x0194
247 #define AG71XX_REG_INT_ENABLE 0x0198
248 #define AG71XX_REG_INT_STATUS 0x019c
249
250 #define AG71XX_REG_FIFO_DEPTH 0x01a8
251 #define AG71XX_REG_RX_SM 0x01b0
252 #define AG71XX_REG_TX_SM 0x01b4
253
254 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
255 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
256 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
257 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
258 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
259 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
260 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
261 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
262
263 #define MAC_CFG2_FDX BIT(0)
264 #define MAC_CFG2_CRC_EN BIT(1)
265 #define MAC_CFG2_PAD_CRC_EN BIT(2)
266 #define MAC_CFG2_LEN_CHECK BIT(4)
267 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
268 #define MAC_CFG2_IF_1000 BIT(9)
269 #define MAC_CFG2_IF_10_100 BIT(8)
270
271 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
272 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
273 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
274 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
275 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
276 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
277 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
278
279 #define FIFO_CFG0_ENABLE_SHIFT 8
280
281 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
282 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
283 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
284 #define FIFO_CFG4_CE BIT(3) /* Code Error */
285 #define FIFO_CFG4_CR BIT(4) /* CRC error */
286 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
287 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
288 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
289 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
290 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
291 #define FIFO_CFG4_DR BIT(10) /* Dribble */
292 #define FIFO_CFG4_LE BIT(11) /* Long Event */
293 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
294 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
295 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
296 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
297 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
298 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
299
300 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
301 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
302 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
303 #define FIFO_CFG5_CE BIT(3) /* Code Error */
304 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
305 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
306 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
307 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
308 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
309 #define FIFO_CFG5_DR BIT(9) /* Dribble */
310 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
311 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
312 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
313 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
314 #define FIFO_CFG5_LE BIT(14) /* Long Event */
315 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
316 #define FIFO_CFG5_16 BIT(16) /* unknown */
317 #define FIFO_CFG5_17 BIT(17) /* unknown */
318 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
319 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
320
321 #define AG71XX_INT_TX_PS BIT(0)
322 #define AG71XX_INT_TX_UR BIT(1)
323 #define AG71XX_INT_TX_BE BIT(3)
324 #define AG71XX_INT_RX_PR BIT(4)
325 #define AG71XX_INT_RX_OF BIT(6)
326 #define AG71XX_INT_RX_BE BIT(7)
327
328 #define MAC_IFCTL_SPEED BIT(16)
329
330 #define MII_CFG_CLK_DIV_4 0
331 #define MII_CFG_CLK_DIV_6 2
332 #define MII_CFG_CLK_DIV_8 3
333 #define MII_CFG_CLK_DIV_10 4
334 #define MII_CFG_CLK_DIV_14 5
335 #define MII_CFG_CLK_DIV_20 6
336 #define MII_CFG_CLK_DIV_28 7
337 #define MII_CFG_CLK_DIV_34 8
338 #define MII_CFG_CLK_DIV_42 9
339 #define MII_CFG_CLK_DIV_50 10
340 #define MII_CFG_CLK_DIV_58 11
341 #define MII_CFG_CLK_DIV_66 12
342 #define MII_CFG_CLK_DIV_74 13
343 #define MII_CFG_CLK_DIV_82 14
344 #define MII_CFG_CLK_DIV_98 15
345 #define MII_CFG_RESET BIT(31)
346
347 #define MII_CMD_WRITE 0x0
348 #define MII_CMD_READ 0x1
349 #define MII_ADDR_SHIFT 8
350 #define MII_IND_BUSY BIT(0)
351 #define MII_IND_INVALID BIT(2)
352
353 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
354
355 #define TX_STATUS_PS BIT(0) /* Packet Sent */
356 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
357 #define TX_STATUS_BE BIT(3) /* Bus Error */
358
359 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
360
361 #define RX_STATUS_PR BIT(0) /* Packet Received */
362 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
363 #define RX_STATUS_BE BIT(3) /* Bus Error */
364
365 static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
366 {
367 switch (reg) {
368 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
369 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
370 case AG71XX_REG_MII_CFG:
371 break;
372
373 default:
374 BUG();
375 }
376 }
377
378 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
379 {
380 ag71xx_check_reg_offset(ag, reg);
381
382 __raw_writel(value, ag->mac_base + reg);
383 /* flush write */
384 (void) __raw_readl(ag->mac_base + reg);
385 }
386
387 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
388 {
389 ag71xx_check_reg_offset(ag, reg);
390
391 return __raw_readl(ag->mac_base + reg);
392 }
393
394 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
395 {
396 void __iomem *r;
397
398 ag71xx_check_reg_offset(ag, reg);
399
400 r = ag->mac_base + reg;
401 __raw_writel(__raw_readl(r) | mask, r);
402 /* flush write */
403 (void)__raw_readl(r);
404 }
405
406 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
407 {
408 void __iomem *r;
409
410 ag71xx_check_reg_offset(ag, reg);
411
412 r = ag->mac_base + reg;
413 __raw_writel(__raw_readl(r) & ~mask, r);
414 /* flush write */
415 (void) __raw_readl(r);
416 }
417
418 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
419 {
420 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
421 }
422
423 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
424 {
425 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
426 }
427
428 #ifdef CONFIG_AG71XX_AR8216_SUPPORT
429 void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
430 int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
431 int pktlen);
432 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
433 {
434 return ag71xx_get_pdata(ag)->has_ar8216;
435 }
436 #else
437 static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
438 struct sk_buff *skb)
439 {
440 }
441
442 static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
443 struct sk_buff *skb,
444 int pktlen)
445 {
446 return 0;
447 }
448 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
449 {
450 return 0;
451 }
452 #endif
453
454 #ifdef CONFIG_AG71XX_DEBUG_FS
455 int ag71xx_debugfs_root_init(void);
456 void ag71xx_debugfs_root_exit(void);
457 int ag71xx_debugfs_init(struct ag71xx *ag);
458 void ag71xx_debugfs_exit(struct ag71xx *ag);
459 void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
460 void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
461 #else
462 static inline int ag71xx_debugfs_root_init(void) { return 0; }
463 static inline void ag71xx_debugfs_root_exit(void) {}
464 static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
465 static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
466 static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
467 u32 status) {}
468 static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
469 int rx, int tx) {}
470 #endif /* CONFIG_AG71XX_DEBUG_FS */
471
472 void ag71xx_ar7240_start(struct ag71xx *ag);
473 void ag71xx_ar7240_stop(struct ag71xx *ag);
474 int ag71xx_ar7240_init(struct ag71xx *ag);
475 void ag71xx_ar7240_cleanup(struct ag71xx *ag);
476
477 int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg);
478 void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val);
479
480 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
481 unsigned reg_addr);
482 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
483 unsigned reg_addr, u16 reg_val);
484
485 #endif /* _AG71XX_H */