25ee7d4f14e626e31f9b1c62255ad70268173e44
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
31
32 #define AR7240_REG_MAC_ADDR0 0x20
33 #define AR7240_REG_MAC_ADDR1 0x24
34
35 #define AR7240_REG_FLOOD_MASK 0x2c
36 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
37
38 #define AR7240_REG_GLOBAL_CTRL 0x30
39 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
40
41 #define AR7240_REG_VTU 0x0040
42 #define AR7240_VTU_OP BITM(3)
43 #define AR7240_VTU_OP_NOOP 0x0
44 #define AR7240_VTU_OP_FLUSH 0x1
45 #define AR7240_VTU_OP_LOAD 0x2
46 #define AR7240_VTU_OP_PURGE 0x3
47 #define AR7240_VTU_OP_REMOVE_PORT 0x4
48 #define AR7240_VTU_ACTIVE BIT(3)
49 #define AR7240_VTU_FULL BIT(4)
50 #define AR7240_VTU_PORT BITS(8, 4)
51 #define AR7240_VTU_PORT_S 8
52 #define AR7240_VTU_VID BITS(16, 12)
53 #define AR7240_VTU_VID_S 16
54 #define AR7240_VTU_PRIO BITS(28, 3)
55 #define AR7240_VTU_PRIO_S 28
56 #define AR7240_VTU_PRIO_EN BIT(31)
57
58 #define AR7240_REG_VTU_DATA 0x0044
59 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
60 #define AR7240_VTUDATA_VALID BIT(11)
61
62 #define AR7240_REG_ATU 0x50
63 #define AR7240_ATU_FLUSH_ALL 0x1
64
65 #define AR7240_REG_AT_CTRL 0x5c
66 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
67 #define AR7240_AT_CTRL_AGE_EN BIT(17)
68 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
69 #define AR7240_AT_CTRL_RESERVED BIT(19)
70 #define AR7240_AT_CTRL_ARP_EN BIT(20)
71
72 #define AR7240_REG_TAG_PRIORITY 0x70
73
74 #define AR7240_REG_SERVICE_TAG 0x74
75 #define AR7240_SERVICE_TAG_M BITM(16)
76
77 #define AR7240_REG_CPU_PORT 0x78
78 #define AR7240_MIRROR_PORT_S 4
79 #define AR7240_CPU_PORT_EN BIT(8)
80
81 #define AR7240_REG_MIB_FUNCTION0 0x80
82 #define AR7240_MIB_TIMER_M BITM(16)
83 #define AR7240_MIB_AT_HALF_EN BIT(16)
84 #define AR7240_MIB_BUSY BIT(17)
85 #define AR7240_MIB_FUNC_S 24
86 #define AR7240_MIB_FUNC_NO_OP 0x0
87 #define AR7240_MIB_FUNC_FLUSH 0x1
88 #define AR7240_MIB_FUNC_CAPTURE 0x3
89
90 #define AR7240_REG_MDIO_CTRL 0x98
91 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
92 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
93 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
94 #define AR7240_MDIO_CTRL_CMD_WRITE 0
95 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
96 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
97 #define AR7240_MDIO_CTRL_BUSY BIT(31)
98
99 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
100
101 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
102 #define AR7240_PORT_STATUS_SPEED_S 0
103 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
104 #define AR7240_PORT_STATUS_SPEED_10 0
105 #define AR7240_PORT_STATUS_SPEED_100 1
106 #define AR7240_PORT_STATUS_SPEED_1000 2
107 #define AR7240_PORT_STATUS_TXMAC BIT(2)
108 #define AR7240_PORT_STATUS_RXMAC BIT(3)
109 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
110 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
111 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
112 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
113 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
114 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
115
116 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
117 #define AR7240_PORT_CTRL_STATE_M BITM(3)
118 #define AR7240_PORT_CTRL_STATE_DISABLED 0
119 #define AR7240_PORT_CTRL_STATE_BLOCK 1
120 #define AR7240_PORT_CTRL_STATE_LISTEN 2
121 #define AR7240_PORT_CTRL_STATE_LEARN 3
122 #define AR7240_PORT_CTRL_STATE_FORWARD 4
123 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
124 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
125 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
126 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
127 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
128 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
129 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
130 #define AR7240_PORT_CTRL_HEADER BIT(11)
131 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
132 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
133 #define AR7240_PORT_CTRL_LEARN BIT(14)
134 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
135 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
136 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
137
138 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
139
140 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
141 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
142 #define AR7240_PORT_VLAN_MODE_S 30
143 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
144 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
145 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
146 #define AR7240_PORT_VLAN_MODE_SECURE 3
147
148
149 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
150
151 #define AR7240_STATS_RXBROAD 0x00
152 #define AR7240_STATS_RXPAUSE 0x04
153 #define AR7240_STATS_RXMULTI 0x08
154 #define AR7240_STATS_RXFCSERR 0x0c
155 #define AR7240_STATS_RXALIGNERR 0x10
156 #define AR7240_STATS_RXRUNT 0x14
157 #define AR7240_STATS_RXFRAGMENT 0x18
158 #define AR7240_STATS_RX64BYTE 0x1c
159 #define AR7240_STATS_RX128BYTE 0x20
160 #define AR7240_STATS_RX256BYTE 0x24
161 #define AR7240_STATS_RX512BYTE 0x28
162 #define AR7240_STATS_RX1024BYTE 0x2c
163 #define AR7240_STATS_RX1518BYTE 0x30
164 #define AR7240_STATS_RXMAXBYTE 0x34
165 #define AR7240_STATS_RXTOOLONG 0x38
166 #define AR7240_STATS_RXGOODBYTE 0x3c
167 #define AR7240_STATS_RXBADBYTE 0x44
168 #define AR7240_STATS_RXOVERFLOW 0x4c
169 #define AR7240_STATS_FILTERED 0x50
170 #define AR7240_STATS_TXBROAD 0x54
171 #define AR7240_STATS_TXPAUSE 0x58
172 #define AR7240_STATS_TXMULTI 0x5c
173 #define AR7240_STATS_TXUNDERRUN 0x60
174 #define AR7240_STATS_TX64BYTE 0x64
175 #define AR7240_STATS_TX128BYTE 0x68
176 #define AR7240_STATS_TX256BYTE 0x6c
177 #define AR7240_STATS_TX512BYTE 0x70
178 #define AR7240_STATS_TX1024BYTE 0x74
179 #define AR7240_STATS_TX1518BYTE 0x78
180 #define AR7240_STATS_TXMAXBYTE 0x7c
181 #define AR7240_STATS_TXOVERSIZE 0x80
182 #define AR7240_STATS_TXBYTE 0x84
183 #define AR7240_STATS_TXCOLLISION 0x8c
184 #define AR7240_STATS_TXABORTCOL 0x90
185 #define AR7240_STATS_TXMULTICOL 0x94
186 #define AR7240_STATS_TXSINGLECOL 0x98
187 #define AR7240_STATS_TXEXCDEFER 0x9c
188 #define AR7240_STATS_TXDEFER 0xa0
189 #define AR7240_STATS_TXLATECOL 0xa4
190
191 #define AR7240_PORT_CPU 0
192 #define AR7240_NUM_PORTS 6
193 #define AR7240_NUM_PHYS 5
194
195 #define AR7240_PHY_ID1 0x004d
196 #define AR7240_PHY_ID2 0xd041
197
198 #define AR934X_PHY_ID1 0x004d
199 #define AR934X_PHY_ID2 0xd042
200
201 #define AR7240_MAX_VLANS 16
202
203 #define AR934X_REG_OPER_MODE0 0x04
204 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
205 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
206
207 #define AR934X_REG_OPER_MODE1 0x08
208 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
209
210 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
211
212 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
213 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
214 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
215 #define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
216 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
217 #define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
218 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
219 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
220 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
221
222 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
223 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
224 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30
225 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
226 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
227 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
228 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
229
230 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
231
232 struct ar7240sw_port_stat {
233 unsigned long rx_broadcast;
234 unsigned long rx_pause;
235 unsigned long rx_multicast;
236 unsigned long rx_fcs_error;
237 unsigned long rx_align_error;
238 unsigned long rx_runt;
239 unsigned long rx_fragments;
240 unsigned long rx_64byte;
241 unsigned long rx_128byte;
242 unsigned long rx_256byte;
243 unsigned long rx_512byte;
244 unsigned long rx_1024byte;
245 unsigned long rx_1518byte;
246 unsigned long rx_maxbyte;
247 unsigned long rx_toolong;
248 unsigned long rx_good_byte;
249 unsigned long rx_bad_byte;
250 unsigned long rx_overflow;
251 unsigned long filtered;
252
253 unsigned long tx_broadcast;
254 unsigned long tx_pause;
255 unsigned long tx_multicast;
256 unsigned long tx_underrun;
257 unsigned long tx_64byte;
258 unsigned long tx_128byte;
259 unsigned long tx_256byte;
260 unsigned long tx_512byte;
261 unsigned long tx_1024byte;
262 unsigned long tx_1518byte;
263 unsigned long tx_maxbyte;
264 unsigned long tx_oversize;
265 unsigned long tx_byte;
266 unsigned long tx_collision;
267 unsigned long tx_abortcol;
268 unsigned long tx_multicol;
269 unsigned long tx_singlecol;
270 unsigned long tx_excdefer;
271 unsigned long tx_defer;
272 unsigned long tx_xlatecol;
273 };
274
275 struct ar7240sw {
276 struct mii_bus *mii_bus;
277 struct ag71xx_switch_platform_data *swdata;
278 struct switch_dev swdev;
279 int num_ports;
280 u8 ver;
281 bool vlan;
282 u16 vlan_id[AR7240_MAX_VLANS];
283 u8 vlan_table[AR7240_MAX_VLANS];
284 u8 vlan_tagged;
285 u16 pvid[AR7240_NUM_PORTS];
286 char buf[80];
287
288 rwlock_t stats_lock;
289 struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS];
290 };
291
292 struct ar7240sw_hw_stat {
293 char string[ETH_GSTRING_LEN];
294 int sizeof_stat;
295 int reg;
296 };
297
298 static DEFINE_MUTEX(reg_mutex);
299
300 static inline int sw_is_ar7240(struct ar7240sw *as)
301 {
302 return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
303 }
304
305 static inline int sw_is_ar934x(struct ar7240sw *as)
306 {
307 return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
308 }
309
310 static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
311 {
312 return BIT(port);
313 }
314
315 static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
316 {
317 return BIT(as->swdev.ports) - 1;
318 }
319
320 static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
321 {
322 return ar7240sw_port_mask_all(as) & ~BIT(port);
323 }
324
325 static inline u16 mk_phy_addr(u32 reg)
326 {
327 return 0x17 & ((reg >> 4) | 0x10);
328 }
329
330 static inline u16 mk_phy_reg(u32 reg)
331 {
332 return (reg << 1) & 0x1e;
333 }
334
335 static inline u16 mk_high_addr(u32 reg)
336 {
337 return (reg >> 7) & 0x1ff;
338 }
339
340 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
341 {
342 unsigned long flags;
343 u16 phy_addr;
344 u16 phy_reg;
345 u32 hi, lo;
346
347 reg = (reg & 0xfffffffc) >> 2;
348 phy_addr = mk_phy_addr(reg);
349 phy_reg = mk_phy_reg(reg);
350
351 local_irq_save(flags);
352 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
353 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
354 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
355 local_irq_restore(flags);
356
357 return (hi << 16) | lo;
358 }
359
360 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
361 {
362 unsigned long flags;
363 u16 phy_addr;
364 u16 phy_reg;
365
366 reg = (reg & 0xfffffffc) >> 2;
367 phy_addr = mk_phy_addr(reg);
368 phy_reg = mk_phy_reg(reg);
369
370 local_irq_save(flags);
371 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
372 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
373 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
374 local_irq_restore(flags);
375 }
376
377 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
378 {
379 u32 ret;
380
381 mutex_lock(&reg_mutex);
382 ret = __ar7240sw_reg_read(mii, reg_addr);
383 mutex_unlock(&reg_mutex);
384
385 return ret;
386 }
387
388 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
389 {
390 mutex_lock(&reg_mutex);
391 __ar7240sw_reg_write(mii, reg_addr, reg_val);
392 mutex_unlock(&reg_mutex);
393 }
394
395 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
396 {
397 u32 t;
398
399 mutex_lock(&reg_mutex);
400 t = __ar7240sw_reg_read(mii, reg);
401 t &= ~mask;
402 t |= val;
403 __ar7240sw_reg_write(mii, reg, t);
404 mutex_unlock(&reg_mutex);
405
406 return t;
407 }
408
409 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
410 {
411 u32 t;
412
413 mutex_lock(&reg_mutex);
414 t = __ar7240sw_reg_read(mii, reg);
415 t |= val;
416 __ar7240sw_reg_write(mii, reg, t);
417 mutex_unlock(&reg_mutex);
418 }
419
420 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
421 unsigned timeout)
422 {
423 int i;
424
425 for (i = 0; i < timeout; i++) {
426 u32 t;
427
428 t = __ar7240sw_reg_read(mii, reg);
429 if ((t & mask) == val)
430 return 0;
431
432 msleep(1);
433 }
434
435 return -ETIMEDOUT;
436 }
437
438 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
439 unsigned timeout)
440 {
441 int ret;
442
443 mutex_lock(&reg_mutex);
444 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
445 mutex_unlock(&reg_mutex);
446 return ret;
447 }
448
449 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
450 unsigned reg_addr)
451 {
452 u32 t, val = 0xffff;
453 int err;
454
455 if (phy_addr >= AR7240_NUM_PHYS)
456 return 0xffff;
457
458 mutex_lock(&reg_mutex);
459 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
460 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
461 AR7240_MDIO_CTRL_MASTER_EN |
462 AR7240_MDIO_CTRL_BUSY |
463 AR7240_MDIO_CTRL_CMD_READ;
464
465 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
466 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
467 AR7240_MDIO_CTRL_BUSY, 0, 5);
468 if (!err)
469 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
470 mutex_unlock(&reg_mutex);
471
472 return val & AR7240_MDIO_CTRL_DATA_M;
473 }
474
475 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
476 unsigned reg_addr, u16 reg_val)
477 {
478 u32 t;
479 int ret;
480
481 if (phy_addr >= AR7240_NUM_PHYS)
482 return -EINVAL;
483
484 mutex_lock(&reg_mutex);
485 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
486 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
487 AR7240_MDIO_CTRL_MASTER_EN |
488 AR7240_MDIO_CTRL_BUSY |
489 AR7240_MDIO_CTRL_CMD_WRITE |
490 reg_val;
491
492 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
493 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
494 AR7240_MDIO_CTRL_BUSY, 0, 5);
495 mutex_unlock(&reg_mutex);
496
497 return ret;
498 }
499
500 static int ar7240sw_capture_stats(struct ar7240sw *as)
501 {
502 struct mii_bus *mii = as->mii_bus;
503 int port;
504 int ret;
505
506 write_lock(&as->stats_lock);
507
508 /* Capture the hardware statistics for all ports */
509 ar7240sw_reg_write(mii, AR7240_REG_MIB_FUNCTION0,
510 (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
511
512 /* Wait for the capturing to complete. */
513 ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
514 AR7240_MIB_BUSY, 0, 10);
515
516 if (ret)
517 goto unlock;
518
519 for (port = 0; port < AR7240_NUM_PORTS; port++) {
520 unsigned int base;
521 struct ar7240sw_port_stat *stats;
522
523 base = AR7240_REG_STATS_BASE(port);
524 stats = &as->port_stats[port];
525
526 #define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
527
528 stats->rx_good_byte += READ_STAT(RXGOODBYTE);
529 stats->tx_byte += READ_STAT(TXBYTE);
530
531 #undef READ_STAT
532 }
533
534 ret = 0;
535
536 unlock:
537 write_unlock(&as->stats_lock);
538 return ret;
539 }
540
541 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
542 {
543 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
544 AR7240_PORT_CTRL_STATE_DISABLED);
545 }
546
547 static void ar7240sw_setup(struct ar7240sw *as)
548 {
549 struct mii_bus *mii = as->mii_bus;
550
551 /* Enable CPU port, and disable mirror port */
552 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
553 AR7240_CPU_PORT_EN |
554 (15 << AR7240_MIRROR_PORT_S));
555
556 /* Setup TAG priority mapping */
557 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
558
559 /* Enable ARP frame acknowledge, aging, MAC replacing */
560 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
561 AR7240_AT_CTRL_RESERVED |
562 0x2b /* 5 min age time */ |
563 AR7240_AT_CTRL_AGE_EN |
564 AR7240_AT_CTRL_ARP_EN |
565 AR7240_AT_CTRL_LEARN_CHANGE);
566
567 /* Enable Broadcast frames transmitted to the CPU */
568 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
569 AR7240_FLOOD_MASK_BROAD_TO_CPU);
570
571 /* setup MTU */
572 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
573 1536);
574
575 /* setup Service TAG */
576 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
577 }
578
579 static int ar7240sw_reset(struct ar7240sw *as)
580 {
581 struct mii_bus *mii = as->mii_bus;
582 int ret;
583 int i;
584
585 /* Set all ports to disabled state. */
586 for (i = 0; i < AR7240_NUM_PORTS; i++)
587 ar7240sw_disable_port(as, i);
588
589 /* Wait for transmit queues to drain. */
590 msleep(2);
591
592 /* Reset the switch. */
593 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
594 AR7240_MASK_CTRL_SOFT_RESET);
595
596 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
597 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
598
599 ar7240sw_setup(as);
600 return ret;
601 }
602
603 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
604 {
605 struct mii_bus *mii = as->mii_bus;
606 u32 ctrl;
607 u32 vid, mode;
608
609 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
610 AR7240_PORT_CTRL_SINGLE_VLAN;
611
612 if (port == AR7240_PORT_CPU) {
613 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
614 AR7240_PORT_STATUS_SPEED_1000 |
615 AR7240_PORT_STATUS_TXFLOW |
616 AR7240_PORT_STATUS_RXFLOW |
617 AR7240_PORT_STATUS_TXMAC |
618 AR7240_PORT_STATUS_RXMAC |
619 AR7240_PORT_STATUS_DUPLEX);
620 } else {
621 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
622 AR7240_PORT_STATUS_LINK_AUTO);
623 }
624
625 /* Set the default VID for this port */
626 if (as->vlan) {
627 vid = as->vlan_id[as->pvid[port]];
628 mode = AR7240_PORT_VLAN_MODE_SECURE;
629 } else {
630 vid = port;
631 mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
632 }
633
634 if (as->vlan) {
635 if (as->vlan_tagged & BIT(port))
636 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
637 AR7240_PORT_CTRL_VLAN_MODE_S;
638 else
639 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
640 AR7240_PORT_CTRL_VLAN_MODE_S;
641 } else {
642 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_KEEP <<
643 AR7240_PORT_CTRL_VLAN_MODE_S;
644 }
645
646 if (!portmask) {
647 if (port == AR7240_PORT_CPU)
648 portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
649 else
650 portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
651 }
652
653 /* allow the port to talk to all other ports, but exclude its
654 * own ID to prevent frames from being reflected back to the
655 * port that they came from */
656 portmask &= ar7240sw_port_mask_but(as, port);
657
658 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
659 if (sw_is_ar934x(as)) {
660 u32 vlan1, vlan2;
661
662 vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
663 vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
664 (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
665 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
666 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
667 } else {
668 u32 vlan;
669
670 vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
671 (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
672
673 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
674 }
675 }
676
677 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
678 {
679 struct mii_bus *mii = as->mii_bus;
680 u32 t;
681
682 t = (addr[4] << 8) | addr[5];
683 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
684
685 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
686 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
687
688 return 0;
689 }
690
691 static int
692 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
693 struct switch_val *val)
694 {
695 struct ar7240sw *as = sw_to_ar7240(dev);
696 as->vlan_id[val->port_vlan] = val->value.i;
697 return 0;
698 }
699
700 static int
701 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
702 struct switch_val *val)
703 {
704 struct ar7240sw *as = sw_to_ar7240(dev);
705 val->value.i = as->vlan_id[val->port_vlan];
706 return 0;
707 }
708
709 static int
710 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
711 {
712 struct ar7240sw *as = sw_to_ar7240(dev);
713
714 /* make sure no invalid PVIDs get set */
715
716 if (vlan >= dev->vlans)
717 return -EINVAL;
718
719 as->pvid[port] = vlan;
720 return 0;
721 }
722
723 static int
724 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
725 {
726 struct ar7240sw *as = sw_to_ar7240(dev);
727 *vlan = as->pvid[port];
728 return 0;
729 }
730
731 static int
732 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
733 {
734 struct ar7240sw *as = sw_to_ar7240(dev);
735 u8 ports = as->vlan_table[val->port_vlan];
736 int i;
737
738 val->len = 0;
739 for (i = 0; i < as->swdev.ports; i++) {
740 struct switch_port *p;
741
742 if (!(ports & (1 << i)))
743 continue;
744
745 p = &val->value.ports[val->len++];
746 p->id = i;
747 if (as->vlan_tagged & (1 << i))
748 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
749 else
750 p->flags = 0;
751 }
752 return 0;
753 }
754
755 static int
756 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
757 {
758 struct ar7240sw *as = sw_to_ar7240(dev);
759 u8 *vt = &as->vlan_table[val->port_vlan];
760 int i, j;
761
762 *vt = 0;
763 for (i = 0; i < val->len; i++) {
764 struct switch_port *p = &val->value.ports[i];
765
766 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
767 as->vlan_tagged |= (1 << p->id);
768 else {
769 as->vlan_tagged &= ~(1 << p->id);
770 as->pvid[p->id] = val->port_vlan;
771
772 /* make sure that an untagged port does not
773 * appear in other vlans */
774 for (j = 0; j < AR7240_MAX_VLANS; j++) {
775 if (j == val->port_vlan)
776 continue;
777 as->vlan_table[j] &= ~(1 << p->id);
778 }
779 }
780
781 *vt |= 1 << p->id;
782 }
783 return 0;
784 }
785
786 static int
787 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
788 struct switch_val *val)
789 {
790 struct ar7240sw *as = sw_to_ar7240(dev);
791 as->vlan = !!val->value.i;
792 return 0;
793 }
794
795 static int
796 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
797 struct switch_val *val)
798 {
799 struct ar7240sw *as = sw_to_ar7240(dev);
800 val->value.i = as->vlan;
801 return 0;
802 }
803
804 static void
805 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
806 {
807 struct mii_bus *mii = as->mii_bus;
808
809 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
810 return;
811
812 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
813 val &= AR7240_VTUDATA_MEMBER;
814 val |= AR7240_VTUDATA_VALID;
815 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
816 }
817 op |= AR7240_VTU_ACTIVE;
818 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
819 }
820
821 static int
822 ar7240_hw_apply(struct switch_dev *dev)
823 {
824 struct ar7240sw *as = sw_to_ar7240(dev);
825 u8 portmask[AR7240_NUM_PORTS];
826 int i, j;
827
828 /* flush all vlan translation unit entries */
829 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
830
831 memset(portmask, 0, sizeof(portmask));
832 if (as->vlan) {
833 /* calculate the port destination masks and load vlans
834 * into the vlan translation unit */
835 for (j = 0; j < AR7240_MAX_VLANS; j++) {
836 u8 vp = as->vlan_table[j];
837
838 if (!vp)
839 continue;
840
841 for (i = 0; i < as->swdev.ports; i++) {
842 u8 mask = (1 << i);
843 if (vp & mask)
844 portmask[i] |= vp & ~mask;
845 }
846
847 ar7240_vtu_op(as,
848 AR7240_VTU_OP_LOAD |
849 (as->vlan_id[j] << AR7240_VTU_VID_S),
850 as->vlan_table[j]);
851 }
852 } else {
853 /* vlan disabled:
854 * isolate all ports, but connect them to the cpu port */
855 for (i = 0; i < as->swdev.ports; i++) {
856 if (i == AR7240_PORT_CPU)
857 continue;
858
859 portmask[i] = 1 << AR7240_PORT_CPU;
860 portmask[AR7240_PORT_CPU] |= (1 << i);
861 }
862 }
863
864 /* update the port destination mask registers and tag settings */
865 for (i = 0; i < as->swdev.ports; i++)
866 ar7240sw_setup_port(as, i, portmask[i]);
867
868 return 0;
869 }
870
871 static int
872 ar7240_reset_switch(struct switch_dev *dev)
873 {
874 struct ar7240sw *as = sw_to_ar7240(dev);
875 ar7240sw_reset(as);
876 return 0;
877 }
878
879 static int
880 ar7240_get_port_link(struct switch_dev *dev, int port,
881 struct switch_port_link *link)
882 {
883 struct ar7240sw *as = sw_to_ar7240(dev);
884 struct mii_bus *mii = as->mii_bus;
885 u32 status;
886
887 if (port > AR7240_NUM_PORTS)
888 return -EINVAL;
889
890 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
891 link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO);
892 if (link->aneg) {
893 link->link = !!(status & AR7240_PORT_STATUS_LINK_UP);
894 if (!link->link)
895 return 0;
896 } else {
897 link->link = true;
898 }
899
900 link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX);
901 link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW);
902 link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW);
903 switch (status & AR7240_PORT_STATUS_SPEED_M) {
904 case AR7240_PORT_STATUS_SPEED_10:
905 link->speed = SWITCH_PORT_SPEED_10;
906 break;
907 case AR7240_PORT_STATUS_SPEED_100:
908 link->speed = SWITCH_PORT_SPEED_100;
909 break;
910 case AR7240_PORT_STATUS_SPEED_1000:
911 link->speed = SWITCH_PORT_SPEED_1000;
912 break;
913 }
914
915 return 0;
916 }
917
918 static int
919 ar7240_get_port_stats(struct switch_dev *dev, int port,
920 struct switch_port_stats *stats)
921 {
922 struct ar7240sw *as = sw_to_ar7240(dev);
923
924 if (port > AR7240_NUM_PORTS)
925 return -EINVAL;
926
927 ar7240sw_capture_stats(as);
928
929 read_lock(&as->stats_lock);
930 stats->rx_bytes = as->port_stats[port].rx_good_byte;
931 stats->tx_bytes = as->port_stats[port].tx_byte;
932 read_unlock(&as->stats_lock);
933
934 return 0;
935 }
936
937 static struct switch_attr ar7240_globals[] = {
938 {
939 .type = SWITCH_TYPE_INT,
940 .name = "enable_vlan",
941 .description = "Enable VLAN mode",
942 .set = ar7240_set_vlan,
943 .get = ar7240_get_vlan,
944 .max = 1
945 },
946 };
947
948 static struct switch_attr ar7240_port[] = {
949 };
950
951 static struct switch_attr ar7240_vlan[] = {
952 {
953 .type = SWITCH_TYPE_INT,
954 .name = "vid",
955 .description = "VLAN ID",
956 .set = ar7240_set_vid,
957 .get = ar7240_get_vid,
958 .max = 4094,
959 },
960 };
961
962 static const struct switch_dev_ops ar7240_ops = {
963 .attr_global = {
964 .attr = ar7240_globals,
965 .n_attr = ARRAY_SIZE(ar7240_globals),
966 },
967 .attr_port = {
968 .attr = ar7240_port,
969 .n_attr = ARRAY_SIZE(ar7240_port),
970 },
971 .attr_vlan = {
972 .attr = ar7240_vlan,
973 .n_attr = ARRAY_SIZE(ar7240_vlan),
974 },
975 .get_port_pvid = ar7240_get_pvid,
976 .set_port_pvid = ar7240_set_pvid,
977 .get_vlan_ports = ar7240_get_ports,
978 .set_vlan_ports = ar7240_set_ports,
979 .apply_config = ar7240_hw_apply,
980 .reset_switch = ar7240_reset_switch,
981 .get_port_link = ar7240_get_port_link,
982 .get_port_stats = ar7240_get_port_stats,
983 };
984
985 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
986 {
987 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
988 struct mii_bus *mii = ag->mii_bus;
989 struct ar7240sw *as;
990 struct switch_dev *swdev;
991 u32 ctrl;
992 u16 phy_id1;
993 u16 phy_id2;
994 int i;
995
996 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
997 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
998 if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
999 (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
1000 pr_err("%s: unknown phy id '%04x:%04x'\n",
1001 ag->dev->name, phy_id1, phy_id2);
1002 return NULL;
1003 }
1004
1005 as = kzalloc(sizeof(*as), GFP_KERNEL);
1006 if (!as)
1007 return NULL;
1008
1009 as->mii_bus = mii;
1010 as->swdata = pdata->switch_data;
1011
1012 swdev = &as->swdev;
1013
1014 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
1015 as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
1016 AR7240_MASK_CTRL_VERSION_M;
1017
1018 if (sw_is_ar7240(as)) {
1019 swdev->name = "AR7240/AR9330 built-in switch";
1020 swdev->ports = AR7240_NUM_PORTS - 1;
1021 } else if (sw_is_ar934x(as)) {
1022 swdev->name = "AR934X built-in switch";
1023
1024 if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
1025 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1026 AR934X_OPER_MODE0_MAC_GMII_EN);
1027 } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
1028 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1029 AR934X_OPER_MODE0_PHY_MII_EN);
1030 } else {
1031 pr_err("%s: invalid PHY interface mode\n",
1032 ag->dev->name);
1033 goto err_free;
1034 }
1035
1036 if (as->swdata->phy4_mii_en) {
1037 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
1038 AR934X_REG_OPER_MODE1_PHY4_MII_EN);
1039 swdev->ports = AR7240_NUM_PORTS - 1;
1040 } else {
1041 swdev->ports = AR7240_NUM_PORTS;
1042 }
1043 } else {
1044 pr_err("%s: unsupported chip, ctrl=%08x\n",
1045 ag->dev->name, ctrl);
1046 goto err_free;
1047 }
1048
1049 swdev->cpu_port = AR7240_PORT_CPU;
1050 swdev->vlans = AR7240_MAX_VLANS;
1051 swdev->ops = &ar7240_ops;
1052
1053 if (register_switch(&as->swdev, ag->dev) < 0)
1054 goto err_free;
1055
1056 pr_info("%s: Found an %s\n", ag->dev->name, swdev->name);
1057
1058 /* initialize defaults */
1059 for (i = 0; i < AR7240_MAX_VLANS; i++)
1060 as->vlan_id[i] = i;
1061
1062 as->vlan_table[0] = ar7240sw_port_mask_all(as);
1063
1064 return as;
1065
1066 err_free:
1067 kfree(as);
1068 return NULL;
1069 }
1070
1071 static void link_function(struct work_struct *work) {
1072 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
1073 unsigned long flags;
1074 int i;
1075 int status = 0;
1076
1077 for (i = 0; i < 4; i++) {
1078 int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
1079 if(link & BMSR_LSTATUS) {
1080 status = 1;
1081 break;
1082 }
1083 }
1084
1085 spin_lock_irqsave(&ag->lock, flags);
1086 if(status != ag->link) {
1087 ag->link = status;
1088 ag71xx_link_adjust(ag);
1089 }
1090 spin_unlock_irqrestore(&ag->lock, flags);
1091
1092 schedule_delayed_work(&ag->link_work, HZ / 2);
1093 }
1094
1095 void ag71xx_ar7240_start(struct ag71xx *ag)
1096 {
1097 struct ar7240sw *as = ag->phy_priv;
1098
1099 ar7240sw_reset(as);
1100
1101 ag->speed = SPEED_1000;
1102 ag->duplex = 1;
1103
1104 ar7240_set_addr(as, ag->dev->dev_addr);
1105 ar7240_hw_apply(&as->swdev);
1106
1107 schedule_delayed_work(&ag->link_work, HZ / 10);
1108 }
1109
1110 void ag71xx_ar7240_stop(struct ag71xx *ag)
1111 {
1112 cancel_delayed_work_sync(&ag->link_work);
1113 }
1114
1115 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
1116 {
1117 struct ar7240sw *as;
1118
1119 as = ar7240_probe(ag);
1120 if (!as)
1121 return -ENODEV;
1122
1123 ag->phy_priv = as;
1124 ar7240sw_reset(as);
1125
1126 rwlock_init(&as->stats_lock);
1127 INIT_DELAYED_WORK(&ag->link_work, link_function);
1128
1129 return 0;
1130 }
1131
1132 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
1133 {
1134 struct ar7240sw *as = ag->phy_priv;
1135
1136 if (!as)
1137 return;
1138
1139 unregister_switch(&as->swdev);
1140 kfree(as);
1141 ag->phy_priv = NULL;
1142 }