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rtl8366_smi: use vlanmc name for all vlanconfig variables
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / phy / rtl8366_smi.c
1 /*
2 * Platform driver for the Realtek RTL8366 ethernet switch
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio.h>
18 #include <linux/spinlock.h>
19 #include <linux/skbuff.h>
20 #include <linux/switch.h>
21 #include <linux/phy.h>
22 #include <linux/rtl8366_smi.h>
23
24 /* #define DEBUG 1 */
25
26 #ifdef DEBUG
27 #include <linux/debugfs.h>
28 #endif
29
30 #define RTL8366_SMI_DRIVER_NAME "rtl8366-smi"
31 #define RTL8366_SMI_DRIVER_DESC "Realtek RTL8366 switch driver"
32 #define RTL8366_SMI_DRIVER_VER "0.1.1"
33
34 #define RTL8366S_PHY_NO_MAX 4
35 #define RTL8366S_PHY_PAGE_MAX 7
36 #define RTL8366S_PHY_ADDR_MAX 31
37
38 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
39 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
40
41 #define RTL8366_RESET_CTRL_REG 0x0100
42 #define RTL8366_CHIP_CTRL_RESET_HW 1
43 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
44
45 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
46 #define RTL8366S_CHIP_VERSION_MASK 0xf
47 #define RTL8366S_CHIP_ID_REG 0x0105
48 #define RTL8366S_CHIP_ID_8366 0x8366
49
50 /* PHY registers control */
51 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
52 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
53
54 #define RTL8366S_PHY_CTRL_READ 1
55 #define RTL8366S_PHY_CTRL_WRITE 0
56
57 #define RTL8366S_PHY_REG_MASK 0x1f
58 #define RTL8366S_PHY_PAGE_OFFSET 5
59 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
60 #define RTL8366S_PHY_NO_OFFSET 9
61 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
62
63 #define RTL8366_SMI_ACK_RETRY_COUNT 5
64 #define RTL8366_SMI_CLK_DELAY 10 /* nsec */
65
66 /* LED control registers */
67 #define RTL8366_LED_BLINKRATE_REG 0x0420
68 #define RTL8366_LED_BLINKRATE_BIT 0
69 #define RTL8366_LED_BLINKRATE_MASK 0x0007
70
71 #define RTL8366_LED_CTRL_REG 0x0421
72 #define RTL8366_LED_0_1_CTRL_REG 0x0422
73 #define RTL8366_LED_2_3_CTRL_REG 0x0423
74
75 #define RTL8366S_MIB_COUNT 33
76 #define RTL8366S_GLOBAL_MIB_COUNT 1
77 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
78 #define RTL8366S_MIB_COUNTER_BASE 0x1000
79 #define RTL8366S_MIB_CTRL_REG 0x11F0
80 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
81 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
82 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
83
84 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
85 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
86 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
87
88
89 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
92
93 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
94
95 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
96 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
97 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
98
99 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
100
101
102 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
103 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
104 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
105 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
106 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
107 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
108 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
109
110
111 #define RTL8366_PORT_NUM_CPU 5
112 #define RTL8366_NUM_PORTS 6
113 #define RTL8366_NUM_VLANS 16
114 #define RTL8366_NUM_LEDGROUPS 4
115 #define RTL8366_NUM_VIDS 4096
116 #define RTL8366S_PRIORITYMAX 7
117 #define RTL8366S_FIDMAX 7
118
119
120 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
121 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
122 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
123 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
124
125 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
126 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
127
128 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
129 RTL8366_PORT_2 | \
130 RTL8366_PORT_3 | \
131 RTL8366_PORT_4 | \
132 RTL8366_PORT_UNKNOWN | \
133 RTL8366_PORT_CPU)
134
135 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
136 RTL8366_PORT_2 | \
137 RTL8366_PORT_3 | \
138 RTL8366_PORT_4 | \
139 RTL8366_PORT_UNKNOWN)
140
141 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
142 RTL8366_PORT_2 | \
143 RTL8366_PORT_3 | \
144 RTL8366_PORT_4)
145
146 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
147 RTL8366_PORT_CPU)
148
149 struct rtl8366s_vlanconfig {
150 u16 reserved2:1;
151 u16 priority:3;
152 u16 vid:12;
153
154 u16 reserved1:1;
155 u16 fid:3;
156 u16 untag:6;
157 u16 member:6;
158 };
159
160 struct rtl8366s_vlan4kentry {
161 u16 reserved1:4;
162 u16 vid:12;
163
164 u16 reserved2:1;
165 u16 fid:3;
166 u16 untag:6;
167 u16 member:6;
168 };
169
170 static const char *MIBCOUNTERS[] = { "IfInOctets ",
171 "EtherStatsOctets ",
172 "EtherStatsUnderSizePkts ",
173 "EtherFregament ",
174 "EtherStatsPkts64Octets ",
175 "EtherStatsPkts65to127Octets ",
176 "EtherStatsPkts128to255Octets ",
177 "EtherStatsPkts256to511Octets ",
178 "EtherStatsPkts512to1023Octets ",
179 "EtherStatsPkts1024to1518Octets ",
180 "EtherOversizeStats ",
181 "EtherStatsJabbers ",
182 "IfInUcastPkts ",
183 "EtherStatsMulticastPkts ",
184 "EtherStatsBroadcastPkts ",
185 "EtherStatsDropEvents ",
186 "Dot3StatsFCSErrors ",
187 "Dot3StatsSymbolErrors ",
188 "Dot3InPauseFrames ",
189 "Dot3ControlInUnknownOpcodes ",
190 "IfOutOctets ",
191 "Dot3StatsSingleCollisionFrames ",
192 "Dot3StatMultipleCollisionFrames ",
193 "Dot3sDeferredTransmissions ",
194 "Dot3StatsLateCollisions ",
195 "EtherStatsCollisions ",
196 "Dot3StatsExcessiveCollisions ",
197 "Dot3OutPauseFrames ",
198 "Dot1dBasePortDelayExceededDiscards",
199 "Dot1dTpPortInDiscards ",
200 "IfOutUcastPkts ",
201 "IfOutMulticastPkts ",
202 "IfOutBroadcastPkts ",
203 NULL };
204
205 struct rtl8366_smi {
206 struct platform_device *pdev;
207 struct rtl8366_smi_platform_data *pdata;
208 spinlock_t lock;
209 struct mii_bus *mii_bus;
210 struct switch_dev dev;
211 int mii_irq[PHY_MAX_ADDR];
212 #ifdef DEBUG
213 struct dentry *debugfs_root;
214 #endif
215 };
216
217 #ifdef DEBUG
218 u16 g_dbg_reg;
219 #endif
220
221 #define to_rtl8366(_dev) container_of(_dev, struct rtl8366_smi, dev)
222
223 static inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi)
224 {
225 ndelay(RTL8366_SMI_CLK_DELAY);
226 }
227
228 static void rtl8366_smi_start(struct rtl8366_smi *smi)
229 {
230 unsigned int sda = smi->pdata->gpio_sda;
231 unsigned int sck = smi->pdata->gpio_sck;
232
233 /*
234 * Set GPIO pins to output mode, with initial state:
235 * SCK = 0, SDA = 1
236 */
237 gpio_direction_output(sck, 0);
238 gpio_direction_output(sda, 1);
239 rtl8366_smi_clk_delay(smi);
240
241 /* CLK 1: 0 -> 1, 1 -> 0 */
242 gpio_set_value(sck, 1);
243 rtl8366_smi_clk_delay(smi);
244 gpio_set_value(sck, 0);
245 rtl8366_smi_clk_delay(smi);
246
247 /* CLK 2: */
248 gpio_set_value(sck, 1);
249 rtl8366_smi_clk_delay(smi);
250 gpio_set_value(sda, 0);
251 rtl8366_smi_clk_delay(smi);
252 gpio_set_value(sck, 0);
253 rtl8366_smi_clk_delay(smi);
254 gpio_set_value(sda, 1);
255 }
256
257 static void rtl8366_smi_stop(struct rtl8366_smi *smi)
258 {
259 unsigned int sda = smi->pdata->gpio_sda;
260 unsigned int sck = smi->pdata->gpio_sck;
261
262 rtl8366_smi_clk_delay(smi);
263 gpio_set_value(sda, 0);
264 gpio_set_value(sck, 1);
265 rtl8366_smi_clk_delay(smi);
266 gpio_set_value(sda, 1);
267 rtl8366_smi_clk_delay(smi);
268 gpio_set_value(sck, 1);
269 rtl8366_smi_clk_delay(smi);
270 gpio_set_value(sck, 0);
271 rtl8366_smi_clk_delay(smi);
272 gpio_set_value(sck, 1);
273
274 /* add a click */
275 rtl8366_smi_clk_delay(smi);
276 gpio_set_value(sck, 0);
277 rtl8366_smi_clk_delay(smi);
278 gpio_set_value(sck, 1);
279
280 /* set GPIO pins to input mode */
281 gpio_direction_input(sda);
282 gpio_direction_input(sck);
283 }
284
285 static void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len)
286 {
287 unsigned int sda = smi->pdata->gpio_sda;
288 unsigned int sck = smi->pdata->gpio_sck;
289
290 for (; len > 0; len--) {
291 rtl8366_smi_clk_delay(smi);
292
293 /* prepare data */
294 if ( data & ( 1 << (len - 1)) )
295 gpio_set_value(sda, 1);
296 else
297 gpio_set_value(sda, 0);
298 rtl8366_smi_clk_delay(smi);
299
300 /* clocking */
301 gpio_set_value(sck, 1);
302 rtl8366_smi_clk_delay(smi);
303 gpio_set_value(sck, 0);
304 }
305 }
306
307 static void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data)
308 {
309 unsigned int sda = smi->pdata->gpio_sda;
310 unsigned int sck = smi->pdata->gpio_sck;
311
312 gpio_direction_input(sda);
313
314 for (*data = 0; len > 0; len--) {
315 u32 u;
316
317 rtl8366_smi_clk_delay(smi);
318
319 /* clocking */
320 gpio_set_value(sck, 1);
321 rtl8366_smi_clk_delay(smi);
322 u = gpio_get_value(sda);
323 gpio_set_value(sck, 0);
324
325 *data |= (u << (len - 1));
326 }
327
328 gpio_direction_output(sda, 0);
329 }
330
331 static int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi)
332 {
333 int retry_cnt;
334
335 retry_cnt = 0;
336 do {
337 u32 ack;
338
339 rtl8366_smi_read_bits(smi, 1, &ack);
340 if (ack == 0)
341 break;
342
343 if (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT)
344 return -EIO;
345 } while (1);
346
347 return 0;
348 }
349
350 static int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data)
351 {
352 rtl8366_smi_write_bits(smi, data, 8);
353 return rtl8366_smi_wait_for_ack(smi);
354 }
355
356 static int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data)
357 {
358 u32 t;
359
360 /* read data */
361 rtl8366_smi_read_bits(smi, 8, &t);
362 *data = (t & 0xff);
363
364 /* send an ACK */
365 rtl8366_smi_write_bits(smi, 0x00, 1);
366
367 return 0;
368 }
369
370 static int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data)
371 {
372 u32 t;
373
374 /* read data */
375 rtl8366_smi_read_bits(smi, 8, &t);
376 *data = (t & 0xff);
377
378 /* send an ACK */
379 rtl8366_smi_write_bits(smi, 0x01, 1);
380
381 return 0;
382 }
383
384 static int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
385 {
386 unsigned long flags;
387 u8 lo = 0;
388 u8 hi = 0;
389 int ret;
390
391 spin_lock_irqsave(&smi->lock, flags);
392
393 rtl8366_smi_start(smi);
394
395 /* send READ command */
396 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x01);
397 if (ret)
398 goto out;
399
400 /* set ADDR[7:0] */
401 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
402 if (ret)
403 goto out;
404
405 /* set ADDR[15:8] */
406 ret = rtl8366_smi_write_byte(smi, addr >> 8);
407 if (ret)
408 goto out;
409
410 /* read DATA[7:0] */
411 rtl8366_smi_read_byte0(smi, &lo);
412 /* read DATA[15:8] */
413 rtl8366_smi_read_byte1(smi, &hi);
414
415 *data = ((u32) lo) | (((u32) hi) << 8);
416
417 ret = 0;
418
419 out:
420 rtl8366_smi_stop(smi);
421 spin_unlock_irqrestore(&smi->lock, flags);
422
423 return ret;
424 }
425
426 static int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
427 {
428 unsigned long flags;
429 int ret;
430
431 spin_lock_irqsave(&smi->lock, flags);
432
433 rtl8366_smi_start(smi);
434
435 /* send WRITE command */
436 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x00);
437 if (ret)
438 goto out;
439
440 /* set ADDR[7:0] */
441 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
442 if (ret)
443 goto out;
444
445 /* set ADDR[15:8] */
446 ret = rtl8366_smi_write_byte(smi, addr >> 8);
447 if (ret)
448 goto out;
449
450 /* write DATA[7:0] */
451 ret = rtl8366_smi_write_byte(smi, data & 0xff);
452 if (ret)
453 goto out;
454
455 /* write DATA[15:8] */
456 ret = rtl8366_smi_write_byte(smi, data >> 8);
457 if (ret)
458 goto out;
459
460 ret = 0;
461
462 out:
463 rtl8366_smi_stop(smi);
464 spin_unlock_irqrestore(&smi->lock, flags);
465
466 return ret;
467 }
468
469 static int rtl8366_smi_read_phy_reg(struct rtl8366_smi *smi,
470 u32 phy_no, u32 page, u32 addr, u32 *data)
471 {
472 u32 reg;
473 int ret;
474
475 if (phy_no > RTL8366S_PHY_NO_MAX)
476 return -EINVAL;
477
478 if (page > RTL8366S_PHY_PAGE_MAX)
479 return -EINVAL;
480
481 if (addr > RTL8366S_PHY_ADDR_MAX)
482 return -EINVAL;
483
484 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
485 RTL8366S_PHY_CTRL_READ);
486 if (ret)
487 return ret;
488
489 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
490 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
491 (addr & RTL8366S_PHY_REG_MASK);
492
493 ret = rtl8366_smi_write_reg(smi, reg, 0);
494 if (ret)
495 return ret;
496
497 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
498 if (ret)
499 return ret;
500
501 return 0;
502 }
503
504 static int rtl8366_smi_write_phy_reg(struct rtl8366_smi *smi,
505 u32 phy_no, u32 page, u32 addr, u32 data)
506 {
507 u32 reg;
508 int ret;
509
510 if (phy_no > RTL8366S_PHY_NO_MAX)
511 return -EINVAL;
512
513 if (page > RTL8366S_PHY_PAGE_MAX)
514 return -EINVAL;
515
516 if (addr > RTL8366S_PHY_ADDR_MAX)
517 return -EINVAL;
518
519 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
520 RTL8366S_PHY_CTRL_WRITE);
521 if (ret)
522 return ret;
523
524 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
525 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
526 (addr & RTL8366S_PHY_REG_MASK);
527
528 ret = rtl8366_smi_write_reg(smi, reg, data);
529 if (ret)
530 return ret;
531
532 return 0;
533 }
534
535 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
536 int port, unsigned long long *val)
537 {
538 int i;
539 int err;
540 u32 addr, data, regoffset;
541 u64 mibvalue;
542
543 /* address offset to MIBs counter */
544 const u16 mibLength[RTL8366S_MIB_COUNT] = {4, 4, 2, 2, 2, 2, 2, 2, 2,
545 2, 2, 2, 2, 2, 2, 2, 2, 2,
546 2, 2, 4, 2, 2, 2, 2, 2, 2,
547 2, 2, 2, 2, 2, 2};
548
549 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
550 return -EINVAL;
551
552 i = 0;
553 regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
554
555 while (i < counter) {
556 regoffset += mibLength[i];
557 i++;
558 }
559
560 addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
561
562
563 /* writing access counter address first */
564 /* then ASIC will prepare 64bits counter wait for being retrived */
565 data = 0;/* writing data will be discard by ASIC */
566 err = rtl8366_smi_write_reg(smi, addr, data);
567 if (err)
568 return err;
569
570 /* read MIB control register */
571 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
572 if (err)
573 return err;
574
575 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
576 return -EBUSY;
577
578 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
579 return -EIO;
580
581 mibvalue = 0;
582 addr = addr + mibLength[counter] - 1;
583 i = mibLength[counter];
584
585 while (i) {
586 err = rtl8366_smi_read_reg(smi, addr, &data);
587 if (err)
588 return err;
589
590 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
591
592 addr--;
593 i--;
594 }
595
596 *val = mibvalue;
597 return 0;
598 }
599
600 static int rtl8366s_get_vlan_4k_entry(struct rtl8366_smi *smi, u32 vid,
601 struct rtl8366s_vlan4kentry *vlan4k)
602 {
603 int err;
604 u32 data;
605 u16 *tableaddr;
606
607 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
608 vlan4k->vid = vid;
609
610 if (vid >= RTL8366_NUM_VIDS)
611 return -EINVAL;
612
613 tableaddr = (u16 *)vlan4k;
614
615 /* write VID */
616 data = *tableaddr;
617 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
618 if (err)
619 return err;
620
621 /* write table access control word */
622 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
623 RTL8366S_TABLE_VLAN_READ_CTRL);
624 if (err)
625 return err;
626
627 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
628 if (err)
629 return err;
630
631 *tableaddr = data;
632 tableaddr++;
633
634 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
635 &data);
636 if (err)
637 return err;
638
639 *tableaddr = data;
640 vlan4k->vid = vid;
641
642 return 0;
643 }
644
645 static int rtl8366s_set_vlan_4k_entry(struct rtl8366_smi *smi,
646 const struct rtl8366s_vlan4kentry *vlan4k)
647 {
648 int err;
649 u32 data;
650 u16 *tableaddr;
651
652 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
653 vlan4k->member > RTL8366_PORT_ALL ||
654 vlan4k->untag > RTL8366_PORT_ALL ||
655 vlan4k->fid > RTL8366S_FIDMAX)
656 return -EINVAL;
657
658 tableaddr = (u16 *)vlan4k;
659
660 data = *tableaddr;
661
662 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
663 if (err)
664 return err;
665
666 tableaddr++;
667
668 data = *tableaddr;
669
670 rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1, data);
671
672
673 /* write table access control word */
674 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
675 RTL8366S_TABLE_VLAN_WRITE_CTRL);
676 if (err)
677 return err;
678
679 return 0;
680 }
681
682 static int rtl8366s_get_vlan_member_config(struct rtl8366_smi *smi, u32 index,
683 struct rtl8366s_vlanconfig *vlanmc)
684 {
685 int err;
686 u32 addr;
687 u32 data;
688 u16 *tableaddr;
689
690 memset(vlanmc, '\0', sizeof(struct rtl8366s_vlanconfig));
691
692 if (index >= RTL8366_NUM_VLANS)
693 return -EINVAL;
694
695 tableaddr = (u16 *)vlanmc;
696
697 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
698
699 err = rtl8366_smi_read_reg(smi, addr, &data);
700 if (err)
701 return err;
702
703 *tableaddr = data;
704 tableaddr++;
705
706 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
707
708 err = rtl8366_smi_read_reg(smi, addr, &data);
709 if (err)
710 return err;
711
712 *tableaddr = data;
713
714 return 0;
715 }
716
717 static int rtl8366s_set_vlan_member_config(struct rtl8366_smi *smi, u32 index,
718 const struct rtl8366s_vlanconfig
719 *vlanmc)
720 {
721 int err;
722 u32 addr;
723 u32 data;
724 u16 *tableaddr;
725
726 if (index >= RTL8366_NUM_VLANS ||
727 vlanmc->vid >= RTL8366_NUM_VIDS ||
728 vlanmc->priority > RTL8366S_PRIORITYMAX ||
729 vlanmc->member > RTL8366_PORT_ALL ||
730 vlanmc->untag > RTL8366_PORT_ALL ||
731 vlanmc->fid > RTL8366S_FIDMAX)
732 return -EINVAL;
733
734 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
735
736
737 tableaddr = (u16 *)vlanmc;
738 data = *tableaddr;
739
740 err = rtl8366_smi_write_reg(smi, addr, data);
741 if (err)
742 return err;
743
744 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
745
746 tableaddr++;
747 data = *tableaddr;
748
749 err = rtl8366_smi_write_reg(smi, addr, data);
750 if (err)
751 return err;
752
753 return 0;
754 }
755
756 static int rtl8366_get_port_vlan_index(struct rtl8366_smi *smi, int port,
757 int *val)
758 {
759 int err;
760 u32 addr;
761 u32 data;
762
763 /* bits mapping to port vlan control register of port n */
764 const u16 bits[RTL8366_NUM_PORTS] = { 0x000F, 0x00F0, 0x0F00,
765 0xF000, 0x000F, 0x00F0 };
766 /* bits offset to port vlan control register of port n */
767 const u16 bitoffset[RTL8366_NUM_PORTS] = { 0, 4, 8, 12, 0, 4 };
768 /* address offset to port vlan control register of port n */
769 const u16 addroffset[RTL8366_NUM_PORTS] = { 0, 0, 0, 0, 1, 1 };
770
771 if (port >= RTL8366_NUM_PORTS)
772 return -EINVAL;
773
774 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addroffset[port];
775
776 err = rtl8366_smi_read_reg(smi, addr, &data);
777 if (err)
778 return err;
779
780 *val = (data & bits[port]) >> bitoffset[port];
781
782 return 0;
783
784 }
785
786 static int rtl8366_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
787 int *val)
788 {
789 int err;
790 int index;
791 struct rtl8366s_vlanconfig vlanmc;
792
793 err = rtl8366_get_port_vlan_index(smi, port, &index);
794 if (err)
795 return err;
796
797 err = rtl8366s_get_vlan_member_config(smi, index, &vlanmc);
798 if (err)
799 return err;
800
801 *val = vlanmc.vid;
802 return 0;
803 }
804
805 static int rtl8366_set_port_vlan_index(struct rtl8366_smi *smi, int port,
806 int index)
807 {
808 int err;
809 u32 addr;
810 u32 data;
811 u32 vlan_data;
812 u32 bits;
813
814 /* bits mapping to port vlan control register of port n */
815 const u16 bitmasks[6] = { 0x000F, 0x00F0, 0x0F00,
816 0xF000, 0x000F, 0x00F0 };
817 /* bits offset to port vlan control register of port n */
818 const u16 bitOff[6] = { 0, 4, 8, 12, 0, 4 };
819 /* address offset to port vlan control register of port n */
820 const u16 addrOff[6] = { 0, 0, 0, 0, 1, 1 };
821
822 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
823 return -EINVAL;
824
825 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addrOff[port];
826
827 bits = bitmasks[port];
828
829 data = (index << bitOff[port]) & bits;
830
831 err = rtl8366_smi_read_reg(smi, addr, &vlan_data);
832 if (err)
833 return err;
834
835 vlan_data &= ~(vlan_data & bits);
836 vlan_data |= data;
837
838 err = rtl8366_smi_write_reg(smi, addr, vlan_data);
839 if (err)
840 return err;
841
842 return 0;
843 }
844
845 static int rtl8366_set_vlan_port_pvid(struct rtl8366_smi *smi, int port,
846 int val)
847 {
848 int i;
849 struct rtl8366s_vlanconfig vlanmc;
850 struct rtl8366s_vlan4kentry vlan4k;
851
852 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
853 return -EINVAL;
854
855
856
857 /* Updating the 4K entry; lookup it and change the port member set */
858 rtl8366s_get_vlan_4k_entry(smi, val, &vlan4k);
859 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
860 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
861 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
862
863 /* For the 16 entries more work needs to be done. First see if such
864 VID is already there and change it */
865 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
866 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
867
868 /* Try to find an existing vid and update port member set */
869 if (val == vlanmc.vid) {
870 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
871 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
872
873 /* Now update PVID register settings */
874 rtl8366_set_port_vlan_index(smi, port, i);
875
876 return 0;
877 }
878 }
879
880 /* PVID could not be found from vlan table. Replace unused (one that
881 has no member ports) with new one */
882 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
883 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
884
885 /* See if this vlan member configuration is unused. It is
886 unused if member set contains no ports or CPU port only */
887 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
888 vlanmc.vid = val;
889 vlanmc.priority = 0;
890 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
891 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
892 vlanmc.fid = 0;
893
894 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
895
896 /* Now update PVID register settings */
897 rtl8366_set_port_vlan_index(smi, port, i);
898
899 return 0;
900 }
901 }
902
903 dev_err(&smi->pdev->dev, "All 16 vlan member configurations are in "
904 "use\n");
905 return -EINVAL;
906 }
907
908
909 static int rtl8366_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
910 {
911 u32 data = 0;
912 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
913
914 data &= ~(data & RTL8366_CHIP_CTRL_VLAN);
915 if (enable)
916 data |= RTL8366_CHIP_CTRL_VLAN;
917
918 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
919 }
920
921 static int rtl8366_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
922 {
923 u32 data = 0;
924 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
925
926 data &= ~(data & 1);
927 if (enable)
928 data |= 1;
929
930 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
931 }
932
933 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
934 {
935 int i;
936 struct rtl8366s_vlan4kentry vlan4k;
937 struct rtl8366s_vlanconfig vlanmc;
938
939 /* clear 16 VLAN member configuration */
940 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
941 vlanmc.vid = 0;
942 vlanmc.priority = 0;
943 vlanmc.member = 0;
944 vlanmc.untag = 0;
945 vlanmc.fid = 0;
946 if (rtl8366s_set_vlan_member_config(smi, i, &vlanmc) != 0)
947 return -EIO;
948 }
949
950 /* Set a default VLAN with vid 1 to 4K table for all ports */
951 vlan4k.vid = 1;
952 vlan4k.member = RTL8366_PORT_ALL;
953 vlan4k.untag = RTL8366_PORT_ALL;
954 vlan4k.fid = 0;
955 if (rtl8366s_set_vlan_4k_entry(smi, &vlan4k) != 0)
956 return -EIO;
957
958 /* Set all ports PVID to default VLAN */
959 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
960 if (rtl8366_set_vlan_port_pvid(smi, i, 0) != 0)
961 return -EIO;
962 }
963
964 return 0;
965 }
966
967 #ifdef DEBUG
968 static int rtl8366_debugfs_open(struct inode *inode, struct file *file)
969 {
970 file->private_data = inode->i_private;
971 return 0;
972 }
973
974 static ssize_t rtl8366_read_debugfs_mibs(struct file *file,
975 char __user *user_buf,
976 size_t count, loff_t *ppos)
977 {
978 char buf[4096];
979 int i, j, len = 0;
980 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
981
982 len += snprintf(buf + len, sizeof(buf) - len, "MIB Counters:\n");
983 len += snprintf(buf + len, sizeof(buf) - len, "Counter"
984 " "
985 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
986 "Port 4\n");
987
988 for (i = 0; i < 33; ++i) {
989
990 len += snprintf(buf + len, sizeof(buf) - len, "%d:%s ",
991 i, MIBCOUNTERS[i]);
992 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
993 unsigned long long counter = 0;
994
995 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
996 len += snprintf(buf + len, sizeof(buf) - len,
997 "[%llu]", counter);
998 else
999 len += snprintf(buf + len, sizeof(buf) - len,
1000 "[error]");
1001
1002 if (j != RTL8366_NUM_PORTS - 1) {
1003 if (counter < 100000)
1004 len += snprintf(buf + len,
1005 sizeof(buf) - len,
1006 "\t");
1007
1008 len += snprintf(buf + len, sizeof(buf) - len,
1009 "\t");
1010 }
1011 }
1012 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1013 }
1014
1015 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1016
1017 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1018 }
1019
1020 static ssize_t rtl8366_read_debugfs_vlan(struct file *file,
1021 char __user *user_buf,
1022 size_t count, loff_t *ppos)
1023 {
1024 char buf[4096];
1025 int i, j, len = 0;
1026 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1027
1028 len += snprintf(buf + len, sizeof(buf) - len, "VLAN Member Config:\n");
1029 len += snprintf(buf + len, sizeof(buf) - len,
1030 "\t id \t vid \t prio \t member \t untag \t fid "
1031 "\tports\n");
1032
1033 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
1034 struct rtl8366s_vlanconfig vlanmc;
1035
1036 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
1037
1038 len += snprintf(buf + len, sizeof(buf) - len,
1039 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
1040 "\t", i, vlanmc.vid, vlanmc.priority,
1041 vlanmc.member, vlanmc.untag, vlanmc.fid);
1042
1043 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1044 int index = 0;
1045 if (!rtl8366_get_port_vlan_index(smi, j, &index)) {
1046 if (index == i)
1047 len += snprintf(buf + len,
1048 sizeof(buf) - len,
1049 "%d", j);
1050 }
1051 }
1052 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1053 }
1054
1055 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1056 }
1057
1058 static ssize_t rtl8366_read_debugfs_reg(struct file *file,
1059 char __user *user_buf,
1060 size_t count, loff_t *ppos)
1061 {
1062 u32 t, reg = g_dbg_reg;
1063 int err, len = 0;
1064 char buf[512];
1065 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1066
1067 memset(buf, '\0', sizeof(buf));
1068
1069 err = rtl8366_smi_read_reg(smi, reg, &t);
1070 if (err) {
1071 len += snprintf(buf, sizeof(buf),
1072 "Read failed (reg: 0x%04x)\n", reg);
1073 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1074 }
1075
1076 len += snprintf(buf, sizeof(buf), "reg = 0x%04x, val = 0x%04x\n",
1077 reg, t);
1078
1079 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1080 }
1081
1082 static ssize_t rtl8366_write_debugfs_reg(struct file *file,
1083 const char __user *user_buf,
1084 size_t count, loff_t *ppos)
1085 {
1086 unsigned long data;
1087 u32 reg = g_dbg_reg;
1088 int err;
1089 char buf[50];
1090 size_t len;
1091 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1092
1093 len = min(count, sizeof(buf) - 1);
1094 if (copy_from_user(buf, user_buf, len)) {
1095 dev_err(&smi->pdev->dev, "copy from user failed\n");
1096 return -EFAULT;
1097 }
1098
1099 buf[len] = '\0';
1100 if (len > 0 && buf[len - 1] == '\n')
1101 buf[len - 1] = '\0';
1102
1103
1104 if (strict_strtoul(buf, 16, &data)) {
1105 dev_err(&smi->pdev->dev, "Invalid reg value %s\n", buf);
1106 } else {
1107 err = rtl8366_smi_write_reg(smi, reg, data);
1108 if (err) {
1109 dev_err(&smi->pdev->dev,
1110 "writing reg 0x%04x val 0x%04lx failed\n",
1111 reg, data);
1112 }
1113 }
1114
1115 return count;
1116 }
1117
1118 static const struct file_operations fops_rtl8366_regs = {
1119 .read = rtl8366_read_debugfs_reg,
1120 .write = rtl8366_write_debugfs_reg,
1121 .open = rtl8366_debugfs_open,
1122 .owner = THIS_MODULE
1123 };
1124
1125 static const struct file_operations fops_rtl8366_vlan = {
1126 .read = rtl8366_read_debugfs_vlan,
1127 .open = rtl8366_debugfs_open,
1128 .owner = THIS_MODULE
1129 };
1130
1131 static const struct file_operations fops_rtl8366_mibs = {
1132 .read = rtl8366_read_debugfs_mibs,
1133 .open = rtl8366_debugfs_open,
1134 .owner = THIS_MODULE
1135 };
1136
1137 static void rtl8366_debugfs_init(struct rtl8366_smi *smi)
1138 {
1139 struct dentry *node;
1140 struct dentry *root;
1141
1142 if (!smi->debugfs_root)
1143 smi->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
1144
1145 if (!smi->debugfs_root) {
1146 dev_err(&smi->pdev->dev, "Unable to create debugfs dir\n");
1147 return;
1148 }
1149 root = smi->debugfs_root;
1150
1151 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
1152 if (!node) {
1153 dev_err(&smi->pdev->dev, "Creating debugfs file reg failed\n");
1154 return;
1155 }
1156
1157 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, smi,
1158 &fops_rtl8366_regs);
1159 if (!node) {
1160 dev_err(&smi->pdev->dev, "Creating debugfs file val failed\n");
1161 return;
1162 }
1163
1164 node = debugfs_create_file("vlan", S_IRUSR, root, smi,
1165 &fops_rtl8366_vlan);
1166 if (!node) {
1167 dev_err(&smi->pdev->dev, "Creating debugfs file vlan "
1168 "failed\n");
1169 return;
1170 }
1171
1172 node = debugfs_create_file("mibs", S_IRUSR, root, smi,
1173 &fops_rtl8366_mibs);
1174 if (!node) {
1175 dev_err(&smi->pdev->dev, "Creating debugfs file mibs "
1176 "xfailed\n");
1177 return;
1178 }
1179 }
1180
1181 static void rtl8366_debugfs_remove(struct rtl8366_smi *smi)
1182 {
1183 if (smi->debugfs_root) {
1184 debugfs_remove_recursive(smi->debugfs_root);
1185 smi->debugfs_root = NULL;
1186 }
1187 }
1188
1189 #else
1190 static inline void rtl8366_debugfs_init(struct rtl8366_smi *smi) {}
1191 static inline void rtl8366_debugfs_remove(struct rtl8366_smi *smi) {}
1192 #endif
1193
1194 static int rtl8366_global_reset_mibs(struct switch_dev *dev,
1195 const struct switch_attr *attr,
1196 struct switch_val *val)
1197 {
1198 u32 data = 0;
1199 struct rtl8366_smi *smi = to_rtl8366(dev);
1200
1201 if (val->value.i == 1) {
1202 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1203 data |= (1 << 2);
1204 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1205 }
1206
1207 return 0;
1208 }
1209
1210 static int rtl8366_get_vlan(struct switch_dev *dev,
1211 const struct switch_attr *attr,
1212 struct switch_val *val)
1213 {
1214 u32 data;
1215 struct rtl8366_smi *smi = to_rtl8366(dev);
1216
1217 if (attr->ofs == 1) {
1218 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1219
1220 if (data & RTL8366_CHIP_CTRL_VLAN)
1221 val->value.i = 1;
1222 else
1223 val->value.i = 0;
1224 } else if (attr->ofs == 2) {
1225 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1226
1227 if (data & 0x0001)
1228 val->value.i = 1;
1229 else
1230 val->value.i = 0;
1231 }
1232
1233 return 0;
1234 }
1235
1236 static int rtl8366_global_get_blinkrate(struct switch_dev *dev,
1237 const struct switch_attr *attr,
1238 struct switch_val *val)
1239 {
1240 u32 data;
1241 struct rtl8366_smi *smi = to_rtl8366(dev);
1242 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1243
1244 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1245
1246 return 0;
1247 }
1248
1249 static int rtl8366_global_set_blinkrate(struct switch_dev *dev,
1250 const struct switch_attr *attr,
1251 struct switch_val *val)
1252 {
1253 u32 data;
1254 struct rtl8366_smi *smi = to_rtl8366(dev);
1255
1256 if (val->value.i >= 6)
1257 return -EINVAL;
1258
1259 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1260
1261 data &= ~(data & RTL8366_LED_BLINKRATE_MASK);
1262 data |= val->value.i;
1263
1264 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1265
1266 return 0;
1267 }
1268
1269 static int rtl8366_set_vlan(struct switch_dev *dev,
1270 const struct switch_attr *attr,
1271 struct switch_val *val)
1272 {
1273 struct rtl8366_smi *smi = to_rtl8366(dev);
1274
1275 if (attr->ofs == 1)
1276 return rtl8366_vlan_set_vlan(smi, val->value.i);
1277 else
1278 return rtl8366_vlan_set_4ktable(smi, val->value.i);
1279 }
1280
1281 static int rtl8366_init_vlan(struct switch_dev *dev,
1282 const struct switch_attr *attr,
1283 struct switch_val *val)
1284 {
1285 struct rtl8366_smi *smi = to_rtl8366(dev);
1286 return rtl8366s_reset_vlan(smi);
1287 }
1288
1289 static int rtl8366_attr_get_port_link(struct switch_dev *dev,
1290 const struct switch_attr *attr,
1291 struct switch_val *val)
1292 {
1293 char buf[1024];
1294 u32 len = 0, data = 0;
1295 int speed, duplex, link, txpause, rxpause, nway;
1296 struct rtl8366_smi *smi = to_rtl8366(dev);
1297
1298 if (val->port_vlan >= RTL8366_NUM_PORTS)
1299 return -EINVAL;
1300
1301 memset(buf, '\0', sizeof(buf));
1302 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1303 (val->port_vlan >> 1),
1304 &data);
1305
1306 if (val->port_vlan & 0x1)
1307 data = data >> 8;
1308
1309 speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
1310 duplex = (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) >> 2;
1311 link = (data & RTL8366S_PORT_STATUS_LINK_MASK) >> 4;
1312 txpause = (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) >> 5;
1313 rxpause = (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) >> 6;
1314 nway = (data & RTL8366S_PORT_STATUS_AN_MASK) >> 7;
1315
1316 len += snprintf(buf + len, sizeof(buf) - len, "Port %d: ",
1317 val->port_vlan);
1318
1319 if (link)
1320 len += snprintf(buf + len, sizeof(buf) - len,
1321 "Link UP, Speed: ");
1322 else
1323 len += snprintf(buf + len, sizeof(buf) - len,
1324 "Link DOWN, Speed: ");
1325
1326 if (speed == 0)
1327 len += snprintf(buf + len, sizeof(buf) - len, "10Base-TX ");
1328 else if (speed == 1)
1329 len += snprintf(buf + len, sizeof(buf) - len, "100Base-TX ");
1330 else if (speed == 2)
1331 len += snprintf(buf + len, sizeof(buf) - len, "1000Base-TX ");
1332
1333 if (duplex)
1334 len += snprintf(buf + len, sizeof(buf) - len, "Full-Duplex, ");
1335 else
1336 len += snprintf(buf + len, sizeof(buf) - len, "Half-Duplex, ");
1337
1338 if (txpause)
1339 len += snprintf(buf + len, sizeof(buf) - len, "TX-Pause ");
1340 if (rxpause)
1341 len += snprintf(buf + len, sizeof(buf) - len, "RX-Pause ");
1342 if (nway)
1343 len += snprintf(buf + len, sizeof(buf) - len, "nway ");
1344
1345 val->value.s = buf;
1346 val->len = len;
1347
1348 return 0;
1349 }
1350
1351 static int rtl8366_attr_get_vlan_info(struct switch_dev *dev,
1352 const struct switch_attr *attr,
1353 struct switch_val *val)
1354 {
1355 int i;
1356 char buf[1024];
1357 u32 len = 0;
1358 struct rtl8366s_vlanconfig vlanmc;
1359 struct rtl8366s_vlan4kentry vlan4k;
1360 struct rtl8366_smi *smi = to_rtl8366(dev);
1361
1362 if (val->port_vlan >= RTL8366_NUM_PORTS)
1363 return -EINVAL;
1364
1365 memset(buf, '\0', sizeof(buf));
1366
1367 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1368 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1369
1370 len += snprintf(buf + len, sizeof(buf) - len, "VLAN %d: Ports: ",
1371 val->port_vlan);
1372
1373 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1374 int index = 0;
1375 if (!rtl8366_get_port_vlan_index(smi, i, &index) &&
1376 index == val->port_vlan)
1377 len += snprintf(buf + len, sizeof(buf) - len, "%d", i);
1378 }
1379 len += snprintf(buf + len, sizeof(buf) - len, "\n");
1380
1381 len += snprintf(buf + len, sizeof(buf) - len,
1382 "\t\t vid \t prio \t member \t untag \t fid\n");
1383 len += snprintf(buf + len, sizeof(buf) - len, "\tMC:\t");
1384 len += snprintf(buf + len, sizeof(buf) - len,
1385 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1386 vlanmc.vid, vlanmc.priority, vlanmc.member,
1387 vlanmc.untag, vlanmc.fid);
1388 len += snprintf(buf + len, sizeof(buf) - len, "\t4K:\t");
1389 len += snprintf(buf + len, sizeof(buf) - len,
1390 "%d \t \t 0x%04x \t 0x%04x \t %d",
1391 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1392
1393 val->value.s = buf;
1394 val->len = len;
1395
1396 return 0;
1397 }
1398
1399 static int rtl8366_set_port_led(struct switch_dev *dev,
1400 const struct switch_attr *attr,
1401 struct switch_val *val)
1402 {
1403 u32 data = 0;
1404 struct rtl8366_smi *smi = to_rtl8366(dev);
1405 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1406 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1407 return -EINVAL;
1408
1409 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1410 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1411 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1412 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1413 } else {
1414 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1415 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1416 (val->value.i << (val->port_vlan * 4));
1417 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1418 }
1419
1420 return 0;
1421 }
1422
1423 static int rtl8366_get_port_led(struct switch_dev *dev,
1424 const struct switch_attr *attr,
1425 struct switch_val *val)
1426 {
1427 u32 data = 0;
1428 struct rtl8366_smi *smi = to_rtl8366(dev);
1429 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1430 return -EINVAL;
1431
1432 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1433 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1434
1435 return 0;
1436 }
1437
1438 static int rtl8366_reset_port_mibs(struct switch_dev *dev,
1439 const struct switch_attr *attr,
1440 struct switch_val *val)
1441 {
1442 u32 data = 0;
1443 struct rtl8366_smi *smi = to_rtl8366(dev);
1444 if (val->port_vlan >= RTL8366_NUM_PORTS)
1445 return -EINVAL;
1446
1447 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1448 data |= (1 << (val->port_vlan + 3));
1449 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1450
1451 return 0;
1452 }
1453
1454 static int rtl8366_get_port_mib(struct switch_dev *dev,
1455 const struct switch_attr *attr,
1456 struct switch_val *val)
1457 {
1458 char buf[2048];
1459 int i, len = 0;
1460 unsigned long long counter = 0;
1461 struct rtl8366_smi *smi = to_rtl8366(dev);
1462 if (val->port_vlan >= RTL8366_NUM_PORTS)
1463 return -EINVAL;
1464
1465 len += snprintf(buf + len, sizeof(buf) - len, "Port %d MIB counters\n",
1466 val->port_vlan);
1467 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1468
1469 len += snprintf(buf + len, sizeof(buf) - len,
1470 "%d:%s\t", i, MIBCOUNTERS[i]);
1471 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1472 len += snprintf(buf + len, sizeof(buf) - len,
1473 "[%llu]\n", counter);
1474 else
1475 len += snprintf(buf + len, sizeof(buf) - len,
1476 "[error]\n");
1477 }
1478
1479 val->value.s = buf;
1480 val->len = len;
1481 return 0;
1482 }
1483
1484 static int rtl8366_set_member(struct switch_dev *dev,
1485 const struct switch_attr *attr,
1486 struct switch_val *val)
1487 {
1488 struct rtl8366s_vlanconfig vlanmc;
1489 struct rtl8366s_vlan4kentry vlan4k;
1490 struct rtl8366_smi *smi = to_rtl8366(dev);
1491
1492 if (val->port_vlan >= RTL8366_NUM_VLANS)
1493 return -EINVAL;
1494
1495 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1496
1497 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1498
1499 vlan4k.member = vlanmc.member = val->value.i;
1500 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanmc);
1501 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
1502
1503 return 0;
1504 }
1505
1506 static int rtl8366_get_member(struct switch_dev *dev,
1507 const struct switch_attr *attr,
1508 struct switch_val *val)
1509 {
1510 struct rtl8366s_vlanconfig vlanmc;
1511 struct rtl8366s_vlan4kentry vlan4k;
1512 struct rtl8366_smi *smi = to_rtl8366(dev);
1513
1514 if (val->port_vlan >= RTL8366_NUM_VLANS)
1515 return -EINVAL;
1516
1517 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1518
1519 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1520
1521 val->value.i = vlanmc.member;
1522
1523 return 0;
1524 }
1525
1526 static int rtl8366_set_untag(struct switch_dev *dev,
1527 const struct switch_attr *attr,
1528 struct switch_val *val)
1529 {
1530 struct rtl8366s_vlanconfig vlanmc;
1531 struct rtl8366s_vlan4kentry vlan4k;
1532 struct rtl8366_smi *smi = to_rtl8366(dev);
1533
1534 if (val->port_vlan >= RTL8366_NUM_VLANS)
1535 return -EINVAL;
1536
1537 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1538 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1539
1540 vlan4k.untag = vlanmc.untag = val->value.i;
1541 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanmc);
1542 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
1543
1544 return 0;
1545 }
1546
1547 static int rtl8366_get_untag(struct switch_dev *dev,
1548 const struct switch_attr *attr,
1549 struct switch_val *val)
1550 {
1551 struct rtl8366s_vlanconfig vlanmc;
1552 struct rtl8366s_vlan4kentry vlan4k;
1553 struct rtl8366_smi *smi = to_rtl8366(dev);
1554
1555 if (val->port_vlan >= RTL8366_NUM_VLANS)
1556 return -EINVAL;
1557
1558 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1559 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1560
1561
1562 val->value.i = vlanmc.untag;
1563
1564 return 0;
1565 }
1566
1567 static int rtl8366_get_port_pvid(struct switch_dev *dev, int port, int *val)
1568 {
1569 struct rtl8366_smi *smi = to_rtl8366(dev);
1570 return rtl8366_get_vlan_port_pvid(smi, port, val);
1571 }
1572
1573 static int rtl8366_set_port_pvid(struct switch_dev *dev, int port, int val)
1574 {
1575 struct rtl8366_smi *smi = to_rtl8366(dev);
1576 return rtl8366_set_vlan_port_pvid(smi, port, val);
1577 }
1578
1579 static int rtl8366_reset_switch(struct switch_dev *dev)
1580 {
1581 struct rtl8366_smi *smi = to_rtl8366(dev);
1582 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
1583 RTL8366_CHIP_CTRL_RESET_HW);
1584 return 0;
1585 }
1586
1587 static struct switch_attr rtl8366_globals[] = {
1588 {
1589 .type = SWITCH_TYPE_INT,
1590 .name = "enable_vlan",
1591 .description = "Enable VLAN mode",
1592 .set = rtl8366_set_vlan,
1593 .get = rtl8366_get_vlan,
1594 .max = 1,
1595 .ofs = 1
1596 },
1597 {
1598 .type = SWITCH_TYPE_INT,
1599 .name = "enable_vlan4k",
1600 .description = "Enable VLAN 4K mode",
1601 .set = rtl8366_set_vlan,
1602 .get = rtl8366_get_vlan,
1603 .max = 1,
1604 .ofs = 2
1605 },
1606 {
1607 .type = SWITCH_TYPE_INT,
1608 .name = "init_vlan",
1609 .description = "Initialize VLAN tables to defaults",
1610 .set = rtl8366_init_vlan,
1611 .get = NULL,
1612 .max = 1
1613 },
1614
1615 {
1616 .type = SWITCH_TYPE_INT,
1617 .name = "reset_mibs",
1618 .description = "Reset all MIB counters",
1619 .set = rtl8366_global_reset_mibs,
1620 .get = NULL,
1621 .max = 1
1622 },
1623 {
1624 .type = SWITCH_TYPE_INT,
1625 .name = "blinkrate",
1626 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1627 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1628 .set = rtl8366_global_set_blinkrate,
1629 .get = rtl8366_global_get_blinkrate,
1630 .max = 5
1631 },
1632 };
1633
1634 static struct switch_attr rtl8366_port[] = {
1635 {
1636 .type = SWITCH_TYPE_STRING,
1637 .name = "link",
1638 .description = "Get port link information",
1639 .max = 1,
1640 .set = NULL,
1641 .get = rtl8366_attr_get_port_link
1642 },
1643 {
1644 .type = SWITCH_TYPE_INT,
1645 .name = "reset_mib",
1646 .description = "Reset single port MIB counters",
1647 .max = 1,
1648 .set = rtl8366_reset_port_mibs,
1649 .get = NULL
1650 },
1651 {
1652 .type = SWITCH_TYPE_STRING,
1653 .name = "mib",
1654 .description = "Get MIB counters for port",
1655 .max = 33,
1656 .set = NULL,
1657 .get = rtl8366_get_port_mib
1658 },
1659 {
1660 .type = SWITCH_TYPE_INT,
1661 .name = "led",
1662 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1663 .max = 15,
1664 .set = rtl8366_set_port_led,
1665 .get = rtl8366_get_port_led
1666 },
1667 };
1668
1669 static struct switch_attr rtl8366_vlan[] = {
1670 {
1671 .type = SWITCH_TYPE_INT,
1672 .name = "untag",
1673 .description = "Get/Set VLAN untag port set (bitmask)",
1674 .set = rtl8366_set_untag,
1675 .get = rtl8366_get_untag,
1676 .max = 63,
1677 },
1678 {
1679 .type = SWITCH_TYPE_INT,
1680 .name = "member",
1681 .description = "Get/Set VLAN member port set (bitmask)",
1682 .set = rtl8366_set_member,
1683 .get = rtl8366_get_member,
1684 .max = 63,
1685 },
1686 {
1687 .type = SWITCH_TYPE_STRING,
1688 .name = "info",
1689 .description = "Get vlan information",
1690 .max = 1,
1691 .set = NULL,
1692 .get = rtl8366_attr_get_vlan_info
1693 },
1694 };
1695
1696
1697 /* template */
1698 static struct switch_dev rtldev = {
1699 .name = "RTL8366S",
1700 .cpu_port = RTL8366_PORT_NUM_CPU,
1701 .ports = RTL8366_NUM_PORTS,
1702 .vlans = RTL8366_NUM_VLANS,
1703 .attr_global = {
1704 .attr = rtl8366_globals,
1705 .n_attr = ARRAY_SIZE(rtl8366_globals),
1706 },
1707 .attr_port = {
1708 .attr = rtl8366_port,
1709 .n_attr = ARRAY_SIZE(rtl8366_port),
1710 },
1711 .attr_vlan = {
1712 .attr = rtl8366_vlan,
1713 .n_attr = ARRAY_SIZE(rtl8366_vlan),
1714 },
1715
1716 .get_port_pvid = rtl8366_get_port_pvid,
1717 .set_port_pvid = rtl8366_set_port_pvid,
1718 .reset_switch = rtl8366_reset_switch,
1719 };
1720
1721 static int rtl8366_smi_mii_read(struct mii_bus *bus, int addr, int reg)
1722 {
1723 struct rtl8366_smi *smi = bus->priv;
1724 u32 val = 0;
1725 int err;
1726
1727 err = rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &val);
1728 if (err)
1729 return 0xffff;
1730
1731 return val;
1732 }
1733
1734 static int rtl8366_smi_mii_write(struct mii_bus *bus, int addr, int reg,
1735 u16 val)
1736 {
1737 struct rtl8366_smi *smi = bus->priv;
1738 u32 t;
1739 int err;
1740
1741 err = rtl8366_smi_write_phy_reg(smi, addr, 0, reg, val);
1742 /* flush write */
1743 (void) rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &t);
1744
1745 return err;
1746 }
1747
1748 static int rtl8366_smi_mii_init(struct rtl8366_smi *smi)
1749 {
1750 int ret;
1751 int i;
1752
1753 smi->mii_bus = mdiobus_alloc();
1754 if (smi->mii_bus == NULL) {
1755 ret = -ENOMEM;
1756 goto err;
1757 }
1758
1759 spin_lock_init(&smi->lock);
1760 smi->mii_bus->priv = (void *) smi;
1761 smi->mii_bus->name = "rtl8366-smi";
1762 smi->mii_bus->read = rtl8366_smi_mii_read;
1763 smi->mii_bus->write = rtl8366_smi_mii_write;
1764 snprintf(smi->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1765 dev_name(&smi->pdev->dev));
1766 smi->mii_bus->parent = &smi->pdev->dev;
1767 smi->mii_bus->phy_mask = ~(0x1f);
1768 smi->mii_bus->irq = smi->mii_irq;
1769 for (i = 0; i < PHY_MAX_ADDR; i++)
1770 smi->mii_irq[i] = PHY_POLL;
1771
1772 ret = mdiobus_register(smi->mii_bus);
1773 if (ret)
1774 goto err_free;
1775
1776 return 0;
1777
1778 err_free:
1779 mdiobus_free(smi->mii_bus);
1780 err:
1781 return ret;
1782 }
1783
1784 static void rtl8366_smi_mii_cleanup(struct rtl8366_smi *smi)
1785 {
1786 mdiobus_unregister(smi->mii_bus);
1787 mdiobus_free(smi->mii_bus);
1788 }
1789
1790 static int rtl8366_smi_setup(struct rtl8366_smi *smi)
1791 {
1792 u32 chip_id = 0;
1793 u32 chip_ver = 0;
1794 int ret;
1795
1796 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1797 if (ret) {
1798 dev_err(&smi->pdev->dev, "unable to read chip id\n");
1799 return ret;
1800 }
1801
1802 switch (chip_id) {
1803 case RTL8366S_CHIP_ID_8366:
1804 break;
1805 default:
1806 dev_err(&smi->pdev->dev, "unknown chip id (%04x)\n", chip_id);
1807 return -ENODEV;
1808 }
1809
1810 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1811 &chip_ver);
1812 if (ret) {
1813 dev_err(&smi->pdev->dev, "unable to read chip version\n");
1814 return ret;
1815 }
1816
1817 dev_info(&smi->pdev->dev, "RTL%04x ver. %u chip found\n",
1818 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1819
1820 rtl8366_debugfs_init(smi);
1821
1822 return 0;
1823 }
1824
1825 static int __init rtl8366_smi_probe(struct platform_device *pdev)
1826 {
1827 static int rtl8366_smi_version_printed;
1828 struct rtl8366_smi_platform_data *pdata;
1829 struct rtl8366_smi *smi;
1830 int err;
1831
1832 if (!rtl8366_smi_version_printed++)
1833 printk(KERN_NOTICE RTL8366_SMI_DRIVER_DESC
1834 " version " RTL8366_SMI_DRIVER_VER"\n");
1835
1836 pdata = pdev->dev.platform_data;
1837 if (!pdata) {
1838 dev_err(&pdev->dev, "no platform data specified\n");
1839 err = -EINVAL;
1840 goto err_out;
1841 }
1842
1843 smi = kzalloc(sizeof(struct rtl8366_smi), GFP_KERNEL);
1844 if (!smi) {
1845 dev_err(&pdev->dev, "no memory for private data\n");
1846 err = -ENOMEM;
1847 goto err_out;
1848 }
1849
1850 err = gpio_request(pdata->gpio_sda, dev_name(&pdev->dev));
1851 if (err) {
1852 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1853 pdata->gpio_sda, err);
1854 goto err_free_smi;
1855 }
1856
1857 err = gpio_request(pdata->gpio_sck, dev_name(&pdev->dev));
1858 if (err) {
1859 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1860 pdata->gpio_sck, err);
1861 goto err_free_sda;
1862 }
1863
1864 smi->pdev = pdev;
1865 smi->pdata = pdata;
1866 spin_lock_init(&smi->lock);
1867
1868 platform_set_drvdata(pdev, smi);
1869
1870 dev_info(&pdev->dev, "using GPIO pins %u (SDA) and %u (SCK)\n",
1871 pdata->gpio_sda, pdata->gpio_sck);
1872
1873 err = rtl8366_smi_setup(smi);
1874 if (err)
1875 goto err_clear_drvdata;
1876
1877 err = rtl8366_smi_mii_init(smi);
1878 if (err)
1879 goto err_clear_drvdata;
1880
1881 return 0;
1882
1883 err_clear_drvdata:
1884 platform_set_drvdata(pdev, NULL);
1885 gpio_free(pdata->gpio_sck);
1886 err_free_sda:
1887 gpio_free(pdata->gpio_sda);
1888 err_free_smi:
1889 kfree(smi);
1890 err_out:
1891 return err;
1892 }
1893
1894 int rtl8366_phy_config_init(struct phy_device *phydev)
1895 {
1896 int err;
1897 struct net_device *netdev = phydev->attached_dev;
1898 struct rtl8366_smi *smi = phydev->bus->priv;
1899 struct switch_dev *dev = &smi->dev;
1900
1901 /* Only init the switch for the primary PHY */
1902 if (phydev->addr != 4) {
1903 printk(KERN_INFO "Discarding address: %d\n", phydev->addr);
1904 return 0;
1905 }
1906
1907 memcpy(&smi->dev, &rtldev, sizeof(struct switch_dev));
1908 dev->priv = smi;
1909 dev->netdev = netdev;
1910
1911 err = register_switch(dev, netdev);
1912 if (err < 0) {
1913 printk(KERN_INFO "Switch registration failed\n");
1914 return err;
1915 }
1916
1917 return 0;
1918 }
1919
1920 int rtl8366_phy_config_aneg(struct phy_device *phydev)
1921 {
1922 return 0;
1923 }
1924
1925 static struct phy_driver rtl8366_smi_phy_driver = {
1926 .phy_id = 0x001cc960,
1927 .name = "Realtek RTL8366",
1928 .phy_id_mask = 0x1ffffff0,
1929 .features = PHY_GBIT_FEATURES,
1930 .config_aneg = rtl8366_phy_config_aneg,
1931 .config_init = rtl8366_phy_config_init,
1932 .read_status = genphy_read_status,
1933 .driver = {
1934 .owner = THIS_MODULE,
1935 },
1936 };
1937
1938 static int __devexit rtl8366_smi_remove(struct platform_device *pdev)
1939 {
1940 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1941
1942 if (smi) {
1943 struct rtl8366_smi_platform_data *pdata;
1944
1945 pdata = pdev->dev.platform_data;
1946
1947 rtl8366_debugfs_remove(smi);
1948 phy_driver_unregister(&rtl8366_smi_phy_driver);
1949 rtl8366_smi_mii_cleanup(smi);
1950 platform_set_drvdata(pdev, NULL);
1951 gpio_free(pdata->gpio_sck);
1952 gpio_free(pdata->gpio_sda);
1953 kfree(smi);
1954 }
1955
1956 return 0;
1957 }
1958
1959 static struct platform_driver rtl8366_smi_driver = {
1960 .driver = {
1961 .name = RTL8366_SMI_DRIVER_NAME,
1962 .owner = THIS_MODULE,
1963 },
1964 .probe = rtl8366_smi_probe,
1965 .remove = __devexit_p(rtl8366_smi_remove),
1966 };
1967
1968 static int __init rtl8366_smi_init(void)
1969 {
1970 int ret;
1971 ret = platform_driver_register(&rtl8366_smi_driver);
1972 if (ret)
1973 return ret;
1974
1975 ret = phy_driver_register(&rtl8366_smi_phy_driver);
1976 if (ret)
1977 goto err_platform_unregister;
1978
1979 return 0;
1980
1981 err_platform_unregister:
1982 platform_driver_unregister(&rtl8366_smi_driver);
1983 return ret;
1984 }
1985 module_init(rtl8366_smi_init);
1986
1987 static void __exit rtl8366_smi_exit(void)
1988 {
1989 phy_driver_unregister(&rtl8366_smi_phy_driver);
1990 platform_driver_unregister(&rtl8366_smi_driver);
1991 }
1992 module_exit(rtl8366_smi_exit);
1993
1994 MODULE_DESCRIPTION(RTL8366_SMI_DRIVER_DESC);
1995 MODULE_VERSION(RTL8366_SMI_DRIVER_VER);
1996 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1997 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1998 MODULE_LICENSE("GPL v2");
1999 MODULE_ALIAS("platform:" RTL8366_SMI_DRIVER_NAME);
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