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rtl8366_smi: fix parameter checking in rtl8366_attr_get_vlan_info
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / phy / rtl8366_smi.c
1 /*
2 * Platform driver for the Realtek RTL8366 ethernet switch
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio.h>
18 #include <linux/spinlock.h>
19 #include <linux/skbuff.h>
20 #include <linux/switch.h>
21 #include <linux/phy.h>
22 #include <linux/rtl8366_smi.h>
23
24 /* #define DEBUG 1 */
25
26 #ifdef DEBUG
27 #include <linux/debugfs.h>
28 #endif
29
30 #define RTL8366_SMI_DRIVER_NAME "rtl8366-smi"
31 #define RTL8366_SMI_DRIVER_DESC "Realtek RTL8366 switch driver"
32 #define RTL8366_SMI_DRIVER_VER "0.1.1"
33
34 #define RTL8366S_PHY_NO_MAX 4
35 #define RTL8366S_PHY_PAGE_MAX 7
36 #define RTL8366S_PHY_ADDR_MAX 31
37
38 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
39 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
40
41 #define RTL8366_RESET_CTRL_REG 0x0100
42 #define RTL8366_CHIP_CTRL_RESET_HW 1
43 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
44
45 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
46 #define RTL8366S_CHIP_VERSION_MASK 0xf
47 #define RTL8366S_CHIP_ID_REG 0x0105
48 #define RTL8366S_CHIP_ID_8366 0x8366
49
50 /* PHY registers control */
51 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
52 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
53
54 #define RTL8366S_PHY_CTRL_READ 1
55 #define RTL8366S_PHY_CTRL_WRITE 0
56
57 #define RTL8366S_PHY_REG_MASK 0x1f
58 #define RTL8366S_PHY_PAGE_OFFSET 5
59 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
60 #define RTL8366S_PHY_NO_OFFSET 9
61 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
62
63 #define RTL8366_SMI_ACK_RETRY_COUNT 5
64 #define RTL8366_SMI_CLK_DELAY 10 /* nsec */
65
66 /* LED control registers */
67 #define RTL8366_LED_BLINKRATE_REG 0x0420
68 #define RTL8366_LED_BLINKRATE_BIT 0
69 #define RTL8366_LED_BLINKRATE_MASK 0x0007
70
71 #define RTL8366_LED_CTRL_REG 0x0421
72 #define RTL8366_LED_0_1_CTRL_REG 0x0422
73 #define RTL8366_LED_2_3_CTRL_REG 0x0423
74
75 #define RTL8366S_MIB_COUNT 33
76 #define RTL8366S_GLOBAL_MIB_COUNT 1
77 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
78 #define RTL8366S_MIB_COUNTER_BASE 0x1000
79 #define RTL8366S_MIB_CTRL_REG 0x11F0
80 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
81 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
82 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
83
84 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
85 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
86 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
87
88
89 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
92
93 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
94
95 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
96 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
97 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
98
99 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
100
101
102 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
103 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
104 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
105 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
106 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
107 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
108 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
109
110
111 #define RTL8366_PORT_NUM_CPU 5
112 #define RTL8366_NUM_PORTS 6
113 #define RTL8366_NUM_VLANS 16
114 #define RTL8366_NUM_LEDGROUPS 4
115 #define RTL8366_NUM_VIDS 4096
116 #define RTL8366S_PRIORITYMAX 7
117 #define RTL8366S_FIDMAX 7
118
119
120 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
121 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
122 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
123 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
124
125 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
126 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
127
128 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
129 RTL8366_PORT_2 | \
130 RTL8366_PORT_3 | \
131 RTL8366_PORT_4 | \
132 RTL8366_PORT_UNKNOWN | \
133 RTL8366_PORT_CPU)
134
135 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
136 RTL8366_PORT_2 | \
137 RTL8366_PORT_3 | \
138 RTL8366_PORT_4 | \
139 RTL8366_PORT_UNKNOWN)
140
141 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
142 RTL8366_PORT_2 | \
143 RTL8366_PORT_3 | \
144 RTL8366_PORT_4)
145
146 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
147 RTL8366_PORT_CPU)
148
149 struct rtl8366s_vlanconfig {
150 u16 reserved2:1;
151 u16 priority:3;
152 u16 vid:12;
153
154 u16 reserved1:1;
155 u16 fid:3;
156 u16 untag:6;
157 u16 member:6;
158 };
159
160 struct rtl8366s_vlan4kentry {
161 u16 reserved1:4;
162 u16 vid:12;
163
164 u16 reserved2:1;
165 u16 fid:3;
166 u16 untag:6;
167 u16 member:6;
168 };
169
170 static const char *MIBCOUNTERS[] = { "IfInOctets ",
171 "EtherStatsOctets ",
172 "EtherStatsUnderSizePkts ",
173 "EtherFregament ",
174 "EtherStatsPkts64Octets ",
175 "EtherStatsPkts65to127Octets ",
176 "EtherStatsPkts128to255Octets ",
177 "EtherStatsPkts256to511Octets ",
178 "EtherStatsPkts512to1023Octets ",
179 "EtherStatsPkts1024to1518Octets ",
180 "EtherOversizeStats ",
181 "EtherStatsJabbers ",
182 "IfInUcastPkts ",
183 "EtherStatsMulticastPkts ",
184 "EtherStatsBroadcastPkts ",
185 "EtherStatsDropEvents ",
186 "Dot3StatsFCSErrors ",
187 "Dot3StatsSymbolErrors ",
188 "Dot3InPauseFrames ",
189 "Dot3ControlInUnknownOpcodes ",
190 "IfOutOctets ",
191 "Dot3StatsSingleCollisionFrames ",
192 "Dot3StatMultipleCollisionFrames ",
193 "Dot3sDeferredTransmissions ",
194 "Dot3StatsLateCollisions ",
195 "EtherStatsCollisions ",
196 "Dot3StatsExcessiveCollisions ",
197 "Dot3OutPauseFrames ",
198 "Dot1dBasePortDelayExceededDiscards",
199 "Dot1dTpPortInDiscards ",
200 "IfOutUcastPkts ",
201 "IfOutMulticastPkts ",
202 "IfOutBroadcastPkts ",
203 NULL };
204
205 struct rtl8366_smi {
206 struct platform_device *pdev;
207 struct rtl8366_smi_platform_data *pdata;
208 spinlock_t lock;
209 struct mii_bus *mii_bus;
210 struct switch_dev dev;
211 int mii_irq[PHY_MAX_ADDR];
212 char buf[4096];
213 #ifdef DEBUG
214 struct dentry *debugfs_root;
215 #endif
216 };
217
218 #ifdef DEBUG
219 u16 g_dbg_reg;
220 #endif
221
222 static inline struct rtl8366_smi *sw_to_rtl8366(struct switch_dev *sw)
223 {
224 return container_of(sw, struct rtl8366_smi, dev);
225 }
226
227 static inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi)
228 {
229 ndelay(RTL8366_SMI_CLK_DELAY);
230 }
231
232 static void rtl8366_smi_start(struct rtl8366_smi *smi)
233 {
234 unsigned int sda = smi->pdata->gpio_sda;
235 unsigned int sck = smi->pdata->gpio_sck;
236
237 /*
238 * Set GPIO pins to output mode, with initial state:
239 * SCK = 0, SDA = 1
240 */
241 gpio_direction_output(sck, 0);
242 gpio_direction_output(sda, 1);
243 rtl8366_smi_clk_delay(smi);
244
245 /* CLK 1: 0 -> 1, 1 -> 0 */
246 gpio_set_value(sck, 1);
247 rtl8366_smi_clk_delay(smi);
248 gpio_set_value(sck, 0);
249 rtl8366_smi_clk_delay(smi);
250
251 /* CLK 2: */
252 gpio_set_value(sck, 1);
253 rtl8366_smi_clk_delay(smi);
254 gpio_set_value(sda, 0);
255 rtl8366_smi_clk_delay(smi);
256 gpio_set_value(sck, 0);
257 rtl8366_smi_clk_delay(smi);
258 gpio_set_value(sda, 1);
259 }
260
261 static void rtl8366_smi_stop(struct rtl8366_smi *smi)
262 {
263 unsigned int sda = smi->pdata->gpio_sda;
264 unsigned int sck = smi->pdata->gpio_sck;
265
266 rtl8366_smi_clk_delay(smi);
267 gpio_set_value(sda, 0);
268 gpio_set_value(sck, 1);
269 rtl8366_smi_clk_delay(smi);
270 gpio_set_value(sda, 1);
271 rtl8366_smi_clk_delay(smi);
272 gpio_set_value(sck, 1);
273 rtl8366_smi_clk_delay(smi);
274 gpio_set_value(sck, 0);
275 rtl8366_smi_clk_delay(smi);
276 gpio_set_value(sck, 1);
277
278 /* add a click */
279 rtl8366_smi_clk_delay(smi);
280 gpio_set_value(sck, 0);
281 rtl8366_smi_clk_delay(smi);
282 gpio_set_value(sck, 1);
283
284 /* set GPIO pins to input mode */
285 gpio_direction_input(sda);
286 gpio_direction_input(sck);
287 }
288
289 static void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len)
290 {
291 unsigned int sda = smi->pdata->gpio_sda;
292 unsigned int sck = smi->pdata->gpio_sck;
293
294 for (; len > 0; len--) {
295 rtl8366_smi_clk_delay(smi);
296
297 /* prepare data */
298 if ( data & ( 1 << (len - 1)) )
299 gpio_set_value(sda, 1);
300 else
301 gpio_set_value(sda, 0);
302 rtl8366_smi_clk_delay(smi);
303
304 /* clocking */
305 gpio_set_value(sck, 1);
306 rtl8366_smi_clk_delay(smi);
307 gpio_set_value(sck, 0);
308 }
309 }
310
311 static void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data)
312 {
313 unsigned int sda = smi->pdata->gpio_sda;
314 unsigned int sck = smi->pdata->gpio_sck;
315
316 gpio_direction_input(sda);
317
318 for (*data = 0; len > 0; len--) {
319 u32 u;
320
321 rtl8366_smi_clk_delay(smi);
322
323 /* clocking */
324 gpio_set_value(sck, 1);
325 rtl8366_smi_clk_delay(smi);
326 u = gpio_get_value(sda);
327 gpio_set_value(sck, 0);
328
329 *data |= (u << (len - 1));
330 }
331
332 gpio_direction_output(sda, 0);
333 }
334
335 static int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi)
336 {
337 int retry_cnt;
338
339 retry_cnt = 0;
340 do {
341 u32 ack;
342
343 rtl8366_smi_read_bits(smi, 1, &ack);
344 if (ack == 0)
345 break;
346
347 if (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT)
348 return -EIO;
349 } while (1);
350
351 return 0;
352 }
353
354 static int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data)
355 {
356 rtl8366_smi_write_bits(smi, data, 8);
357 return rtl8366_smi_wait_for_ack(smi);
358 }
359
360 static int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data)
361 {
362 u32 t;
363
364 /* read data */
365 rtl8366_smi_read_bits(smi, 8, &t);
366 *data = (t & 0xff);
367
368 /* send an ACK */
369 rtl8366_smi_write_bits(smi, 0x00, 1);
370
371 return 0;
372 }
373
374 static int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data)
375 {
376 u32 t;
377
378 /* read data */
379 rtl8366_smi_read_bits(smi, 8, &t);
380 *data = (t & 0xff);
381
382 /* send an ACK */
383 rtl8366_smi_write_bits(smi, 0x01, 1);
384
385 return 0;
386 }
387
388 static int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
389 {
390 unsigned long flags;
391 u8 lo = 0;
392 u8 hi = 0;
393 int ret;
394
395 spin_lock_irqsave(&smi->lock, flags);
396
397 rtl8366_smi_start(smi);
398
399 /* send READ command */
400 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x01);
401 if (ret)
402 goto out;
403
404 /* set ADDR[7:0] */
405 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
406 if (ret)
407 goto out;
408
409 /* set ADDR[15:8] */
410 ret = rtl8366_smi_write_byte(smi, addr >> 8);
411 if (ret)
412 goto out;
413
414 /* read DATA[7:0] */
415 rtl8366_smi_read_byte0(smi, &lo);
416 /* read DATA[15:8] */
417 rtl8366_smi_read_byte1(smi, &hi);
418
419 *data = ((u32) lo) | (((u32) hi) << 8);
420
421 ret = 0;
422
423 out:
424 rtl8366_smi_stop(smi);
425 spin_unlock_irqrestore(&smi->lock, flags);
426
427 return ret;
428 }
429
430 static int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
431 {
432 unsigned long flags;
433 int ret;
434
435 spin_lock_irqsave(&smi->lock, flags);
436
437 rtl8366_smi_start(smi);
438
439 /* send WRITE command */
440 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x00);
441 if (ret)
442 goto out;
443
444 /* set ADDR[7:0] */
445 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
446 if (ret)
447 goto out;
448
449 /* set ADDR[15:8] */
450 ret = rtl8366_smi_write_byte(smi, addr >> 8);
451 if (ret)
452 goto out;
453
454 /* write DATA[7:0] */
455 ret = rtl8366_smi_write_byte(smi, data & 0xff);
456 if (ret)
457 goto out;
458
459 /* write DATA[15:8] */
460 ret = rtl8366_smi_write_byte(smi, data >> 8);
461 if (ret)
462 goto out;
463
464 ret = 0;
465
466 out:
467 rtl8366_smi_stop(smi);
468 spin_unlock_irqrestore(&smi->lock, flags);
469
470 return ret;
471 }
472
473 static int rtl8366_smi_read_phy_reg(struct rtl8366_smi *smi,
474 u32 phy_no, u32 page, u32 addr, u32 *data)
475 {
476 u32 reg;
477 int ret;
478
479 if (phy_no > RTL8366S_PHY_NO_MAX)
480 return -EINVAL;
481
482 if (page > RTL8366S_PHY_PAGE_MAX)
483 return -EINVAL;
484
485 if (addr > RTL8366S_PHY_ADDR_MAX)
486 return -EINVAL;
487
488 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
489 RTL8366S_PHY_CTRL_READ);
490 if (ret)
491 return ret;
492
493 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
494 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
495 (addr & RTL8366S_PHY_REG_MASK);
496
497 ret = rtl8366_smi_write_reg(smi, reg, 0);
498 if (ret)
499 return ret;
500
501 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
502 if (ret)
503 return ret;
504
505 return 0;
506 }
507
508 static int rtl8366_smi_write_phy_reg(struct rtl8366_smi *smi,
509 u32 phy_no, u32 page, u32 addr, u32 data)
510 {
511 u32 reg;
512 int ret;
513
514 if (phy_no > RTL8366S_PHY_NO_MAX)
515 return -EINVAL;
516
517 if (page > RTL8366S_PHY_PAGE_MAX)
518 return -EINVAL;
519
520 if (addr > RTL8366S_PHY_ADDR_MAX)
521 return -EINVAL;
522
523 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
524 RTL8366S_PHY_CTRL_WRITE);
525 if (ret)
526 return ret;
527
528 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
529 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
530 (addr & RTL8366S_PHY_REG_MASK);
531
532 ret = rtl8366_smi_write_reg(smi, reg, data);
533 if (ret)
534 return ret;
535
536 return 0;
537 }
538
539 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
540 int port, unsigned long long *val)
541 {
542 int i;
543 int err;
544 u32 addr, data, regoffset;
545 u64 mibvalue;
546
547 /* address offset to MIBs counter */
548 const u16 mibLength[RTL8366S_MIB_COUNT] = {4, 4, 2, 2, 2, 2, 2, 2, 2,
549 2, 2, 2, 2, 2, 2, 2, 2, 2,
550 2, 2, 4, 2, 2, 2, 2, 2, 2,
551 2, 2, 2, 2, 2, 2};
552
553 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
554 return -EINVAL;
555
556 i = 0;
557 regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
558
559 while (i < counter) {
560 regoffset += mibLength[i];
561 i++;
562 }
563
564 addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
565
566
567 /* writing access counter address first */
568 /* then ASIC will prepare 64bits counter wait for being retrived */
569 data = 0;/* writing data will be discard by ASIC */
570 err = rtl8366_smi_write_reg(smi, addr, data);
571 if (err)
572 return err;
573
574 /* read MIB control register */
575 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
576 if (err)
577 return err;
578
579 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
580 return -EBUSY;
581
582 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
583 return -EIO;
584
585 mibvalue = 0;
586 addr = addr + mibLength[counter] - 1;
587 i = mibLength[counter];
588
589 while (i) {
590 err = rtl8366_smi_read_reg(smi, addr, &data);
591 if (err)
592 return err;
593
594 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
595
596 addr--;
597 i--;
598 }
599
600 *val = mibvalue;
601 return 0;
602 }
603
604 static int rtl8366s_get_vlan_4k_entry(struct rtl8366_smi *smi, u32 vid,
605 struct rtl8366s_vlan4kentry *vlan4k)
606 {
607 int err;
608 u32 data;
609 u16 *tableaddr;
610
611 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
612 vlan4k->vid = vid;
613
614 if (vid >= RTL8366_NUM_VIDS)
615 return -EINVAL;
616
617 tableaddr = (u16 *)vlan4k;
618
619 /* write VID */
620 data = *tableaddr;
621 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
622 if (err)
623 return err;
624
625 /* write table access control word */
626 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
627 RTL8366S_TABLE_VLAN_READ_CTRL);
628 if (err)
629 return err;
630
631 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
632 if (err)
633 return err;
634
635 *tableaddr = data;
636 tableaddr++;
637
638 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
639 &data);
640 if (err)
641 return err;
642
643 *tableaddr = data;
644 vlan4k->vid = vid;
645
646 return 0;
647 }
648
649 static int rtl8366s_set_vlan_4k_entry(struct rtl8366_smi *smi,
650 const struct rtl8366s_vlan4kentry *vlan4k)
651 {
652 int err;
653 u32 data;
654 u16 *tableaddr;
655
656 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
657 vlan4k->member > RTL8366_PORT_ALL ||
658 vlan4k->untag > RTL8366_PORT_ALL ||
659 vlan4k->fid > RTL8366S_FIDMAX)
660 return -EINVAL;
661
662 tableaddr = (u16 *)vlan4k;
663
664 data = *tableaddr;
665
666 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
667 if (err)
668 return err;
669
670 tableaddr++;
671
672 data = *tableaddr;
673
674 rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1, data);
675
676
677 /* write table access control word */
678 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
679 RTL8366S_TABLE_VLAN_WRITE_CTRL);
680 if (err)
681 return err;
682
683 return 0;
684 }
685
686 static int rtl8366s_get_vlan_member_config(struct rtl8366_smi *smi, u32 index,
687 struct rtl8366s_vlanconfig *vlanmc)
688 {
689 int err;
690 u32 addr;
691 u32 data;
692 u16 *tableaddr;
693
694 memset(vlanmc, '\0', sizeof(struct rtl8366s_vlanconfig));
695
696 if (index >= RTL8366_NUM_VLANS)
697 return -EINVAL;
698
699 tableaddr = (u16 *)vlanmc;
700
701 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
702
703 err = rtl8366_smi_read_reg(smi, addr, &data);
704 if (err)
705 return err;
706
707 *tableaddr = data;
708 tableaddr++;
709
710 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
711
712 err = rtl8366_smi_read_reg(smi, addr, &data);
713 if (err)
714 return err;
715
716 *tableaddr = data;
717
718 return 0;
719 }
720
721 static int rtl8366s_set_vlan_member_config(struct rtl8366_smi *smi, u32 index,
722 const struct rtl8366s_vlanconfig
723 *vlanmc)
724 {
725 int err;
726 u32 addr;
727 u32 data;
728 u16 *tableaddr;
729
730 if (index >= RTL8366_NUM_VLANS ||
731 vlanmc->vid >= RTL8366_NUM_VIDS ||
732 vlanmc->priority > RTL8366S_PRIORITYMAX ||
733 vlanmc->member > RTL8366_PORT_ALL ||
734 vlanmc->untag > RTL8366_PORT_ALL ||
735 vlanmc->fid > RTL8366S_FIDMAX)
736 return -EINVAL;
737
738 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
739
740
741 tableaddr = (u16 *)vlanmc;
742 data = *tableaddr;
743
744 err = rtl8366_smi_write_reg(smi, addr, data);
745 if (err)
746 return err;
747
748 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
749
750 tableaddr++;
751 data = *tableaddr;
752
753 err = rtl8366_smi_write_reg(smi, addr, data);
754 if (err)
755 return err;
756
757 return 0;
758 }
759
760 static int rtl8366_get_port_vlan_index(struct rtl8366_smi *smi, int port,
761 int *val)
762 {
763 int err;
764 u32 addr;
765 u32 data;
766
767 /* bits mapping to port vlan control register of port n */
768 const u16 bits[RTL8366_NUM_PORTS] = { 0x000F, 0x00F0, 0x0F00,
769 0xF000, 0x000F, 0x00F0 };
770 /* bits offset to port vlan control register of port n */
771 const u16 bitoffset[RTL8366_NUM_PORTS] = { 0, 4, 8, 12, 0, 4 };
772 /* address offset to port vlan control register of port n */
773 const u16 addroffset[RTL8366_NUM_PORTS] = { 0, 0, 0, 0, 1, 1 };
774
775 if (port >= RTL8366_NUM_PORTS)
776 return -EINVAL;
777
778 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addroffset[port];
779
780 err = rtl8366_smi_read_reg(smi, addr, &data);
781 if (err)
782 return err;
783
784 *val = (data & bits[port]) >> bitoffset[port];
785
786 return 0;
787
788 }
789
790 static int rtl8366_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
791 int *val)
792 {
793 int err;
794 int index;
795 struct rtl8366s_vlanconfig vlanmc;
796
797 err = rtl8366_get_port_vlan_index(smi, port, &index);
798 if (err)
799 return err;
800
801 err = rtl8366s_get_vlan_member_config(smi, index, &vlanmc);
802 if (err)
803 return err;
804
805 *val = vlanmc.vid;
806 return 0;
807 }
808
809 static int rtl8366_set_port_vlan_index(struct rtl8366_smi *smi, int port,
810 int index)
811 {
812 int err;
813 u32 addr;
814 u32 data;
815 u32 vlan_data;
816 u32 bits;
817
818 /* bits mapping to port vlan control register of port n */
819 const u16 bitmasks[6] = { 0x000F, 0x00F0, 0x0F00,
820 0xF000, 0x000F, 0x00F0 };
821 /* bits offset to port vlan control register of port n */
822 const u16 bitOff[6] = { 0, 4, 8, 12, 0, 4 };
823 /* address offset to port vlan control register of port n */
824 const u16 addrOff[6] = { 0, 0, 0, 0, 1, 1 };
825
826 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
827 return -EINVAL;
828
829 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addrOff[port];
830
831 bits = bitmasks[port];
832
833 data = (index << bitOff[port]) & bits;
834
835 err = rtl8366_smi_read_reg(smi, addr, &vlan_data);
836 if (err)
837 return err;
838
839 vlan_data &= ~(vlan_data & bits);
840 vlan_data |= data;
841
842 err = rtl8366_smi_write_reg(smi, addr, vlan_data);
843 if (err)
844 return err;
845
846 return 0;
847 }
848
849 static int rtl8366_set_vlan_port_pvid(struct rtl8366_smi *smi, int port,
850 int val)
851 {
852 int i;
853 struct rtl8366s_vlanconfig vlanmc;
854 struct rtl8366s_vlan4kentry vlan4k;
855
856 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
857 return -EINVAL;
858
859
860
861 /* Updating the 4K entry; lookup it and change the port member set */
862 rtl8366s_get_vlan_4k_entry(smi, val, &vlan4k);
863 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
864 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
865 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
866
867 /* For the 16 entries more work needs to be done. First see if such
868 VID is already there and change it */
869 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
870 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
871
872 /* Try to find an existing vid and update port member set */
873 if (val == vlanmc.vid) {
874 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
875 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
876
877 /* Now update PVID register settings */
878 rtl8366_set_port_vlan_index(smi, port, i);
879
880 return 0;
881 }
882 }
883
884 /* PVID could not be found from vlan table. Replace unused (one that
885 has no member ports) with new one */
886 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
887 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
888
889 /* See if this vlan member configuration is unused. It is
890 unused if member set contains no ports or CPU port only */
891 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
892 vlanmc.vid = val;
893 vlanmc.priority = 0;
894 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
895 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
896 vlanmc.fid = 0;
897
898 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
899
900 /* Now update PVID register settings */
901 rtl8366_set_port_vlan_index(smi, port, i);
902
903 return 0;
904 }
905 }
906
907 dev_err(&smi->pdev->dev, "All 16 vlan member configurations are in "
908 "use\n");
909 return -EINVAL;
910 }
911
912
913 static int rtl8366_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
914 {
915 u32 data = 0;
916 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
917
918 data &= ~(data & RTL8366_CHIP_CTRL_VLAN);
919 if (enable)
920 data |= RTL8366_CHIP_CTRL_VLAN;
921
922 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
923 }
924
925 static int rtl8366_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
926 {
927 u32 data = 0;
928 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
929
930 data &= ~(data & 1);
931 if (enable)
932 data |= 1;
933
934 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
935 }
936
937 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
938 {
939 struct rtl8366s_vlan4kentry vlan4k;
940 struct rtl8366s_vlanconfig vlanmc;
941 int err;
942 int i;
943
944 /* clear 16 VLAN member configuration */
945 vlanmc.vid = 0;
946 vlanmc.priority = 0;
947 vlanmc.member = 0;
948 vlanmc.untag = 0;
949 vlanmc.fid = 0;
950 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
951 err = rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
952 if (err)
953 return err;
954 }
955
956 /* Set a default VLAN with vid 1 to 4K table for all ports */
957 vlan4k.vid = 1;
958 vlan4k.member = RTL8366_PORT_ALL;
959 vlan4k.untag = RTL8366_PORT_ALL;
960 vlan4k.fid = 0;
961 err = rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
962 if (err)
963 return err;
964
965 /* Set all ports PVID to default VLAN */
966 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
967 err = rtl8366_set_vlan_port_pvid(smi, i, 0);
968 if (err)
969 return err;
970 }
971
972 return 0;
973 }
974
975 #ifdef DEBUG
976 static int rtl8366_debugfs_open(struct inode *inode, struct file *file)
977 {
978 file->private_data = inode->i_private;
979 return 0;
980 }
981
982 static ssize_t rtl8366_read_debugfs_mibs(struct file *file,
983 char __user *user_buf,
984 size_t count, loff_t *ppos)
985 {
986 int i, j, len = 0;
987 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
988 char *buf = smi->buf;
989
990 len += snprintf(buf + len, sizeof(smi->buf) - len, "MIB Counters:\n");
991 len += snprintf(buf + len, sizeof(smi->buf) - len, "Counter"
992 " "
993 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
994 "Port 4\n");
995
996 for (i = 0; i < 33; ++i) {
997
998 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d:%s ",
999 i, MIBCOUNTERS[i]);
1000 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1001 unsigned long long counter = 0;
1002
1003 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
1004 len += snprintf(buf + len, sizeof(smi->buf) - len,
1005 "[%llu]", counter);
1006 else
1007 len += snprintf(buf + len, sizeof(smi->buf) - len,
1008 "[error]");
1009
1010 if (j != RTL8366_NUM_PORTS - 1) {
1011 if (counter < 100000)
1012 len += snprintf(buf + len,
1013 sizeof(smi->buf) - len,
1014 "\t");
1015
1016 len += snprintf(buf + len, sizeof(smi->buf) - len,
1017 "\t");
1018 }
1019 }
1020 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1021 }
1022
1023 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1024
1025 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1026 }
1027
1028 static ssize_t rtl8366_read_debugfs_vlan(struct file *file,
1029 char __user *user_buf,
1030 size_t count, loff_t *ppos)
1031 {
1032 int i, j, len = 0;
1033 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1034 char *buf = smi->buf;
1035
1036 len += snprintf(buf + len, sizeof(smi->buf) - len, "VLAN Member Config:\n");
1037 len += snprintf(buf + len, sizeof(smi->buf) - len,
1038 "\t id \t vid \t prio \t member \t untag \t fid "
1039 "\tports\n");
1040
1041 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
1042 struct rtl8366s_vlanconfig vlanmc;
1043
1044 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
1045
1046 len += snprintf(buf + len, sizeof(smi->buf) - len,
1047 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
1048 "\t", i, vlanmc.vid, vlanmc.priority,
1049 vlanmc.member, vlanmc.untag, vlanmc.fid);
1050
1051 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1052 int index = 0;
1053 if (!rtl8366_get_port_vlan_index(smi, j, &index)) {
1054 if (index == i)
1055 len += snprintf(buf + len,
1056 sizeof(smi->buf) - len,
1057 "%d", j);
1058 }
1059 }
1060 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1061 }
1062
1063 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1064 }
1065
1066 static ssize_t rtl8366_read_debugfs_reg(struct file *file,
1067 char __user *user_buf,
1068 size_t count, loff_t *ppos)
1069 {
1070 u32 t, reg = g_dbg_reg;
1071 int err, len = 0;
1072 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1073 char *buf = smi->buf;
1074
1075 memset(buf, '\0', sizeof(smi->buf));
1076
1077 err = rtl8366_smi_read_reg(smi, reg, &t);
1078 if (err) {
1079 len += snprintf(buf, sizeof(smi->buf),
1080 "Read failed (reg: 0x%04x)\n", reg);
1081 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1082 }
1083
1084 len += snprintf(buf, sizeof(smi->buf), "reg = 0x%04x, val = 0x%04x\n",
1085 reg, t);
1086
1087 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1088 }
1089
1090 static ssize_t rtl8366_write_debugfs_reg(struct file *file,
1091 const char __user *user_buf,
1092 size_t count, loff_t *ppos)
1093 {
1094 unsigned long data;
1095 u32 reg = g_dbg_reg;
1096 int err;
1097 size_t len;
1098 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1099 char *buf = smi->buf;
1100
1101 len = min(count, sizeof(smi->buf) - 1);
1102 if (copy_from_user(buf, user_buf, len)) {
1103 dev_err(&smi->pdev->dev, "copy from user failed\n");
1104 return -EFAULT;
1105 }
1106
1107 buf[len] = '\0';
1108 if (len > 0 && buf[len - 1] == '\n')
1109 buf[len - 1] = '\0';
1110
1111
1112 if (strict_strtoul(buf, 16, &data)) {
1113 dev_err(&smi->pdev->dev, "Invalid reg value %s\n", buf);
1114 } else {
1115 err = rtl8366_smi_write_reg(smi, reg, data);
1116 if (err) {
1117 dev_err(&smi->pdev->dev,
1118 "writing reg 0x%04x val 0x%04lx failed\n",
1119 reg, data);
1120 }
1121 }
1122
1123 return count;
1124 }
1125
1126 static const struct file_operations fops_rtl8366_regs = {
1127 .read = rtl8366_read_debugfs_reg,
1128 .write = rtl8366_write_debugfs_reg,
1129 .open = rtl8366_debugfs_open,
1130 .owner = THIS_MODULE
1131 };
1132
1133 static const struct file_operations fops_rtl8366_vlan = {
1134 .read = rtl8366_read_debugfs_vlan,
1135 .open = rtl8366_debugfs_open,
1136 .owner = THIS_MODULE
1137 };
1138
1139 static const struct file_operations fops_rtl8366_mibs = {
1140 .read = rtl8366_read_debugfs_mibs,
1141 .open = rtl8366_debugfs_open,
1142 .owner = THIS_MODULE
1143 };
1144
1145 static void rtl8366_debugfs_init(struct rtl8366_smi *smi)
1146 {
1147 struct dentry *node;
1148 struct dentry *root;
1149
1150 if (!smi->debugfs_root)
1151 smi->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
1152
1153 if (!smi->debugfs_root) {
1154 dev_err(&smi->pdev->dev, "Unable to create debugfs dir\n");
1155 return;
1156 }
1157 root = smi->debugfs_root;
1158
1159 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
1160 if (!node) {
1161 dev_err(&smi->pdev->dev, "Creating debugfs file reg failed\n");
1162 return;
1163 }
1164
1165 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, smi,
1166 &fops_rtl8366_regs);
1167 if (!node) {
1168 dev_err(&smi->pdev->dev, "Creating debugfs file val failed\n");
1169 return;
1170 }
1171
1172 node = debugfs_create_file("vlan", S_IRUSR, root, smi,
1173 &fops_rtl8366_vlan);
1174 if (!node) {
1175 dev_err(&smi->pdev->dev, "Creating debugfs file vlan "
1176 "failed\n");
1177 return;
1178 }
1179
1180 node = debugfs_create_file("mibs", S_IRUSR, root, smi,
1181 &fops_rtl8366_mibs);
1182 if (!node) {
1183 dev_err(&smi->pdev->dev, "Creating debugfs file mibs "
1184 "xfailed\n");
1185 return;
1186 }
1187 }
1188
1189 static void rtl8366_debugfs_remove(struct rtl8366_smi *smi)
1190 {
1191 if (smi->debugfs_root) {
1192 debugfs_remove_recursive(smi->debugfs_root);
1193 smi->debugfs_root = NULL;
1194 }
1195 }
1196
1197 #else
1198 static inline void rtl8366_debugfs_init(struct rtl8366_smi *smi) {}
1199 static inline void rtl8366_debugfs_remove(struct rtl8366_smi *smi) {}
1200 #endif
1201
1202 static int rtl8366_global_reset_mibs(struct switch_dev *dev,
1203 const struct switch_attr *attr,
1204 struct switch_val *val)
1205 {
1206 u32 data = 0;
1207 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1208
1209 if (val->value.i == 1) {
1210 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1211 data |= (1 << 2);
1212 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1213 }
1214
1215 return 0;
1216 }
1217
1218 static int rtl8366_get_vlan(struct switch_dev *dev,
1219 const struct switch_attr *attr,
1220 struct switch_val *val)
1221 {
1222 u32 data;
1223 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1224
1225 if (attr->ofs == 1) {
1226 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1227
1228 if (data & RTL8366_CHIP_CTRL_VLAN)
1229 val->value.i = 1;
1230 else
1231 val->value.i = 0;
1232 } else if (attr->ofs == 2) {
1233 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1234
1235 if (data & 0x0001)
1236 val->value.i = 1;
1237 else
1238 val->value.i = 0;
1239 }
1240
1241 return 0;
1242 }
1243
1244 static int rtl8366_global_get_blinkrate(struct switch_dev *dev,
1245 const struct switch_attr *attr,
1246 struct switch_val *val)
1247 {
1248 u32 data;
1249 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1250 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1251
1252 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1253
1254 return 0;
1255 }
1256
1257 static int rtl8366_global_set_blinkrate(struct switch_dev *dev,
1258 const struct switch_attr *attr,
1259 struct switch_val *val)
1260 {
1261 u32 data;
1262 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1263
1264 if (val->value.i >= 6)
1265 return -EINVAL;
1266
1267 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1268
1269 data &= ~(data & RTL8366_LED_BLINKRATE_MASK);
1270 data |= val->value.i;
1271
1272 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1273
1274 return 0;
1275 }
1276
1277 static int rtl8366_set_vlan(struct switch_dev *dev,
1278 const struct switch_attr *attr,
1279 struct switch_val *val)
1280 {
1281 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1282
1283 if (attr->ofs == 1)
1284 return rtl8366_vlan_set_vlan(smi, val->value.i);
1285 else
1286 return rtl8366_vlan_set_4ktable(smi, val->value.i);
1287 }
1288
1289 static int rtl8366_attr_get_port_link(struct switch_dev *dev,
1290 const struct switch_attr *attr,
1291 struct switch_val *val)
1292 {
1293 u32 len = 0, data = 0;
1294 int speed, duplex, link, txpause, rxpause, nway;
1295 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1296 char *buf = smi->buf;
1297
1298 if (val->port_vlan >= RTL8366_NUM_PORTS)
1299 return -EINVAL;
1300
1301 memset(buf, '\0', sizeof(smi->buf));
1302 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1303 (val->port_vlan >> 1),
1304 &data);
1305
1306 if (val->port_vlan & 0x1)
1307 data = data >> 8;
1308
1309 speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
1310 duplex = (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) >> 2;
1311 link = (data & RTL8366S_PORT_STATUS_LINK_MASK) >> 4;
1312 txpause = (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) >> 5;
1313 rxpause = (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) >> 6;
1314 nway = (data & RTL8366S_PORT_STATUS_AN_MASK) >> 7;
1315
1316 len += snprintf(buf + len, sizeof(smi->buf) - len, "Port %d: ",
1317 val->port_vlan);
1318
1319 if (link)
1320 len += snprintf(buf + len, sizeof(smi->buf) - len,
1321 "Link UP, Speed: ");
1322 else
1323 len += snprintf(buf + len, sizeof(smi->buf) - len,
1324 "Link DOWN, Speed: ");
1325
1326 if (speed == 0)
1327 len += snprintf(buf + len, sizeof(smi->buf) - len, "10Base-TX ");
1328 else if (speed == 1)
1329 len += snprintf(buf + len, sizeof(smi->buf) - len, "100Base-TX ");
1330 else if (speed == 2)
1331 len += snprintf(buf + len, sizeof(smi->buf) - len, "1000Base-TX ");
1332
1333 if (duplex)
1334 len += snprintf(buf + len, sizeof(smi->buf) - len, "Full-Duplex, ");
1335 else
1336 len += snprintf(buf + len, sizeof(smi->buf) - len, "Half-Duplex, ");
1337
1338 if (txpause)
1339 len += snprintf(buf + len, sizeof(smi->buf) - len, "TX-Pause ");
1340 if (rxpause)
1341 len += snprintf(buf + len, sizeof(smi->buf) - len, "RX-Pause ");
1342 if (nway)
1343 len += snprintf(buf + len, sizeof(smi->buf) - len, "nway ");
1344
1345 val->value.s = buf;
1346 val->len = len;
1347
1348 return 0;
1349 }
1350
1351 static int rtl8366_attr_get_vlan_info(struct switch_dev *dev,
1352 const struct switch_attr *attr,
1353 struct switch_val *val)
1354 {
1355 int i;
1356 u32 len = 0;
1357 struct rtl8366s_vlanconfig vlanmc;
1358 struct rtl8366s_vlan4kentry vlan4k;
1359 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1360 char *buf = smi->buf;
1361
1362 if (val->port_vlan >= RTL8366_NUM_VLANS)
1363 return -EINVAL;
1364
1365 memset(buf, '\0', sizeof(smi->buf));
1366
1367 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1368 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1369
1370 len += snprintf(buf + len, sizeof(smi->buf) - len, "VLAN %d: Ports: ",
1371 val->port_vlan);
1372
1373 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1374 int index = 0;
1375 if (!rtl8366_get_port_vlan_index(smi, i, &index) &&
1376 index == val->port_vlan)
1377 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d", i);
1378 }
1379 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1380
1381 len += snprintf(buf + len, sizeof(smi->buf) - len,
1382 "\t\t vid \t prio \t member \t untag \t fid\n");
1383 len += snprintf(buf + len, sizeof(smi->buf) - len, "\tMC:\t");
1384 len += snprintf(buf + len, sizeof(smi->buf) - len,
1385 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1386 vlanmc.vid, vlanmc.priority, vlanmc.member,
1387 vlanmc.untag, vlanmc.fid);
1388 len += snprintf(buf + len, sizeof(smi->buf) - len, "\t4K:\t");
1389 len += snprintf(buf + len, sizeof(smi->buf) - len,
1390 "%d \t \t 0x%04x \t 0x%04x \t %d",
1391 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1392
1393 val->value.s = buf;
1394 val->len = len;
1395
1396 return 0;
1397 }
1398
1399 static int rtl8366_set_port_led(struct switch_dev *dev,
1400 const struct switch_attr *attr,
1401 struct switch_val *val)
1402 {
1403 u32 data = 0;
1404 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1405 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1406 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1407 return -EINVAL;
1408
1409 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1410 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1411 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1412 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1413 } else {
1414 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1415 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1416 (val->value.i << (val->port_vlan * 4));
1417 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1418 }
1419
1420 return 0;
1421 }
1422
1423 static int rtl8366_get_port_led(struct switch_dev *dev,
1424 const struct switch_attr *attr,
1425 struct switch_val *val)
1426 {
1427 u32 data = 0;
1428 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1429 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1430 return -EINVAL;
1431
1432 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1433 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1434
1435 return 0;
1436 }
1437
1438 static int rtl8366_reset_port_mibs(struct switch_dev *dev,
1439 const struct switch_attr *attr,
1440 struct switch_val *val)
1441 {
1442 u32 data = 0;
1443 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1444 if (val->port_vlan >= RTL8366_NUM_PORTS)
1445 return -EINVAL;
1446
1447 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1448 data |= (1 << (val->port_vlan + 3));
1449 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1450
1451 return 0;
1452 }
1453
1454 static int rtl8366_get_port_mib(struct switch_dev *dev,
1455 const struct switch_attr *attr,
1456 struct switch_val *val)
1457 {
1458 int i, len = 0;
1459 unsigned long long counter = 0;
1460 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1461 char *buf = smi->buf;
1462
1463 if (val->port_vlan >= RTL8366_NUM_PORTS)
1464 return -EINVAL;
1465
1466 len += snprintf(buf + len, sizeof(smi->buf) - len, "Port %d MIB counters\n",
1467 val->port_vlan);
1468 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1469
1470 len += snprintf(buf + len, sizeof(smi->buf) - len,
1471 "%d:%s\t", i, MIBCOUNTERS[i]);
1472 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1473 len += snprintf(buf + len, sizeof(smi->buf) - len,
1474 "[%llu]\n", counter);
1475 else
1476 len += snprintf(buf + len, sizeof(smi->buf) - len,
1477 "[error]\n");
1478 }
1479
1480 val->value.s = buf;
1481 val->len = len;
1482 return 0;
1483 }
1484
1485 static int rtl8366_get_ports(struct switch_dev *dev,
1486 struct switch_val *val)
1487 {
1488 struct rtl8366s_vlanconfig vlanmc;
1489 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1490 struct switch_port *port;
1491 int i;
1492
1493 if (val->port_vlan >= RTL8366_NUM_VLANS)
1494 return -EINVAL;
1495
1496 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1497
1498 port = &val->value.ports[0];
1499 val->len = 0;
1500 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1501 if (!(vlanmc.member & BIT(i)))
1502 continue;
1503
1504 port->id = i;
1505 port->flags = (vlanmc.untag & BIT(i)) ?
1506 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1507 val->len++;
1508 port++;
1509 }
1510 return 0;
1511 }
1512
1513 static int rtl8366_set_ports(struct switch_dev *dev,
1514 struct switch_val *val)
1515 {
1516 struct rtl8366s_vlanconfig vlanmc;
1517 struct rtl8366s_vlan4kentry vlan4k;
1518 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1519 struct switch_port *port;
1520 int i;
1521
1522 if (val->port_vlan >= RTL8366_NUM_VLANS)
1523 return -EINVAL;
1524
1525 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1526 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1527
1528 vlanmc.untag = 0;
1529 vlanmc.member = 0;
1530
1531 port = &val->value.ports[0];
1532 for (i = 0; i < val->len; i++, port++) {
1533 vlanmc.member |= BIT(port->id);
1534
1535 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1536 vlanmc.untag |= BIT(port->id);
1537 }
1538
1539 vlan4k.member = vlanmc.member;
1540 vlan4k.untag = vlanmc.untag;
1541
1542 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanmc);
1543 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
1544 return 0;
1545 }
1546
1547 static int rtl8366_get_port_pvid(struct switch_dev *dev, int port, int *val)
1548 {
1549 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1550 return rtl8366_get_vlan_port_pvid(smi, port, val);
1551 }
1552
1553 static int rtl8366_set_port_pvid(struct switch_dev *dev, int port, int val)
1554 {
1555 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1556 return rtl8366_set_vlan_port_pvid(smi, port, val);
1557 }
1558
1559 static int rtl8366_reset_switch(struct switch_dev *dev)
1560 {
1561 struct rtl8366_smi *smi = sw_to_rtl8366(dev);
1562 int timeout = 10;
1563 u32 data;
1564
1565 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
1566 RTL8366_CHIP_CTRL_RESET_HW);
1567 do {
1568 msleep(1);
1569 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
1570 return -EIO;
1571
1572 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
1573 break;
1574 } while (--timeout);
1575
1576 if (!timeout) {
1577 printk("Timeout waiting for the switch to reset\n");
1578 return -EIO;
1579 }
1580
1581 return rtl8366s_reset_vlan(smi);
1582 }
1583
1584 static struct switch_attr rtl8366_globals[] = {
1585 {
1586 .type = SWITCH_TYPE_INT,
1587 .name = "enable_vlan",
1588 .description = "Enable VLAN mode",
1589 .set = rtl8366_set_vlan,
1590 .get = rtl8366_get_vlan,
1591 .max = 1,
1592 .ofs = 1
1593 },
1594 {
1595 .type = SWITCH_TYPE_INT,
1596 .name = "enable_vlan4k",
1597 .description = "Enable VLAN 4K mode",
1598 .set = rtl8366_set_vlan,
1599 .get = rtl8366_get_vlan,
1600 .max = 1,
1601 .ofs = 2
1602 },
1603 {
1604 .type = SWITCH_TYPE_INT,
1605 .name = "reset_mibs",
1606 .description = "Reset all MIB counters",
1607 .set = rtl8366_global_reset_mibs,
1608 .get = NULL,
1609 .max = 1
1610 },
1611 {
1612 .type = SWITCH_TYPE_INT,
1613 .name = "blinkrate",
1614 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1615 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1616 .set = rtl8366_global_set_blinkrate,
1617 .get = rtl8366_global_get_blinkrate,
1618 .max = 5
1619 },
1620 };
1621
1622 static struct switch_attr rtl8366_port[] = {
1623 {
1624 .type = SWITCH_TYPE_STRING,
1625 .name = "link",
1626 .description = "Get port link information",
1627 .max = 1,
1628 .set = NULL,
1629 .get = rtl8366_attr_get_port_link
1630 },
1631 {
1632 .type = SWITCH_TYPE_INT,
1633 .name = "reset_mib",
1634 .description = "Reset single port MIB counters",
1635 .max = 1,
1636 .set = rtl8366_reset_port_mibs,
1637 .get = NULL
1638 },
1639 {
1640 .type = SWITCH_TYPE_STRING,
1641 .name = "mib",
1642 .description = "Get MIB counters for port",
1643 .max = 33,
1644 .set = NULL,
1645 .get = rtl8366_get_port_mib
1646 },
1647 {
1648 .type = SWITCH_TYPE_INT,
1649 .name = "led",
1650 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1651 .max = 15,
1652 .set = rtl8366_set_port_led,
1653 .get = rtl8366_get_port_led
1654 },
1655 };
1656
1657 static struct switch_attr rtl8366_vlan[] = {
1658 {
1659 .type = SWITCH_TYPE_STRING,
1660 .name = "info",
1661 .description = "Get vlan information",
1662 .max = 1,
1663 .set = NULL,
1664 .get = rtl8366_attr_get_vlan_info
1665 },
1666 };
1667
1668
1669 /* template */
1670 static struct switch_dev rtldev = {
1671 .name = "RTL8366S",
1672 .cpu_port = RTL8366_PORT_NUM_CPU,
1673 .ports = RTL8366_NUM_PORTS,
1674 .vlans = RTL8366_NUM_VLANS,
1675 .attr_global = {
1676 .attr = rtl8366_globals,
1677 .n_attr = ARRAY_SIZE(rtl8366_globals),
1678 },
1679 .attr_port = {
1680 .attr = rtl8366_port,
1681 .n_attr = ARRAY_SIZE(rtl8366_port),
1682 },
1683 .attr_vlan = {
1684 .attr = rtl8366_vlan,
1685 .n_attr = ARRAY_SIZE(rtl8366_vlan),
1686 },
1687
1688 .get_vlan_ports = rtl8366_get_ports,
1689 .set_vlan_ports = rtl8366_set_ports,
1690 .get_port_pvid = rtl8366_get_port_pvid,
1691 .set_port_pvid = rtl8366_set_port_pvid,
1692 .reset_switch = rtl8366_reset_switch,
1693 };
1694
1695 static int rtl8366_smi_switch_init(struct rtl8366_smi *smi)
1696 {
1697 struct switch_dev *dev = &smi->dev;
1698 int err;
1699
1700 memcpy(dev, &rtldev, sizeof(struct switch_dev));
1701 dev->priv = smi;
1702 dev->devname = dev_name(&smi->pdev->dev);
1703
1704 err = register_switch(dev, NULL);
1705 if (err)
1706 dev_err(&smi->pdev->dev, "switch registration failed\n");
1707
1708 return err;
1709 }
1710
1711 static void rtl8366_smi_switch_cleanup(struct rtl8366_smi *smi)
1712 {
1713 unregister_switch(&smi->dev);
1714 }
1715
1716 static int rtl8366_smi_mii_read(struct mii_bus *bus, int addr, int reg)
1717 {
1718 struct rtl8366_smi *smi = bus->priv;
1719 u32 val = 0;
1720 int err;
1721
1722 err = rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &val);
1723 if (err)
1724 return 0xffff;
1725
1726 return val;
1727 }
1728
1729 static int rtl8366_smi_mii_write(struct mii_bus *bus, int addr, int reg,
1730 u16 val)
1731 {
1732 struct rtl8366_smi *smi = bus->priv;
1733 u32 t;
1734 int err;
1735
1736 err = rtl8366_smi_write_phy_reg(smi, addr, 0, reg, val);
1737 /* flush write */
1738 (void) rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &t);
1739
1740 return err;
1741 }
1742
1743 static int rtl8366_smi_mii_init(struct rtl8366_smi *smi)
1744 {
1745 int ret;
1746 int i;
1747
1748 smi->mii_bus = mdiobus_alloc();
1749 if (smi->mii_bus == NULL) {
1750 ret = -ENOMEM;
1751 goto err;
1752 }
1753
1754 spin_lock_init(&smi->lock);
1755 smi->mii_bus->priv = (void *) smi;
1756 smi->mii_bus->name = "rtl8366-smi";
1757 smi->mii_bus->read = rtl8366_smi_mii_read;
1758 smi->mii_bus->write = rtl8366_smi_mii_write;
1759 snprintf(smi->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1760 dev_name(&smi->pdev->dev));
1761 smi->mii_bus->parent = &smi->pdev->dev;
1762 smi->mii_bus->phy_mask = ~(0x1f);
1763 smi->mii_bus->irq = smi->mii_irq;
1764 for (i = 0; i < PHY_MAX_ADDR; i++)
1765 smi->mii_irq[i] = PHY_POLL;
1766
1767 ret = mdiobus_register(smi->mii_bus);
1768 if (ret)
1769 goto err_free;
1770
1771 return 0;
1772
1773 err_free:
1774 mdiobus_free(smi->mii_bus);
1775 err:
1776 return ret;
1777 }
1778
1779 static void rtl8366_smi_mii_cleanup(struct rtl8366_smi *smi)
1780 {
1781 mdiobus_unregister(smi->mii_bus);
1782 mdiobus_free(smi->mii_bus);
1783 }
1784
1785 static int rtl8366_smi_mii_bus_match(struct mii_bus *bus)
1786 {
1787 return (bus->read == rtl8366_smi_mii_read &&
1788 bus->write == rtl8366_smi_mii_write);
1789 }
1790
1791 static int rtl8366_smi_setup(struct rtl8366_smi *smi)
1792 {
1793 u32 chip_id = 0;
1794 u32 chip_ver = 0;
1795 int ret;
1796
1797 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1798 if (ret) {
1799 dev_err(&smi->pdev->dev, "unable to read chip id\n");
1800 return ret;
1801 }
1802
1803 switch (chip_id) {
1804 case RTL8366S_CHIP_ID_8366:
1805 break;
1806 default:
1807 dev_err(&smi->pdev->dev, "unknown chip id (%04x)\n", chip_id);
1808 return -ENODEV;
1809 }
1810
1811 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1812 &chip_ver);
1813 if (ret) {
1814 dev_err(&smi->pdev->dev, "unable to read chip version\n");
1815 return ret;
1816 }
1817
1818 dev_info(&smi->pdev->dev, "RTL%04x ver. %u chip found\n",
1819 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1820
1821 rtl8366_debugfs_init(smi);
1822
1823 return 0;
1824 }
1825
1826 static int __init rtl8366_smi_probe(struct platform_device *pdev)
1827 {
1828 static int rtl8366_smi_version_printed;
1829 struct rtl8366_smi_platform_data *pdata;
1830 struct rtl8366_smi *smi;
1831 int err;
1832
1833 if (!rtl8366_smi_version_printed++)
1834 printk(KERN_NOTICE RTL8366_SMI_DRIVER_DESC
1835 " version " RTL8366_SMI_DRIVER_VER"\n");
1836
1837 pdata = pdev->dev.platform_data;
1838 if (!pdata) {
1839 dev_err(&pdev->dev, "no platform data specified\n");
1840 err = -EINVAL;
1841 goto err_out;
1842 }
1843
1844 smi = kzalloc(sizeof(struct rtl8366_smi), GFP_KERNEL);
1845 if (!smi) {
1846 dev_err(&pdev->dev, "no memory for private data\n");
1847 err = -ENOMEM;
1848 goto err_out;
1849 }
1850
1851 err = gpio_request(pdata->gpio_sda, dev_name(&pdev->dev));
1852 if (err) {
1853 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1854 pdata->gpio_sda, err);
1855 goto err_free_smi;
1856 }
1857
1858 err = gpio_request(pdata->gpio_sck, dev_name(&pdev->dev));
1859 if (err) {
1860 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1861 pdata->gpio_sck, err);
1862 goto err_free_sda;
1863 }
1864
1865 smi->pdev = pdev;
1866 smi->pdata = pdata;
1867 spin_lock_init(&smi->lock);
1868
1869 platform_set_drvdata(pdev, smi);
1870
1871 dev_info(&pdev->dev, "using GPIO pins %u (SDA) and %u (SCK)\n",
1872 pdata->gpio_sda, pdata->gpio_sck);
1873
1874 err = rtl8366_smi_setup(smi);
1875 if (err)
1876 goto err_clear_drvdata;
1877
1878 err = rtl8366_smi_mii_init(smi);
1879 if (err)
1880 goto err_clear_drvdata;
1881
1882 err = rtl8366_smi_switch_init(smi);
1883 if (err)
1884 goto err_mii_cleanup;
1885
1886 return 0;
1887
1888 err_mii_cleanup:
1889 rtl8366_smi_mii_cleanup(smi);
1890 err_clear_drvdata:
1891 platform_set_drvdata(pdev, NULL);
1892 gpio_free(pdata->gpio_sck);
1893 err_free_sda:
1894 gpio_free(pdata->gpio_sda);
1895 err_free_smi:
1896 kfree(smi);
1897 err_out:
1898 return err;
1899 }
1900
1901 int rtl8366_phy_config_init(struct phy_device *phydev)
1902 {
1903 if (!rtl8366_smi_mii_bus_match(phydev->bus))
1904 return -EINVAL;
1905
1906 return 0;
1907 }
1908
1909 int rtl8366_phy_config_aneg(struct phy_device *phydev)
1910 {
1911 return 0;
1912 }
1913
1914 static struct phy_driver rtl8366_smi_phy_driver = {
1915 .phy_id = 0x001cc960,
1916 .name = "Realtek RTL8366",
1917 .phy_id_mask = 0x1ffffff0,
1918 .features = PHY_GBIT_FEATURES,
1919 .config_aneg = rtl8366_phy_config_aneg,
1920 .config_init = rtl8366_phy_config_init,
1921 .read_status = genphy_read_status,
1922 .driver = {
1923 .owner = THIS_MODULE,
1924 },
1925 };
1926
1927 static int __devexit rtl8366_smi_remove(struct platform_device *pdev)
1928 {
1929 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1930
1931 if (smi) {
1932 struct rtl8366_smi_platform_data *pdata;
1933
1934 pdata = pdev->dev.platform_data;
1935
1936 rtl8366_smi_switch_cleanup(smi);
1937 rtl8366_debugfs_remove(smi);
1938 rtl8366_smi_mii_cleanup(smi);
1939 platform_set_drvdata(pdev, NULL);
1940 gpio_free(pdata->gpio_sck);
1941 gpio_free(pdata->gpio_sda);
1942 kfree(smi);
1943 }
1944
1945 return 0;
1946 }
1947
1948 static struct platform_driver rtl8366_smi_driver = {
1949 .driver = {
1950 .name = RTL8366_SMI_DRIVER_NAME,
1951 .owner = THIS_MODULE,
1952 },
1953 .probe = rtl8366_smi_probe,
1954 .remove = __devexit_p(rtl8366_smi_remove),
1955 };
1956
1957 static int __init rtl8366_smi_init(void)
1958 {
1959 int ret;
1960 ret = platform_driver_register(&rtl8366_smi_driver);
1961 if (ret)
1962 return ret;
1963
1964 ret = phy_driver_register(&rtl8366_smi_phy_driver);
1965 if (ret)
1966 goto err_platform_unregister;
1967
1968 return 0;
1969
1970 err_platform_unregister:
1971 platform_driver_unregister(&rtl8366_smi_driver);
1972 return ret;
1973 }
1974 module_init(rtl8366_smi_init);
1975
1976 static void __exit rtl8366_smi_exit(void)
1977 {
1978 phy_driver_unregister(&rtl8366_smi_phy_driver);
1979 platform_driver_unregister(&rtl8366_smi_driver);
1980 }
1981 module_exit(rtl8366_smi_exit);
1982
1983 MODULE_DESCRIPTION(RTL8366_SMI_DRIVER_DESC);
1984 MODULE_VERSION(RTL8366_SMI_DRIVER_VER);
1985 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1986 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1987 MODULE_LICENSE("GPL v2");
1988 MODULE_ALIAS("platform:" RTL8366_SMI_DRIVER_NAME);
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