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rtl8366_smi: reset the vlan table when resetting the switch and use vlan get/set...
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / phy / rtl8366_smi.c
1 /*
2 * Platform driver for the Realtek RTL8366 ethernet switch
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/gpio.h>
18 #include <linux/spinlock.h>
19 #include <linux/skbuff.h>
20 #include <linux/switch.h>
21 #include <linux/phy.h>
22 #include <linux/rtl8366_smi.h>
23
24 /* #define DEBUG 1 */
25
26 #ifdef DEBUG
27 #include <linux/debugfs.h>
28 #endif
29
30 #define RTL8366_SMI_DRIVER_NAME "rtl8366-smi"
31 #define RTL8366_SMI_DRIVER_DESC "Realtek RTL8366 switch driver"
32 #define RTL8366_SMI_DRIVER_VER "0.1.1"
33
34 #define RTL8366S_PHY_NO_MAX 4
35 #define RTL8366S_PHY_PAGE_MAX 7
36 #define RTL8366S_PHY_ADDR_MAX 31
37
38 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
39 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
40
41 #define RTL8366_RESET_CTRL_REG 0x0100
42 #define RTL8366_CHIP_CTRL_RESET_HW 1
43 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
44
45 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
46 #define RTL8366S_CHIP_VERSION_MASK 0xf
47 #define RTL8366S_CHIP_ID_REG 0x0105
48 #define RTL8366S_CHIP_ID_8366 0x8366
49
50 /* PHY registers control */
51 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
52 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
53
54 #define RTL8366S_PHY_CTRL_READ 1
55 #define RTL8366S_PHY_CTRL_WRITE 0
56
57 #define RTL8366S_PHY_REG_MASK 0x1f
58 #define RTL8366S_PHY_PAGE_OFFSET 5
59 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
60 #define RTL8366S_PHY_NO_OFFSET 9
61 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
62
63 #define RTL8366_SMI_ACK_RETRY_COUNT 5
64 #define RTL8366_SMI_CLK_DELAY 10 /* nsec */
65
66 /* LED control registers */
67 #define RTL8366_LED_BLINKRATE_REG 0x0420
68 #define RTL8366_LED_BLINKRATE_BIT 0
69 #define RTL8366_LED_BLINKRATE_MASK 0x0007
70
71 #define RTL8366_LED_CTRL_REG 0x0421
72 #define RTL8366_LED_0_1_CTRL_REG 0x0422
73 #define RTL8366_LED_2_3_CTRL_REG 0x0423
74
75 #define RTL8366S_MIB_COUNT 33
76 #define RTL8366S_GLOBAL_MIB_COUNT 1
77 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
78 #define RTL8366S_MIB_COUNTER_BASE 0x1000
79 #define RTL8366S_MIB_CTRL_REG 0x11F0
80 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
81 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
82 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
83
84 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
85 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
86 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
87
88
89 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
92
93 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
94
95 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
96 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
97 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
98
99 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
100
101
102 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
103 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
104 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
105 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
106 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
107 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
108 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
109
110
111 #define RTL8366_PORT_NUM_CPU 5
112 #define RTL8366_NUM_PORTS 6
113 #define RTL8366_NUM_VLANS 16
114 #define RTL8366_NUM_LEDGROUPS 4
115 #define RTL8366_NUM_VIDS 4096
116 #define RTL8366S_PRIORITYMAX 7
117 #define RTL8366S_FIDMAX 7
118
119
120 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
121 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
122 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
123 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
124
125 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
126 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
127
128 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
129 RTL8366_PORT_2 | \
130 RTL8366_PORT_3 | \
131 RTL8366_PORT_4 | \
132 RTL8366_PORT_UNKNOWN | \
133 RTL8366_PORT_CPU)
134
135 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
136 RTL8366_PORT_2 | \
137 RTL8366_PORT_3 | \
138 RTL8366_PORT_4 | \
139 RTL8366_PORT_UNKNOWN)
140
141 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
142 RTL8366_PORT_2 | \
143 RTL8366_PORT_3 | \
144 RTL8366_PORT_4)
145
146 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
147 RTL8366_PORT_CPU)
148
149 struct rtl8366s_vlanconfig {
150 u16 reserved2:1;
151 u16 priority:3;
152 u16 vid:12;
153
154 u16 reserved1:1;
155 u16 fid:3;
156 u16 untag:6;
157 u16 member:6;
158 };
159
160 struct rtl8366s_vlan4kentry {
161 u16 reserved1:4;
162 u16 vid:12;
163
164 u16 reserved2:1;
165 u16 fid:3;
166 u16 untag:6;
167 u16 member:6;
168 };
169
170 static const char *MIBCOUNTERS[] = { "IfInOctets ",
171 "EtherStatsOctets ",
172 "EtherStatsUnderSizePkts ",
173 "EtherFregament ",
174 "EtherStatsPkts64Octets ",
175 "EtherStatsPkts65to127Octets ",
176 "EtherStatsPkts128to255Octets ",
177 "EtherStatsPkts256to511Octets ",
178 "EtherStatsPkts512to1023Octets ",
179 "EtherStatsPkts1024to1518Octets ",
180 "EtherOversizeStats ",
181 "EtherStatsJabbers ",
182 "IfInUcastPkts ",
183 "EtherStatsMulticastPkts ",
184 "EtherStatsBroadcastPkts ",
185 "EtherStatsDropEvents ",
186 "Dot3StatsFCSErrors ",
187 "Dot3StatsSymbolErrors ",
188 "Dot3InPauseFrames ",
189 "Dot3ControlInUnknownOpcodes ",
190 "IfOutOctets ",
191 "Dot3StatsSingleCollisionFrames ",
192 "Dot3StatMultipleCollisionFrames ",
193 "Dot3sDeferredTransmissions ",
194 "Dot3StatsLateCollisions ",
195 "EtherStatsCollisions ",
196 "Dot3StatsExcessiveCollisions ",
197 "Dot3OutPauseFrames ",
198 "Dot1dBasePortDelayExceededDiscards",
199 "Dot1dTpPortInDiscards ",
200 "IfOutUcastPkts ",
201 "IfOutMulticastPkts ",
202 "IfOutBroadcastPkts ",
203 NULL };
204
205 struct rtl8366_smi {
206 struct platform_device *pdev;
207 struct rtl8366_smi_platform_data *pdata;
208 spinlock_t lock;
209 struct mii_bus *mii_bus;
210 struct switch_dev dev;
211 int mii_irq[PHY_MAX_ADDR];
212 char buf[4096];
213 #ifdef DEBUG
214 struct dentry *debugfs_root;
215 #endif
216 };
217
218 #ifdef DEBUG
219 u16 g_dbg_reg;
220 #endif
221
222 #define to_rtl8366(_dev) container_of(_dev, struct rtl8366_smi, dev)
223
224 static inline void rtl8366_smi_clk_delay(struct rtl8366_smi *smi)
225 {
226 ndelay(RTL8366_SMI_CLK_DELAY);
227 }
228
229 static void rtl8366_smi_start(struct rtl8366_smi *smi)
230 {
231 unsigned int sda = smi->pdata->gpio_sda;
232 unsigned int sck = smi->pdata->gpio_sck;
233
234 /*
235 * Set GPIO pins to output mode, with initial state:
236 * SCK = 0, SDA = 1
237 */
238 gpio_direction_output(sck, 0);
239 gpio_direction_output(sda, 1);
240 rtl8366_smi_clk_delay(smi);
241
242 /* CLK 1: 0 -> 1, 1 -> 0 */
243 gpio_set_value(sck, 1);
244 rtl8366_smi_clk_delay(smi);
245 gpio_set_value(sck, 0);
246 rtl8366_smi_clk_delay(smi);
247
248 /* CLK 2: */
249 gpio_set_value(sck, 1);
250 rtl8366_smi_clk_delay(smi);
251 gpio_set_value(sda, 0);
252 rtl8366_smi_clk_delay(smi);
253 gpio_set_value(sck, 0);
254 rtl8366_smi_clk_delay(smi);
255 gpio_set_value(sda, 1);
256 }
257
258 static void rtl8366_smi_stop(struct rtl8366_smi *smi)
259 {
260 unsigned int sda = smi->pdata->gpio_sda;
261 unsigned int sck = smi->pdata->gpio_sck;
262
263 rtl8366_smi_clk_delay(smi);
264 gpio_set_value(sda, 0);
265 gpio_set_value(sck, 1);
266 rtl8366_smi_clk_delay(smi);
267 gpio_set_value(sda, 1);
268 rtl8366_smi_clk_delay(smi);
269 gpio_set_value(sck, 1);
270 rtl8366_smi_clk_delay(smi);
271 gpio_set_value(sck, 0);
272 rtl8366_smi_clk_delay(smi);
273 gpio_set_value(sck, 1);
274
275 /* add a click */
276 rtl8366_smi_clk_delay(smi);
277 gpio_set_value(sck, 0);
278 rtl8366_smi_clk_delay(smi);
279 gpio_set_value(sck, 1);
280
281 /* set GPIO pins to input mode */
282 gpio_direction_input(sda);
283 gpio_direction_input(sck);
284 }
285
286 static void rtl8366_smi_write_bits(struct rtl8366_smi *smi, u32 data, u32 len)
287 {
288 unsigned int sda = smi->pdata->gpio_sda;
289 unsigned int sck = smi->pdata->gpio_sck;
290
291 for (; len > 0; len--) {
292 rtl8366_smi_clk_delay(smi);
293
294 /* prepare data */
295 if ( data & ( 1 << (len - 1)) )
296 gpio_set_value(sda, 1);
297 else
298 gpio_set_value(sda, 0);
299 rtl8366_smi_clk_delay(smi);
300
301 /* clocking */
302 gpio_set_value(sck, 1);
303 rtl8366_smi_clk_delay(smi);
304 gpio_set_value(sck, 0);
305 }
306 }
307
308 static void rtl8366_smi_read_bits(struct rtl8366_smi *smi, u32 len, u32 *data)
309 {
310 unsigned int sda = smi->pdata->gpio_sda;
311 unsigned int sck = smi->pdata->gpio_sck;
312
313 gpio_direction_input(sda);
314
315 for (*data = 0; len > 0; len--) {
316 u32 u;
317
318 rtl8366_smi_clk_delay(smi);
319
320 /* clocking */
321 gpio_set_value(sck, 1);
322 rtl8366_smi_clk_delay(smi);
323 u = gpio_get_value(sda);
324 gpio_set_value(sck, 0);
325
326 *data |= (u << (len - 1));
327 }
328
329 gpio_direction_output(sda, 0);
330 }
331
332 static int rtl8366_smi_wait_for_ack(struct rtl8366_smi *smi)
333 {
334 int retry_cnt;
335
336 retry_cnt = 0;
337 do {
338 u32 ack;
339
340 rtl8366_smi_read_bits(smi, 1, &ack);
341 if (ack == 0)
342 break;
343
344 if (++retry_cnt > RTL8366_SMI_ACK_RETRY_COUNT)
345 return -EIO;
346 } while (1);
347
348 return 0;
349 }
350
351 static int rtl8366_smi_write_byte(struct rtl8366_smi *smi, u8 data)
352 {
353 rtl8366_smi_write_bits(smi, data, 8);
354 return rtl8366_smi_wait_for_ack(smi);
355 }
356
357 static int rtl8366_smi_read_byte0(struct rtl8366_smi *smi, u8 *data)
358 {
359 u32 t;
360
361 /* read data */
362 rtl8366_smi_read_bits(smi, 8, &t);
363 *data = (t & 0xff);
364
365 /* send an ACK */
366 rtl8366_smi_write_bits(smi, 0x00, 1);
367
368 return 0;
369 }
370
371 static int rtl8366_smi_read_byte1(struct rtl8366_smi *smi, u8 *data)
372 {
373 u32 t;
374
375 /* read data */
376 rtl8366_smi_read_bits(smi, 8, &t);
377 *data = (t & 0xff);
378
379 /* send an ACK */
380 rtl8366_smi_write_bits(smi, 0x01, 1);
381
382 return 0;
383 }
384
385 static int rtl8366_smi_read_reg(struct rtl8366_smi *smi, u32 addr, u32 *data)
386 {
387 unsigned long flags;
388 u8 lo = 0;
389 u8 hi = 0;
390 int ret;
391
392 spin_lock_irqsave(&smi->lock, flags);
393
394 rtl8366_smi_start(smi);
395
396 /* send READ command */
397 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x01);
398 if (ret)
399 goto out;
400
401 /* set ADDR[7:0] */
402 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
403 if (ret)
404 goto out;
405
406 /* set ADDR[15:8] */
407 ret = rtl8366_smi_write_byte(smi, addr >> 8);
408 if (ret)
409 goto out;
410
411 /* read DATA[7:0] */
412 rtl8366_smi_read_byte0(smi, &lo);
413 /* read DATA[15:8] */
414 rtl8366_smi_read_byte1(smi, &hi);
415
416 *data = ((u32) lo) | (((u32) hi) << 8);
417
418 ret = 0;
419
420 out:
421 rtl8366_smi_stop(smi);
422 spin_unlock_irqrestore(&smi->lock, flags);
423
424 return ret;
425 }
426
427 static int rtl8366_smi_write_reg(struct rtl8366_smi *smi, u32 addr, u32 data)
428 {
429 unsigned long flags;
430 int ret;
431
432 spin_lock_irqsave(&smi->lock, flags);
433
434 rtl8366_smi_start(smi);
435
436 /* send WRITE command */
437 ret = rtl8366_smi_write_byte(smi, 0x0a << 4 | 0x04 << 1 | 0x00);
438 if (ret)
439 goto out;
440
441 /* set ADDR[7:0] */
442 ret = rtl8366_smi_write_byte(smi, addr & 0xff);
443 if (ret)
444 goto out;
445
446 /* set ADDR[15:8] */
447 ret = rtl8366_smi_write_byte(smi, addr >> 8);
448 if (ret)
449 goto out;
450
451 /* write DATA[7:0] */
452 ret = rtl8366_smi_write_byte(smi, data & 0xff);
453 if (ret)
454 goto out;
455
456 /* write DATA[15:8] */
457 ret = rtl8366_smi_write_byte(smi, data >> 8);
458 if (ret)
459 goto out;
460
461 ret = 0;
462
463 out:
464 rtl8366_smi_stop(smi);
465 spin_unlock_irqrestore(&smi->lock, flags);
466
467 return ret;
468 }
469
470 static int rtl8366_smi_read_phy_reg(struct rtl8366_smi *smi,
471 u32 phy_no, u32 page, u32 addr, u32 *data)
472 {
473 u32 reg;
474 int ret;
475
476 if (phy_no > RTL8366S_PHY_NO_MAX)
477 return -EINVAL;
478
479 if (page > RTL8366S_PHY_PAGE_MAX)
480 return -EINVAL;
481
482 if (addr > RTL8366S_PHY_ADDR_MAX)
483 return -EINVAL;
484
485 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
486 RTL8366S_PHY_CTRL_READ);
487 if (ret)
488 return ret;
489
490 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
491 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
492 (addr & RTL8366S_PHY_REG_MASK);
493
494 ret = rtl8366_smi_write_reg(smi, reg, 0);
495 if (ret)
496 return ret;
497
498 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
499 if (ret)
500 return ret;
501
502 return 0;
503 }
504
505 static int rtl8366_smi_write_phy_reg(struct rtl8366_smi *smi,
506 u32 phy_no, u32 page, u32 addr, u32 data)
507 {
508 u32 reg;
509 int ret;
510
511 if (phy_no > RTL8366S_PHY_NO_MAX)
512 return -EINVAL;
513
514 if (page > RTL8366S_PHY_PAGE_MAX)
515 return -EINVAL;
516
517 if (addr > RTL8366S_PHY_ADDR_MAX)
518 return -EINVAL;
519
520 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
521 RTL8366S_PHY_CTRL_WRITE);
522 if (ret)
523 return ret;
524
525 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
526 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
527 (addr & RTL8366S_PHY_REG_MASK);
528
529 ret = rtl8366_smi_write_reg(smi, reg, data);
530 if (ret)
531 return ret;
532
533 return 0;
534 }
535
536 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
537 int port, unsigned long long *val)
538 {
539 int i;
540 int err;
541 u32 addr, data, regoffset;
542 u64 mibvalue;
543
544 /* address offset to MIBs counter */
545 const u16 mibLength[RTL8366S_MIB_COUNT] = {4, 4, 2, 2, 2, 2, 2, 2, 2,
546 2, 2, 2, 2, 2, 2, 2, 2, 2,
547 2, 2, 4, 2, 2, 2, 2, 2, 2,
548 2, 2, 2, 2, 2, 2};
549
550 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
551 return -EINVAL;
552
553 i = 0;
554 regoffset = RTL8366S_MIB_COUNTER_PORT_OFFSET * (port);
555
556 while (i < counter) {
557 regoffset += mibLength[i];
558 i++;
559 }
560
561 addr = RTL8366S_MIB_COUNTER_BASE + regoffset;
562
563
564 /* writing access counter address first */
565 /* then ASIC will prepare 64bits counter wait for being retrived */
566 data = 0;/* writing data will be discard by ASIC */
567 err = rtl8366_smi_write_reg(smi, addr, data);
568 if (err)
569 return err;
570
571 /* read MIB control register */
572 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
573 if (err)
574 return err;
575
576 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
577 return -EBUSY;
578
579 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
580 return -EIO;
581
582 mibvalue = 0;
583 addr = addr + mibLength[counter] - 1;
584 i = mibLength[counter];
585
586 while (i) {
587 err = rtl8366_smi_read_reg(smi, addr, &data);
588 if (err)
589 return err;
590
591 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
592
593 addr--;
594 i--;
595 }
596
597 *val = mibvalue;
598 return 0;
599 }
600
601 static int rtl8366s_get_vlan_4k_entry(struct rtl8366_smi *smi, u32 vid,
602 struct rtl8366s_vlan4kentry *vlan4k)
603 {
604 int err;
605 u32 data;
606 u16 *tableaddr;
607
608 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
609 vlan4k->vid = vid;
610
611 if (vid >= RTL8366_NUM_VIDS)
612 return -EINVAL;
613
614 tableaddr = (u16 *)vlan4k;
615
616 /* write VID */
617 data = *tableaddr;
618 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
619 if (err)
620 return err;
621
622 /* write table access control word */
623 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
624 RTL8366S_TABLE_VLAN_READ_CTRL);
625 if (err)
626 return err;
627
628 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
629 if (err)
630 return err;
631
632 *tableaddr = data;
633 tableaddr++;
634
635 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
636 &data);
637 if (err)
638 return err;
639
640 *tableaddr = data;
641 vlan4k->vid = vid;
642
643 return 0;
644 }
645
646 static int rtl8366s_set_vlan_4k_entry(struct rtl8366_smi *smi,
647 const struct rtl8366s_vlan4kentry *vlan4k)
648 {
649 int err;
650 u32 data;
651 u16 *tableaddr;
652
653 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
654 vlan4k->member > RTL8366_PORT_ALL ||
655 vlan4k->untag > RTL8366_PORT_ALL ||
656 vlan4k->fid > RTL8366S_FIDMAX)
657 return -EINVAL;
658
659 tableaddr = (u16 *)vlan4k;
660
661 data = *tableaddr;
662
663 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
664 if (err)
665 return err;
666
667 tableaddr++;
668
669 data = *tableaddr;
670
671 rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1, data);
672
673
674 /* write table access control word */
675 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
676 RTL8366S_TABLE_VLAN_WRITE_CTRL);
677 if (err)
678 return err;
679
680 return 0;
681 }
682
683 static int rtl8366s_get_vlan_member_config(struct rtl8366_smi *smi, u32 index,
684 struct rtl8366s_vlanconfig *vlanmc)
685 {
686 int err;
687 u32 addr;
688 u32 data;
689 u16 *tableaddr;
690
691 memset(vlanmc, '\0', sizeof(struct rtl8366s_vlanconfig));
692
693 if (index >= RTL8366_NUM_VLANS)
694 return -EINVAL;
695
696 tableaddr = (u16 *)vlanmc;
697
698 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
699
700 err = rtl8366_smi_read_reg(smi, addr, &data);
701 if (err)
702 return err;
703
704 *tableaddr = data;
705 tableaddr++;
706
707 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
708
709 err = rtl8366_smi_read_reg(smi, addr, &data);
710 if (err)
711 return err;
712
713 *tableaddr = data;
714
715 return 0;
716 }
717
718 static int rtl8366s_set_vlan_member_config(struct rtl8366_smi *smi, u32 index,
719 const struct rtl8366s_vlanconfig
720 *vlanmc)
721 {
722 int err;
723 u32 addr;
724 u32 data;
725 u16 *tableaddr;
726
727 if (index >= RTL8366_NUM_VLANS ||
728 vlanmc->vid >= RTL8366_NUM_VIDS ||
729 vlanmc->priority > RTL8366S_PRIORITYMAX ||
730 vlanmc->member > RTL8366_PORT_ALL ||
731 vlanmc->untag > RTL8366_PORT_ALL ||
732 vlanmc->fid > RTL8366S_FIDMAX)
733 return -EINVAL;
734
735 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
736
737
738 tableaddr = (u16 *)vlanmc;
739 data = *tableaddr;
740
741 err = rtl8366_smi_write_reg(smi, addr, data);
742 if (err)
743 return err;
744
745 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
746
747 tableaddr++;
748 data = *tableaddr;
749
750 err = rtl8366_smi_write_reg(smi, addr, data);
751 if (err)
752 return err;
753
754 return 0;
755 }
756
757 static int rtl8366_get_port_vlan_index(struct rtl8366_smi *smi, int port,
758 int *val)
759 {
760 int err;
761 u32 addr;
762 u32 data;
763
764 /* bits mapping to port vlan control register of port n */
765 const u16 bits[RTL8366_NUM_PORTS] = { 0x000F, 0x00F0, 0x0F00,
766 0xF000, 0x000F, 0x00F0 };
767 /* bits offset to port vlan control register of port n */
768 const u16 bitoffset[RTL8366_NUM_PORTS] = { 0, 4, 8, 12, 0, 4 };
769 /* address offset to port vlan control register of port n */
770 const u16 addroffset[RTL8366_NUM_PORTS] = { 0, 0, 0, 0, 1, 1 };
771
772 if (port >= RTL8366_NUM_PORTS)
773 return -EINVAL;
774
775 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addroffset[port];
776
777 err = rtl8366_smi_read_reg(smi, addr, &data);
778 if (err)
779 return err;
780
781 *val = (data & bits[port]) >> bitoffset[port];
782
783 return 0;
784
785 }
786
787 static int rtl8366_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
788 int *val)
789 {
790 int err;
791 int index;
792 struct rtl8366s_vlanconfig vlanmc;
793
794 err = rtl8366_get_port_vlan_index(smi, port, &index);
795 if (err)
796 return err;
797
798 err = rtl8366s_get_vlan_member_config(smi, index, &vlanmc);
799 if (err)
800 return err;
801
802 *val = vlanmc.vid;
803 return 0;
804 }
805
806 static int rtl8366_set_port_vlan_index(struct rtl8366_smi *smi, int port,
807 int index)
808 {
809 int err;
810 u32 addr;
811 u32 data;
812 u32 vlan_data;
813 u32 bits;
814
815 /* bits mapping to port vlan control register of port n */
816 const u16 bitmasks[6] = { 0x000F, 0x00F0, 0x0F00,
817 0xF000, 0x000F, 0x00F0 };
818 /* bits offset to port vlan control register of port n */
819 const u16 bitOff[6] = { 0, 4, 8, 12, 0, 4 };
820 /* address offset to port vlan control register of port n */
821 const u16 addrOff[6] = { 0, 0, 0, 0, 1, 1 };
822
823 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
824 return -EINVAL;
825
826 addr = RTL8366S_PORT_VLAN_CTRL_BASE + addrOff[port];
827
828 bits = bitmasks[port];
829
830 data = (index << bitOff[port]) & bits;
831
832 err = rtl8366_smi_read_reg(smi, addr, &vlan_data);
833 if (err)
834 return err;
835
836 vlan_data &= ~(vlan_data & bits);
837 vlan_data |= data;
838
839 err = rtl8366_smi_write_reg(smi, addr, vlan_data);
840 if (err)
841 return err;
842
843 return 0;
844 }
845
846 static int rtl8366_set_vlan_port_pvid(struct rtl8366_smi *smi, int port,
847 int val)
848 {
849 int i;
850 struct rtl8366s_vlanconfig vlanmc;
851 struct rtl8366s_vlan4kentry vlan4k;
852
853 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
854 return -EINVAL;
855
856
857
858 /* Updating the 4K entry; lookup it and change the port member set */
859 rtl8366s_get_vlan_4k_entry(smi, val, &vlan4k);
860 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
861 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
862 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
863
864 /* For the 16 entries more work needs to be done. First see if such
865 VID is already there and change it */
866 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
867 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
868
869 /* Try to find an existing vid and update port member set */
870 if (val == vlanmc.vid) {
871 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
872 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
873
874 /* Now update PVID register settings */
875 rtl8366_set_port_vlan_index(smi, port, i);
876
877 return 0;
878 }
879 }
880
881 /* PVID could not be found from vlan table. Replace unused (one that
882 has no member ports) with new one */
883 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
884 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
885
886 /* See if this vlan member configuration is unused. It is
887 unused if member set contains no ports or CPU port only */
888 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
889 vlanmc.vid = val;
890 vlanmc.priority = 0;
891 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
892 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
893 vlanmc.fid = 0;
894
895 rtl8366s_set_vlan_member_config(smi, i, &vlanmc);
896
897 /* Now update PVID register settings */
898 rtl8366_set_port_vlan_index(smi, port, i);
899
900 return 0;
901 }
902 }
903
904 dev_err(&smi->pdev->dev, "All 16 vlan member configurations are in "
905 "use\n");
906 return -EINVAL;
907 }
908
909
910 static int rtl8366_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
911 {
912 u32 data = 0;
913 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
914
915 data &= ~(data & RTL8366_CHIP_CTRL_VLAN);
916 if (enable)
917 data |= RTL8366_CHIP_CTRL_VLAN;
918
919 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
920 }
921
922 static int rtl8366_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
923 {
924 u32 data = 0;
925 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
926
927 data &= ~(data & 1);
928 if (enable)
929 data |= 1;
930
931 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
932 }
933
934 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
935 {
936 int i;
937 struct rtl8366s_vlan4kentry vlan4k;
938 struct rtl8366s_vlanconfig vlanmc;
939
940 /* clear 16 VLAN member configuration */
941 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
942 vlanmc.vid = 0;
943 vlanmc.priority = 0;
944 vlanmc.member = 0;
945 vlanmc.untag = 0;
946 vlanmc.fid = 0;
947 if (rtl8366s_set_vlan_member_config(smi, i, &vlanmc) != 0)
948 return -EIO;
949 }
950
951 /* Set a default VLAN with vid 1 to 4K table for all ports */
952 vlan4k.vid = 1;
953 vlan4k.member = RTL8366_PORT_ALL;
954 vlan4k.untag = RTL8366_PORT_ALL;
955 vlan4k.fid = 0;
956 if (rtl8366s_set_vlan_4k_entry(smi, &vlan4k) != 0)
957 return -EIO;
958
959 /* Set all ports PVID to default VLAN */
960 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
961 if (rtl8366_set_vlan_port_pvid(smi, i, 0) != 0)
962 return -EIO;
963 }
964
965 return 0;
966 }
967
968 #ifdef DEBUG
969 static int rtl8366_debugfs_open(struct inode *inode, struct file *file)
970 {
971 file->private_data = inode->i_private;
972 return 0;
973 }
974
975 static ssize_t rtl8366_read_debugfs_mibs(struct file *file,
976 char __user *user_buf,
977 size_t count, loff_t *ppos)
978 {
979 int i, j, len = 0;
980 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
981 char *buf = smi->buf;
982
983 len += snprintf(buf + len, sizeof(smi->buf) - len, "MIB Counters:\n");
984 len += snprintf(buf + len, sizeof(smi->buf) - len, "Counter"
985 " "
986 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
987 "Port 4\n");
988
989 for (i = 0; i < 33; ++i) {
990
991 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d:%s ",
992 i, MIBCOUNTERS[i]);
993 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
994 unsigned long long counter = 0;
995
996 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
997 len += snprintf(buf + len, sizeof(smi->buf) - len,
998 "[%llu]", counter);
999 else
1000 len += snprintf(buf + len, sizeof(smi->buf) - len,
1001 "[error]");
1002
1003 if (j != RTL8366_NUM_PORTS - 1) {
1004 if (counter < 100000)
1005 len += snprintf(buf + len,
1006 sizeof(smi->buf) - len,
1007 "\t");
1008
1009 len += snprintf(buf + len, sizeof(smi->buf) - len,
1010 "\t");
1011 }
1012 }
1013 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1014 }
1015
1016 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1017
1018 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1019 }
1020
1021 static ssize_t rtl8366_read_debugfs_vlan(struct file *file,
1022 char __user *user_buf,
1023 size_t count, loff_t *ppos)
1024 {
1025 int i, j, len = 0;
1026 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1027 char *buf = smi->buf;
1028
1029 len += snprintf(buf + len, sizeof(smi->buf) - len, "VLAN Member Config:\n");
1030 len += snprintf(buf + len, sizeof(smi->buf) - len,
1031 "\t id \t vid \t prio \t member \t untag \t fid "
1032 "\tports\n");
1033
1034 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
1035 struct rtl8366s_vlanconfig vlanmc;
1036
1037 rtl8366s_get_vlan_member_config(smi, i, &vlanmc);
1038
1039 len += snprintf(buf + len, sizeof(smi->buf) - len,
1040 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
1041 "\t", i, vlanmc.vid, vlanmc.priority,
1042 vlanmc.member, vlanmc.untag, vlanmc.fid);
1043
1044 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
1045 int index = 0;
1046 if (!rtl8366_get_port_vlan_index(smi, j, &index)) {
1047 if (index == i)
1048 len += snprintf(buf + len,
1049 sizeof(smi->buf) - len,
1050 "%d", j);
1051 }
1052 }
1053 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1054 }
1055
1056 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1057 }
1058
1059 static ssize_t rtl8366_read_debugfs_reg(struct file *file,
1060 char __user *user_buf,
1061 size_t count, loff_t *ppos)
1062 {
1063 u32 t, reg = g_dbg_reg;
1064 int err, len = 0;
1065 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1066 char *buf = smi->buf;
1067
1068 memset(buf, '\0', sizeof(smi->buf));
1069
1070 err = rtl8366_smi_read_reg(smi, reg, &t);
1071 if (err) {
1072 len += snprintf(buf, sizeof(smi->buf),
1073 "Read failed (reg: 0x%04x)\n", reg);
1074 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1075 }
1076
1077 len += snprintf(buf, sizeof(smi->buf), "reg = 0x%04x, val = 0x%04x\n",
1078 reg, t);
1079
1080 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
1081 }
1082
1083 static ssize_t rtl8366_write_debugfs_reg(struct file *file,
1084 const char __user *user_buf,
1085 size_t count, loff_t *ppos)
1086 {
1087 unsigned long data;
1088 u32 reg = g_dbg_reg;
1089 int err;
1090 size_t len;
1091 struct rtl8366_smi *smi = (struct rtl8366_smi *)file->private_data;
1092 char *buf = smi->buf;
1093
1094 len = min(count, sizeof(smi->buf) - 1);
1095 if (copy_from_user(buf, user_buf, len)) {
1096 dev_err(&smi->pdev->dev, "copy from user failed\n");
1097 return -EFAULT;
1098 }
1099
1100 buf[len] = '\0';
1101 if (len > 0 && buf[len - 1] == '\n')
1102 buf[len - 1] = '\0';
1103
1104
1105 if (strict_strtoul(buf, 16, &data)) {
1106 dev_err(&smi->pdev->dev, "Invalid reg value %s\n", buf);
1107 } else {
1108 err = rtl8366_smi_write_reg(smi, reg, data);
1109 if (err) {
1110 dev_err(&smi->pdev->dev,
1111 "writing reg 0x%04x val 0x%04lx failed\n",
1112 reg, data);
1113 }
1114 }
1115
1116 return count;
1117 }
1118
1119 static const struct file_operations fops_rtl8366_regs = {
1120 .read = rtl8366_read_debugfs_reg,
1121 .write = rtl8366_write_debugfs_reg,
1122 .open = rtl8366_debugfs_open,
1123 .owner = THIS_MODULE
1124 };
1125
1126 static const struct file_operations fops_rtl8366_vlan = {
1127 .read = rtl8366_read_debugfs_vlan,
1128 .open = rtl8366_debugfs_open,
1129 .owner = THIS_MODULE
1130 };
1131
1132 static const struct file_operations fops_rtl8366_mibs = {
1133 .read = rtl8366_read_debugfs_mibs,
1134 .open = rtl8366_debugfs_open,
1135 .owner = THIS_MODULE
1136 };
1137
1138 static void rtl8366_debugfs_init(struct rtl8366_smi *smi)
1139 {
1140 struct dentry *node;
1141 struct dentry *root;
1142
1143 if (!smi->debugfs_root)
1144 smi->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
1145
1146 if (!smi->debugfs_root) {
1147 dev_err(&smi->pdev->dev, "Unable to create debugfs dir\n");
1148 return;
1149 }
1150 root = smi->debugfs_root;
1151
1152 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
1153 if (!node) {
1154 dev_err(&smi->pdev->dev, "Creating debugfs file reg failed\n");
1155 return;
1156 }
1157
1158 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, smi,
1159 &fops_rtl8366_regs);
1160 if (!node) {
1161 dev_err(&smi->pdev->dev, "Creating debugfs file val failed\n");
1162 return;
1163 }
1164
1165 node = debugfs_create_file("vlan", S_IRUSR, root, smi,
1166 &fops_rtl8366_vlan);
1167 if (!node) {
1168 dev_err(&smi->pdev->dev, "Creating debugfs file vlan "
1169 "failed\n");
1170 return;
1171 }
1172
1173 node = debugfs_create_file("mibs", S_IRUSR, root, smi,
1174 &fops_rtl8366_mibs);
1175 if (!node) {
1176 dev_err(&smi->pdev->dev, "Creating debugfs file mibs "
1177 "xfailed\n");
1178 return;
1179 }
1180 }
1181
1182 static void rtl8366_debugfs_remove(struct rtl8366_smi *smi)
1183 {
1184 if (smi->debugfs_root) {
1185 debugfs_remove_recursive(smi->debugfs_root);
1186 smi->debugfs_root = NULL;
1187 }
1188 }
1189
1190 #else
1191 static inline void rtl8366_debugfs_init(struct rtl8366_smi *smi) {}
1192 static inline void rtl8366_debugfs_remove(struct rtl8366_smi *smi) {}
1193 #endif
1194
1195 static int rtl8366_global_reset_mibs(struct switch_dev *dev,
1196 const struct switch_attr *attr,
1197 struct switch_val *val)
1198 {
1199 u32 data = 0;
1200 struct rtl8366_smi *smi = to_rtl8366(dev);
1201
1202 if (val->value.i == 1) {
1203 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1204 data |= (1 << 2);
1205 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1206 }
1207
1208 return 0;
1209 }
1210
1211 static int rtl8366_get_vlan(struct switch_dev *dev,
1212 const struct switch_attr *attr,
1213 struct switch_val *val)
1214 {
1215 u32 data;
1216 struct rtl8366_smi *smi = to_rtl8366(dev);
1217
1218 if (attr->ofs == 1) {
1219 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1220
1221 if (data & RTL8366_CHIP_CTRL_VLAN)
1222 val->value.i = 1;
1223 else
1224 val->value.i = 0;
1225 } else if (attr->ofs == 2) {
1226 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1227
1228 if (data & 0x0001)
1229 val->value.i = 1;
1230 else
1231 val->value.i = 0;
1232 }
1233
1234 return 0;
1235 }
1236
1237 static int rtl8366_global_get_blinkrate(struct switch_dev *dev,
1238 const struct switch_attr *attr,
1239 struct switch_val *val)
1240 {
1241 u32 data;
1242 struct rtl8366_smi *smi = to_rtl8366(dev);
1243 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1244
1245 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1246
1247 return 0;
1248 }
1249
1250 static int rtl8366_global_set_blinkrate(struct switch_dev *dev,
1251 const struct switch_attr *attr,
1252 struct switch_val *val)
1253 {
1254 u32 data;
1255 struct rtl8366_smi *smi = to_rtl8366(dev);
1256
1257 if (val->value.i >= 6)
1258 return -EINVAL;
1259
1260 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1261
1262 data &= ~(data & RTL8366_LED_BLINKRATE_MASK);
1263 data |= val->value.i;
1264
1265 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1266
1267 return 0;
1268 }
1269
1270 static int rtl8366_set_vlan(struct switch_dev *dev,
1271 const struct switch_attr *attr,
1272 struct switch_val *val)
1273 {
1274 struct rtl8366_smi *smi = to_rtl8366(dev);
1275
1276 if (attr->ofs == 1)
1277 return rtl8366_vlan_set_vlan(smi, val->value.i);
1278 else
1279 return rtl8366_vlan_set_4ktable(smi, val->value.i);
1280 }
1281
1282 static int rtl8366_attr_get_port_link(struct switch_dev *dev,
1283 const struct switch_attr *attr,
1284 struct switch_val *val)
1285 {
1286 u32 len = 0, data = 0;
1287 int speed, duplex, link, txpause, rxpause, nway;
1288 struct rtl8366_smi *smi = to_rtl8366(dev);
1289 char *buf = smi->buf;
1290
1291 if (val->port_vlan >= RTL8366_NUM_PORTS)
1292 return -EINVAL;
1293
1294 memset(buf, '\0', sizeof(smi->buf));
1295 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1296 (val->port_vlan >> 1),
1297 &data);
1298
1299 if (val->port_vlan & 0x1)
1300 data = data >> 8;
1301
1302 speed = (data & RTL8366S_PORT_STATUS_SPEED_MASK);
1303 duplex = (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) >> 2;
1304 link = (data & RTL8366S_PORT_STATUS_LINK_MASK) >> 4;
1305 txpause = (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) >> 5;
1306 rxpause = (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) >> 6;
1307 nway = (data & RTL8366S_PORT_STATUS_AN_MASK) >> 7;
1308
1309 len += snprintf(buf + len, sizeof(smi->buf) - len, "Port %d: ",
1310 val->port_vlan);
1311
1312 if (link)
1313 len += snprintf(buf + len, sizeof(smi->buf) - len,
1314 "Link UP, Speed: ");
1315 else
1316 len += snprintf(buf + len, sizeof(smi->buf) - len,
1317 "Link DOWN, Speed: ");
1318
1319 if (speed == 0)
1320 len += snprintf(buf + len, sizeof(smi->buf) - len, "10Base-TX ");
1321 else if (speed == 1)
1322 len += snprintf(buf + len, sizeof(smi->buf) - len, "100Base-TX ");
1323 else if (speed == 2)
1324 len += snprintf(buf + len, sizeof(smi->buf) - len, "1000Base-TX ");
1325
1326 if (duplex)
1327 len += snprintf(buf + len, sizeof(smi->buf) - len, "Full-Duplex, ");
1328 else
1329 len += snprintf(buf + len, sizeof(smi->buf) - len, "Half-Duplex, ");
1330
1331 if (txpause)
1332 len += snprintf(buf + len, sizeof(smi->buf) - len, "TX-Pause ");
1333 if (rxpause)
1334 len += snprintf(buf + len, sizeof(smi->buf) - len, "RX-Pause ");
1335 if (nway)
1336 len += snprintf(buf + len, sizeof(smi->buf) - len, "nway ");
1337
1338 val->value.s = buf;
1339 val->len = len;
1340
1341 return 0;
1342 }
1343
1344 static int rtl8366_attr_get_vlan_info(struct switch_dev *dev,
1345 const struct switch_attr *attr,
1346 struct switch_val *val)
1347 {
1348 int i;
1349 u32 len = 0;
1350 struct rtl8366s_vlanconfig vlanmc;
1351 struct rtl8366s_vlan4kentry vlan4k;
1352 struct rtl8366_smi *smi = to_rtl8366(dev);
1353 char *buf = smi->buf;
1354
1355 if (val->port_vlan >= RTL8366_NUM_PORTS)
1356 return -EINVAL;
1357
1358 memset(buf, '\0', sizeof(smi->buf));
1359
1360 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1361 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1362
1363 len += snprintf(buf + len, sizeof(smi->buf) - len, "VLAN %d: Ports: ",
1364 val->port_vlan);
1365
1366 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1367 int index = 0;
1368 if (!rtl8366_get_port_vlan_index(smi, i, &index) &&
1369 index == val->port_vlan)
1370 len += snprintf(buf + len, sizeof(smi->buf) - len, "%d", i);
1371 }
1372 len += snprintf(buf + len, sizeof(smi->buf) - len, "\n");
1373
1374 len += snprintf(buf + len, sizeof(smi->buf) - len,
1375 "\t\t vid \t prio \t member \t untag \t fid\n");
1376 len += snprintf(buf + len, sizeof(smi->buf) - len, "\tMC:\t");
1377 len += snprintf(buf + len, sizeof(smi->buf) - len,
1378 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1379 vlanmc.vid, vlanmc.priority, vlanmc.member,
1380 vlanmc.untag, vlanmc.fid);
1381 len += snprintf(buf + len, sizeof(smi->buf) - len, "\t4K:\t");
1382 len += snprintf(buf + len, sizeof(smi->buf) - len,
1383 "%d \t \t 0x%04x \t 0x%04x \t %d",
1384 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1385
1386 val->value.s = buf;
1387 val->len = len;
1388
1389 return 0;
1390 }
1391
1392 static int rtl8366_set_port_led(struct switch_dev *dev,
1393 const struct switch_attr *attr,
1394 struct switch_val *val)
1395 {
1396 u32 data = 0;
1397 struct rtl8366_smi *smi = to_rtl8366(dev);
1398 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1399 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1400 return -EINVAL;
1401
1402 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1403 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1404 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1405 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1406 } else {
1407 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1408 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1409 (val->value.i << (val->port_vlan * 4));
1410 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1411 }
1412
1413 return 0;
1414 }
1415
1416 static int rtl8366_get_port_led(struct switch_dev *dev,
1417 const struct switch_attr *attr,
1418 struct switch_val *val)
1419 {
1420 u32 data = 0;
1421 struct rtl8366_smi *smi = to_rtl8366(dev);
1422 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1423 return -EINVAL;
1424
1425 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1426 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1427
1428 return 0;
1429 }
1430
1431 static int rtl8366_reset_port_mibs(struct switch_dev *dev,
1432 const struct switch_attr *attr,
1433 struct switch_val *val)
1434 {
1435 u32 data = 0;
1436 struct rtl8366_smi *smi = to_rtl8366(dev);
1437 if (val->port_vlan >= RTL8366_NUM_PORTS)
1438 return -EINVAL;
1439
1440 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1441 data |= (1 << (val->port_vlan + 3));
1442 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1443
1444 return 0;
1445 }
1446
1447 static int rtl8366_get_port_mib(struct switch_dev *dev,
1448 const struct switch_attr *attr,
1449 struct switch_val *val)
1450 {
1451 int i, len = 0;
1452 unsigned long long counter = 0;
1453 struct rtl8366_smi *smi = to_rtl8366(dev);
1454 char *buf = smi->buf;
1455
1456 if (val->port_vlan >= RTL8366_NUM_PORTS)
1457 return -EINVAL;
1458
1459 len += snprintf(buf + len, sizeof(smi->buf) - len, "Port %d MIB counters\n",
1460 val->port_vlan);
1461 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1462
1463 len += snprintf(buf + len, sizeof(smi->buf) - len,
1464 "%d:%s\t", i, MIBCOUNTERS[i]);
1465 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1466 len += snprintf(buf + len, sizeof(smi->buf) - len,
1467 "[%llu]\n", counter);
1468 else
1469 len += snprintf(buf + len, sizeof(smi->buf) - len,
1470 "[error]\n");
1471 }
1472
1473 val->value.s = buf;
1474 val->len = len;
1475 return 0;
1476 }
1477
1478 static int rtl8366_get_ports(struct switch_dev *dev,
1479 struct switch_val *val)
1480 {
1481 struct rtl8366s_vlanconfig vlanmc;
1482 struct rtl8366_smi *smi = to_rtl8366(dev);
1483 struct switch_port *port;
1484 int i;
1485
1486 if (val->port_vlan >= RTL8366_NUM_VLANS)
1487 return -EINVAL;
1488
1489 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1490
1491 port = &val->value.ports[0];
1492 val->len = 0;
1493 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1494 if (!(vlanmc.member & BIT(i)))
1495 continue;
1496
1497 port->id = i;
1498 port->flags = vlanmc.untag ? 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1499 val->len++;
1500 port++;
1501 }
1502 return 0;
1503 }
1504
1505 static int rtl8366_set_ports(struct switch_dev *dev,
1506 struct switch_val *val)
1507 {
1508 struct rtl8366s_vlanconfig vlanmc;
1509 struct rtl8366s_vlan4kentry vlan4k;
1510 struct rtl8366_smi *smi = to_rtl8366(dev);
1511 struct switch_port *port;
1512 int i;
1513
1514 if (val->port_vlan >= RTL8366_NUM_VLANS)
1515 return -EINVAL;
1516
1517 rtl8366s_get_vlan_member_config(smi, val->port_vlan, &vlanmc);
1518 rtl8366s_get_vlan_4k_entry(smi, vlanmc.vid, &vlan4k);
1519
1520 vlanmc.untag = 0;
1521 vlanmc.member = 0;
1522
1523 port = &val->value.ports[0];
1524 for (i = 0; i < val->len; i++, port++) {
1525 vlanmc.member |= BIT(port->id);
1526
1527 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1528 vlanmc.untag |= BIT(port->id);
1529 }
1530
1531 vlan4k.member = vlanmc.member;
1532 vlan4k.untag = vlanmc.untag;
1533
1534 rtl8366s_set_vlan_member_config(smi, val->port_vlan, &vlanmc);
1535 rtl8366s_set_vlan_4k_entry(smi, &vlan4k);
1536 return 0;
1537 }
1538
1539 static int rtl8366_get_port_pvid(struct switch_dev *dev, int port, int *val)
1540 {
1541 struct rtl8366_smi *smi = to_rtl8366(dev);
1542 return rtl8366_get_vlan_port_pvid(smi, port, val);
1543 }
1544
1545 static int rtl8366_set_port_pvid(struct switch_dev *dev, int port, int val)
1546 {
1547 struct rtl8366_smi *smi = to_rtl8366(dev);
1548 return rtl8366_set_vlan_port_pvid(smi, port, val);
1549 }
1550
1551 static int rtl8366_reset_switch(struct switch_dev *dev)
1552 {
1553 struct rtl8366_smi *smi = to_rtl8366(dev);
1554 int timeout = 10;
1555 u32 data;
1556
1557 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
1558 RTL8366_CHIP_CTRL_RESET_HW);
1559 do {
1560 msleep(1);
1561 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
1562 return -EIO;
1563
1564 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
1565 break;
1566 } while (--timeout);
1567
1568 if (!timeout) {
1569 printk("Timeout waiting for the switch to reset\n");
1570 return -EIO;
1571 }
1572
1573 return rtl8366s_reset_vlan(smi);
1574 }
1575
1576 static struct switch_attr rtl8366_globals[] = {
1577 {
1578 .type = SWITCH_TYPE_INT,
1579 .name = "enable_vlan",
1580 .description = "Enable VLAN mode",
1581 .set = rtl8366_set_vlan,
1582 .get = rtl8366_get_vlan,
1583 .max = 1,
1584 .ofs = 1
1585 },
1586 {
1587 .type = SWITCH_TYPE_INT,
1588 .name = "enable_vlan4k",
1589 .description = "Enable VLAN 4K mode",
1590 .set = rtl8366_set_vlan,
1591 .get = rtl8366_get_vlan,
1592 .max = 1,
1593 .ofs = 2
1594 },
1595 {
1596 .type = SWITCH_TYPE_INT,
1597 .name = "reset_mibs",
1598 .description = "Reset all MIB counters",
1599 .set = rtl8366_global_reset_mibs,
1600 .get = NULL,
1601 .max = 1
1602 },
1603 {
1604 .type = SWITCH_TYPE_INT,
1605 .name = "blinkrate",
1606 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1607 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1608 .set = rtl8366_global_set_blinkrate,
1609 .get = rtl8366_global_get_blinkrate,
1610 .max = 5
1611 },
1612 };
1613
1614 static struct switch_attr rtl8366_port[] = {
1615 {
1616 .type = SWITCH_TYPE_STRING,
1617 .name = "link",
1618 .description = "Get port link information",
1619 .max = 1,
1620 .set = NULL,
1621 .get = rtl8366_attr_get_port_link
1622 },
1623 {
1624 .type = SWITCH_TYPE_INT,
1625 .name = "reset_mib",
1626 .description = "Reset single port MIB counters",
1627 .max = 1,
1628 .set = rtl8366_reset_port_mibs,
1629 .get = NULL
1630 },
1631 {
1632 .type = SWITCH_TYPE_STRING,
1633 .name = "mib",
1634 .description = "Get MIB counters for port",
1635 .max = 33,
1636 .set = NULL,
1637 .get = rtl8366_get_port_mib
1638 },
1639 {
1640 .type = SWITCH_TYPE_INT,
1641 .name = "led",
1642 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1643 .max = 15,
1644 .set = rtl8366_set_port_led,
1645 .get = rtl8366_get_port_led
1646 },
1647 };
1648
1649 static struct switch_attr rtl8366_vlan[] = {
1650 {
1651 .type = SWITCH_TYPE_STRING,
1652 .name = "info",
1653 .description = "Get vlan information",
1654 .max = 1,
1655 .set = NULL,
1656 .get = rtl8366_attr_get_vlan_info
1657 },
1658 };
1659
1660
1661 /* template */
1662 static struct switch_dev rtldev = {
1663 .name = "RTL8366S",
1664 .cpu_port = RTL8366_PORT_NUM_CPU,
1665 .ports = RTL8366_NUM_PORTS,
1666 .vlans = RTL8366_NUM_VLANS,
1667 .attr_global = {
1668 .attr = rtl8366_globals,
1669 .n_attr = ARRAY_SIZE(rtl8366_globals),
1670 },
1671 .attr_port = {
1672 .attr = rtl8366_port,
1673 .n_attr = ARRAY_SIZE(rtl8366_port),
1674 },
1675 .attr_vlan = {
1676 .attr = rtl8366_vlan,
1677 .n_attr = ARRAY_SIZE(rtl8366_vlan),
1678 },
1679
1680 .get_vlan_ports = rtl8366_get_ports,
1681 .set_vlan_ports = rtl8366_set_ports,
1682 .get_port_pvid = rtl8366_get_port_pvid,
1683 .set_port_pvid = rtl8366_set_port_pvid,
1684 .reset_switch = rtl8366_reset_switch,
1685 };
1686
1687 static int rtl8366_smi_switch_init(struct rtl8366_smi *smi)
1688 {
1689 struct switch_dev *dev = &smi->dev;
1690 int err;
1691
1692 memcpy(dev, &rtldev, sizeof(struct switch_dev));
1693 dev->priv = smi;
1694 dev->devname = dev_name(&smi->pdev->dev);
1695
1696 err = register_switch(dev, NULL);
1697 if (err)
1698 dev_err(&smi->pdev->dev, "switch registration failed\n");
1699
1700 return err;
1701 }
1702
1703 static void rtl8366_smi_switch_cleanup(struct rtl8366_smi *smi)
1704 {
1705 unregister_switch(&smi->dev);
1706 }
1707
1708 static int rtl8366_smi_mii_read(struct mii_bus *bus, int addr, int reg)
1709 {
1710 struct rtl8366_smi *smi = bus->priv;
1711 u32 val = 0;
1712 int err;
1713
1714 err = rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &val);
1715 if (err)
1716 return 0xffff;
1717
1718 return val;
1719 }
1720
1721 static int rtl8366_smi_mii_write(struct mii_bus *bus, int addr, int reg,
1722 u16 val)
1723 {
1724 struct rtl8366_smi *smi = bus->priv;
1725 u32 t;
1726 int err;
1727
1728 err = rtl8366_smi_write_phy_reg(smi, addr, 0, reg, val);
1729 /* flush write */
1730 (void) rtl8366_smi_read_phy_reg(smi, addr, 0, reg, &t);
1731
1732 return err;
1733 }
1734
1735 static int rtl8366_smi_mii_init(struct rtl8366_smi *smi)
1736 {
1737 int ret;
1738 int i;
1739
1740 smi->mii_bus = mdiobus_alloc();
1741 if (smi->mii_bus == NULL) {
1742 ret = -ENOMEM;
1743 goto err;
1744 }
1745
1746 spin_lock_init(&smi->lock);
1747 smi->mii_bus->priv = (void *) smi;
1748 smi->mii_bus->name = "rtl8366-smi";
1749 smi->mii_bus->read = rtl8366_smi_mii_read;
1750 smi->mii_bus->write = rtl8366_smi_mii_write;
1751 snprintf(smi->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1752 dev_name(&smi->pdev->dev));
1753 smi->mii_bus->parent = &smi->pdev->dev;
1754 smi->mii_bus->phy_mask = ~(0x1f);
1755 smi->mii_bus->irq = smi->mii_irq;
1756 for (i = 0; i < PHY_MAX_ADDR; i++)
1757 smi->mii_irq[i] = PHY_POLL;
1758
1759 ret = mdiobus_register(smi->mii_bus);
1760 if (ret)
1761 goto err_free;
1762
1763 return 0;
1764
1765 err_free:
1766 mdiobus_free(smi->mii_bus);
1767 err:
1768 return ret;
1769 }
1770
1771 static void rtl8366_smi_mii_cleanup(struct rtl8366_smi *smi)
1772 {
1773 mdiobus_unregister(smi->mii_bus);
1774 mdiobus_free(smi->mii_bus);
1775 }
1776
1777 static int rtl8366_smi_mii_bus_match(struct mii_bus *bus)
1778 {
1779 return (bus->read == rtl8366_smi_mii_read &&
1780 bus->write == rtl8366_smi_mii_write);
1781 }
1782
1783 static int rtl8366_smi_setup(struct rtl8366_smi *smi)
1784 {
1785 u32 chip_id = 0;
1786 u32 chip_ver = 0;
1787 int ret;
1788
1789 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1790 if (ret) {
1791 dev_err(&smi->pdev->dev, "unable to read chip id\n");
1792 return ret;
1793 }
1794
1795 switch (chip_id) {
1796 case RTL8366S_CHIP_ID_8366:
1797 break;
1798 default:
1799 dev_err(&smi->pdev->dev, "unknown chip id (%04x)\n", chip_id);
1800 return -ENODEV;
1801 }
1802
1803 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1804 &chip_ver);
1805 if (ret) {
1806 dev_err(&smi->pdev->dev, "unable to read chip version\n");
1807 return ret;
1808 }
1809
1810 dev_info(&smi->pdev->dev, "RTL%04x ver. %u chip found\n",
1811 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1812
1813 rtl8366_debugfs_init(smi);
1814
1815 return 0;
1816 }
1817
1818 static int __init rtl8366_smi_probe(struct platform_device *pdev)
1819 {
1820 static int rtl8366_smi_version_printed;
1821 struct rtl8366_smi_platform_data *pdata;
1822 struct rtl8366_smi *smi;
1823 int err;
1824
1825 if (!rtl8366_smi_version_printed++)
1826 printk(KERN_NOTICE RTL8366_SMI_DRIVER_DESC
1827 " version " RTL8366_SMI_DRIVER_VER"\n");
1828
1829 pdata = pdev->dev.platform_data;
1830 if (!pdata) {
1831 dev_err(&pdev->dev, "no platform data specified\n");
1832 err = -EINVAL;
1833 goto err_out;
1834 }
1835
1836 smi = kzalloc(sizeof(struct rtl8366_smi), GFP_KERNEL);
1837 if (!smi) {
1838 dev_err(&pdev->dev, "no memory for private data\n");
1839 err = -ENOMEM;
1840 goto err_out;
1841 }
1842
1843 err = gpio_request(pdata->gpio_sda, dev_name(&pdev->dev));
1844 if (err) {
1845 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1846 pdata->gpio_sda, err);
1847 goto err_free_smi;
1848 }
1849
1850 err = gpio_request(pdata->gpio_sck, dev_name(&pdev->dev));
1851 if (err) {
1852 dev_err(&pdev->dev, "gpio_request failed for %u, err=%d\n",
1853 pdata->gpio_sck, err);
1854 goto err_free_sda;
1855 }
1856
1857 smi->pdev = pdev;
1858 smi->pdata = pdata;
1859 spin_lock_init(&smi->lock);
1860
1861 platform_set_drvdata(pdev, smi);
1862
1863 dev_info(&pdev->dev, "using GPIO pins %u (SDA) and %u (SCK)\n",
1864 pdata->gpio_sda, pdata->gpio_sck);
1865
1866 err = rtl8366_smi_setup(smi);
1867 if (err)
1868 goto err_clear_drvdata;
1869
1870 err = rtl8366_smi_mii_init(smi);
1871 if (err)
1872 goto err_clear_drvdata;
1873
1874 err = rtl8366_smi_switch_init(smi);
1875 if (err)
1876 goto err_mii_cleanup;
1877
1878 return 0;
1879
1880 err_mii_cleanup:
1881 rtl8366_smi_mii_cleanup(smi);
1882 err_clear_drvdata:
1883 platform_set_drvdata(pdev, NULL);
1884 gpio_free(pdata->gpio_sck);
1885 err_free_sda:
1886 gpio_free(pdata->gpio_sda);
1887 err_free_smi:
1888 kfree(smi);
1889 err_out:
1890 return err;
1891 }
1892
1893 int rtl8366_phy_config_init(struct phy_device *phydev)
1894 {
1895 if (!rtl8366_smi_mii_bus_match(phydev->bus))
1896 return -EINVAL;
1897
1898 return 0;
1899 }
1900
1901 int rtl8366_phy_config_aneg(struct phy_device *phydev)
1902 {
1903 return 0;
1904 }
1905
1906 static struct phy_driver rtl8366_smi_phy_driver = {
1907 .phy_id = 0x001cc960,
1908 .name = "Realtek RTL8366",
1909 .phy_id_mask = 0x1ffffff0,
1910 .features = PHY_GBIT_FEATURES,
1911 .config_aneg = rtl8366_phy_config_aneg,
1912 .config_init = rtl8366_phy_config_init,
1913 .read_status = genphy_read_status,
1914 .driver = {
1915 .owner = THIS_MODULE,
1916 },
1917 };
1918
1919 static int __devexit rtl8366_smi_remove(struct platform_device *pdev)
1920 {
1921 struct rtl8366_smi *smi = platform_get_drvdata(pdev);
1922
1923 if (smi) {
1924 struct rtl8366_smi_platform_data *pdata;
1925
1926 pdata = pdev->dev.platform_data;
1927
1928 rtl8366_smi_switch_cleanup(smi);
1929 rtl8366_debugfs_remove(smi);
1930 rtl8366_smi_mii_cleanup(smi);
1931 platform_set_drvdata(pdev, NULL);
1932 gpio_free(pdata->gpio_sck);
1933 gpio_free(pdata->gpio_sda);
1934 kfree(smi);
1935 }
1936
1937 return 0;
1938 }
1939
1940 static struct platform_driver rtl8366_smi_driver = {
1941 .driver = {
1942 .name = RTL8366_SMI_DRIVER_NAME,
1943 .owner = THIS_MODULE,
1944 },
1945 .probe = rtl8366_smi_probe,
1946 .remove = __devexit_p(rtl8366_smi_remove),
1947 };
1948
1949 static int __init rtl8366_smi_init(void)
1950 {
1951 int ret;
1952 ret = platform_driver_register(&rtl8366_smi_driver);
1953 if (ret)
1954 return ret;
1955
1956 ret = phy_driver_register(&rtl8366_smi_phy_driver);
1957 if (ret)
1958 goto err_platform_unregister;
1959
1960 return 0;
1961
1962 err_platform_unregister:
1963 platform_driver_unregister(&rtl8366_smi_driver);
1964 return ret;
1965 }
1966 module_init(rtl8366_smi_init);
1967
1968 static void __exit rtl8366_smi_exit(void)
1969 {
1970 phy_driver_unregister(&rtl8366_smi_phy_driver);
1971 platform_driver_unregister(&rtl8366_smi_driver);
1972 }
1973 module_exit(rtl8366_smi_exit);
1974
1975 MODULE_DESCRIPTION(RTL8366_SMI_DRIVER_DESC);
1976 MODULE_VERSION(RTL8366_SMI_DRIVER_VER);
1977 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1978 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1979 MODULE_LICENSE("GPL v2");
1980 MODULE_ALIAS("platform:" RTL8366_SMI_DRIVER_NAME);
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