2b2299991565ecff8eaa8b0da7cbf5b82bfee2cd
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / spi / rb4xx_spi.c
1 /*
2 * SPI controller driver for the Mikrotik RB4xx boards
3 *
4 * Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This file was based on the patches for Linux 2.6.27.39 published by
7 * MikroTik for their RouterBoard 4xx series devices.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/spinlock.h>
19 #include <linux/workqueue.h>
20 #include <linux/platform_device.h>
21 #include <linux/spi/spi.h>
22
23 #include <asm/mach-ar71xx/ar71xx.h>
24
25 #define DRV_NAME "rb4xx-spi"
26 #define DRV_DESC "Mikrotik RB4xx SPI controller driver"
27 #define DRV_VERSION "0.1.0"
28
29 #define SPI_CTRL_FASTEST 0x40
30 #define SPI_FLASH_HZ 33333334
31 #define SPI_CPLD_HZ 33333334
32
33 #define CPLD_CMD_READ_FAST 0x0b
34
35 #undef RB4XX_SPI_DEBUG
36
37 struct rb4xx_spi {
38 void __iomem *base;
39 struct spi_master *master;
40
41 unsigned spi_ctrl_flash;
42 unsigned spi_ctrl_fread;
43
44 spinlock_t lock;
45 struct list_head queue;
46 int busy:1;
47 int cs_wait;
48 };
49
50 static unsigned spi_clk_low = SPI_IOC_CS1;
51
52 #ifdef RB4XX_SPI_DEBUG
53 static inline void do_spi_delay(void)
54 {
55 ndelay(20000);
56 }
57 #else
58 static inline void do_spi_delay(void) { }
59 #endif
60
61 static inline void do_spi_init(struct spi_device *spi)
62 {
63 unsigned cs = SPI_IOC_CS0 | SPI_IOC_CS1;
64
65 if (!(spi->mode & SPI_CS_HIGH))
66 cs ^= (spi->chip_select == 2) ? SPI_IOC_CS1 : SPI_IOC_CS0;
67
68 spi_clk_low = cs;
69 }
70
71 static inline void do_spi_finish(void __iomem *base)
72 {
73 do_spi_delay();
74 __raw_writel(SPI_IOC_CS0 | SPI_IOC_CS1, base + SPI_REG_IOC);
75 }
76
77 static inline void do_spi_clk(void __iomem *base, int bit)
78 {
79 unsigned bval = spi_clk_low | ((bit & 1) ? SPI_IOC_DO : 0);
80
81 do_spi_delay();
82 __raw_writel(bval, base + SPI_REG_IOC);
83 do_spi_delay();
84 __raw_writel(bval | SPI_IOC_CLK, base + SPI_REG_IOC);
85 }
86
87 static void do_spi_byte(void __iomem *base, unsigned char byte)
88 {
89 do_spi_clk(base, byte >> 7);
90 do_spi_clk(base, byte >> 6);
91 do_spi_clk(base, byte >> 5);
92 do_spi_clk(base, byte >> 4);
93 do_spi_clk(base, byte >> 3);
94 do_spi_clk(base, byte >> 2);
95 do_spi_clk(base, byte >> 1);
96 do_spi_clk(base, byte);
97
98 #ifdef RB4XX_SPI_DEBUG
99 printk("spi_byte sent 0x%02x got 0x%02x\n",
100 (unsigned)byte,
101 (unsigned char)__raw_readl(base + SPI_REG_RDS));
102 #endif
103 }
104
105 static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1,
106 unsigned bit2)
107 {
108 unsigned bval = (spi_clk_low |
109 ((bit1 & 1) ? SPI_IOC_DO : 0) |
110 ((bit2 & 1) ? SPI_IOC_CS2 : 0));
111 do_spi_delay();
112 __raw_writel(bval, base + SPI_REG_IOC);
113 do_spi_delay();
114 __raw_writel(bval | SPI_IOC_CLK, base + SPI_REG_IOC);
115 }
116
117 static void do_spi_byte_fast(void __iomem *base, unsigned char byte)
118 {
119 do_spi_clk_fast(base, byte >> 7, byte >> 6);
120 do_spi_clk_fast(base, byte >> 5, byte >> 4);
121 do_spi_clk_fast(base, byte >> 3, byte >> 2);
122 do_spi_clk_fast(base, byte >> 1, byte >> 0);
123
124 #ifdef RB4XX_SPI_DEBUG
125 printk("spi_byte_fast sent 0x%02x got 0x%02x\n",
126 (unsigned)byte,
127 (unsigned char) __raw_readl(base + SPI_REG_RDS));
128 #endif
129 }
130
131 static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t)
132 {
133 const unsigned char *rxv_ptr = NULL;
134 const unsigned char *tx_ptr = t->tx_buf;
135 unsigned char *rx_ptr = t->rx_buf;
136 unsigned i;
137
138 #ifdef RB4XX_SPI_DEBUG
139 printk("spi_txrx len %u tx %u rx %u\n",
140 t->len,
141 (t->tx_buf ? 1 : 0),
142 (t->rx_buf ? 1 : 0));
143 #endif
144
145 if (t->verify) {
146 rxv_ptr = tx_ptr;
147 tx_ptr = NULL;
148 }
149
150 for (i = 0; i < t->len; ++i) {
151 unsigned char sdata = tx_ptr ? tx_ptr[i] : 0;
152
153 if (t->fast_write)
154 do_spi_byte_fast(base, sdata);
155 else
156 do_spi_byte(base, sdata);
157
158 if (rx_ptr) {
159 rx_ptr[i] = __raw_readl(base + SPI_REG_RDS) & 0xff;
160 } else if (rxv_ptr) {
161 unsigned char c = __raw_readl(base + SPI_REG_RDS);
162 if (rxv_ptr[i] != c)
163 return i;
164 }
165 }
166
167 return i;
168 }
169
170 static int rb4xx_spi_read_fast(struct rb4xx_spi *rbspi,
171 struct spi_message *m)
172 {
173 struct spi_transfer *t;
174 const unsigned char *tx_ptr;
175 unsigned addr;
176 void __iomem *base = rbspi->base;
177
178 /* check for exactly two transfers */
179 if (list_empty(&m->transfers) ||
180 list_is_last(m->transfers.next, &m->transfers) ||
181 !list_is_last(m->transfers.next->next, &m->transfers)) {
182 return -1;
183 }
184
185 /* first transfer contains command and address */
186 t = list_entry(m->transfers.next,
187 struct spi_transfer, transfer_list);
188
189 if (t->len != 5 || t->tx_buf == NULL)
190 return -1;
191
192 tx_ptr = t->tx_buf;
193 if (tx_ptr[0] != CPLD_CMD_READ_FAST)
194 return -1;
195
196 addr = tx_ptr[1];
197 addr = tx_ptr[2] | (addr << 8);
198 addr = tx_ptr[3] | (addr << 8);
199 addr += (unsigned) base;
200
201 m->actual_length += t->len;
202
203 /* second transfer contains data itself */
204 t = list_entry(m->transfers.next->next,
205 struct spi_transfer, transfer_list);
206
207 if (t->tx_buf && !t->verify)
208 return -1;
209
210 __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS);
211 __raw_writel(rbspi->spi_ctrl_fread, base + SPI_REG_CTRL);
212 __raw_writel(0, base + SPI_REG_FS);
213
214 if (t->rx_buf) {
215 memcpy(t->rx_buf, (const void *)addr, t->len);
216 } else if (t->tx_buf) {
217 unsigned char buf[t->len];
218 memcpy(buf, (const void *)addr, t->len);
219 if (memcmp(t->tx_buf, buf, t->len) != 0)
220 m->status = -EMSGSIZE;
221 }
222 m->actual_length += t->len;
223
224 if (rbspi->spi_ctrl_flash != rbspi->spi_ctrl_fread) {
225 __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS);
226 __raw_writel(rbspi->spi_ctrl_flash, base + SPI_REG_CTRL);
227 __raw_writel(0, base + SPI_REG_FS);
228 }
229
230 return 0;
231 }
232
233 static int rb4xx_spi_msg(struct rb4xx_spi *rbspi, struct spi_message *m)
234 {
235 struct spi_transfer *t = NULL;
236 void __iomem *base = rbspi->base;
237
238 m->status = 0;
239 if (list_empty(&m->transfers))
240 return -1;
241
242 if (m->fast_read)
243 if (rb4xx_spi_read_fast(rbspi, m) == 0)
244 return -1;
245
246 __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS);
247 __raw_writel(SPI_CTRL_FASTEST, base + SPI_REG_CTRL);
248 do_spi_init(m->spi);
249
250 list_for_each_entry(t, &m->transfers, transfer_list) {
251 int len;
252
253 len = rb4xx_spi_txrx(base, t);
254 if (len != t->len) {
255 m->status = -EMSGSIZE;
256 break;
257 }
258 m->actual_length += len;
259
260 if (t->cs_change) {
261 if (list_is_last(&t->transfer_list, &m->transfers)) {
262 /* wait for continuation */
263 return m->spi->chip_select;
264 }
265 do_spi_finish(base);
266 ndelay(100);
267 }
268 }
269
270 do_spi_finish(base);
271 __raw_writel(rbspi->spi_ctrl_flash, base + SPI_REG_CTRL);
272 __raw_writel(0, base + SPI_REG_FS);
273 return -1;
274 }
275
276 static void rb4xx_spi_process_queue_locked(struct rb4xx_spi *rbspi,
277 unsigned long *flags)
278 {
279 int cs = rbspi->cs_wait;
280
281 rbspi->busy = 1;
282 while (!list_empty(&rbspi->queue)) {
283 struct spi_message *m;
284
285 list_for_each_entry(m, &rbspi->queue, queue)
286 if (cs < 0 || cs == m->spi->chip_select)
287 break;
288
289 if (&m->queue == &rbspi->queue)
290 break;
291
292 list_del_init(&m->queue);
293 spin_unlock_irqrestore(&rbspi->lock, *flags);
294
295 cs = rb4xx_spi_msg(rbspi, m);
296 m->complete(m->context);
297
298 spin_lock_irqsave(&rbspi->lock, *flags);
299 }
300
301 rbspi->cs_wait = cs;
302 rbspi->busy = 0;
303
304 if (cs >= 0) {
305 /* TODO: add timer to unlock cs after 1s inactivity */
306 }
307 }
308
309 static int rb4xx_spi_transfer(struct spi_device *spi,
310 struct spi_message *m)
311 {
312 struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
313 unsigned long flags;
314
315 m->actual_length = 0;
316 m->status = -EINPROGRESS;
317
318 spin_lock_irqsave(&rbspi->lock, flags);
319 list_add_tail(&m->queue, &rbspi->queue);
320 if (rbspi->busy ||
321 (rbspi->cs_wait >= 0 && rbspi->cs_wait != m->spi->chip_select)) {
322 /* job will be done later */
323 spin_unlock_irqrestore(&rbspi->lock, flags);
324 return 0;
325 }
326
327 /* process job in current context */
328 rb4xx_spi_process_queue_locked(rbspi, &flags);
329 spin_unlock_irqrestore(&rbspi->lock, flags);
330
331 return 0;
332 }
333
334 static int rb4xx_spi_setup(struct spi_device *spi)
335 {
336 struct rb4xx_spi *rbspi = spi_master_get_devdata(spi->master);
337 unsigned long flags;
338
339 if (spi->mode & ~(SPI_CS_HIGH)) {
340 dev_err(&spi->dev, "mode %x not supported\n",
341 (unsigned) spi->mode);
342 return -EINVAL;
343 }
344
345 if (spi->bits_per_word != 8 && spi->bits_per_word != 0) {
346 dev_err(&spi->dev, "bits_per_word %u not supported\n",
347 (unsigned) spi->bits_per_word);
348 return -EINVAL;
349 }
350
351 spin_lock_irqsave(&rbspi->lock, flags);
352 if (rbspi->cs_wait == spi->chip_select && !rbspi->busy) {
353 rbspi->cs_wait = -1;
354 rb4xx_spi_process_queue_locked(rbspi, &flags);
355 }
356 spin_unlock_irqrestore(&rbspi->lock, flags);
357
358 return 0;
359 }
360
361 static unsigned get_spi_ctrl(unsigned hz_max, const char *name)
362 {
363 unsigned div;
364
365 div = (ar71xx_ahb_freq - 1) / (2 * hz_max);
366
367 /*
368 * CPU has a bug at (div == 0) - first bit read is random
369 */
370 if (div == 0)
371 ++div;
372
373 if (name) {
374 unsigned ahb_khz = (ar71xx_ahb_freq + 500) / 1000;
375 unsigned div_real = 2 * (div + 1);
376 pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n",
377 name,
378 ahb_khz / div_real,
379 ahb_khz, div_real);
380 }
381
382 return SPI_CTRL_FASTEST + div;
383 }
384
385 static int rb4xx_spi_probe(struct platform_device *pdev)
386 {
387 struct spi_master *master;
388 struct rb4xx_spi *rbspi;
389 struct resource *r;
390 int err = 0;
391
392 master = spi_alloc_master(&pdev->dev, sizeof(*rbspi));
393 if (master == NULL) {
394 dev_err(&pdev->dev, "no memory for spi_master\n");
395 err = -ENOMEM;
396 goto err_out;
397 }
398
399 master->bus_num = 0;
400 master->num_chipselect = 3;
401 master->setup = rb4xx_spi_setup;
402 master->transfer = rb4xx_spi_transfer;
403
404 rbspi = spi_master_get_devdata(master);
405 platform_set_drvdata(pdev, rbspi);
406
407 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
408 if (r == NULL) {
409 err = -ENOENT;
410 goto err_put_master;
411 }
412
413 rbspi->base = ioremap(r->start, r->end - r->start + 1);
414 if (!rbspi->base) {
415 err = -ENXIO;
416 goto err_put_master;
417 }
418
419 rbspi->master = master;
420 rbspi->spi_ctrl_flash = get_spi_ctrl(SPI_FLASH_HZ, "FLASH");
421 rbspi->spi_ctrl_fread = get_spi_ctrl(SPI_CPLD_HZ, "CPLD");
422 rbspi->cs_wait = -1;
423
424 spin_lock_init(&rbspi->lock);
425 INIT_LIST_HEAD(&rbspi->queue);
426
427 err = spi_register_master(master);
428 if (err) {
429 dev_err(&pdev->dev, "failed to register SPI master\n");
430 goto err_iounmap;
431 }
432
433 return 0;
434
435 err_iounmap:
436 iounmap(rbspi->base);
437 err_put_master:
438 platform_set_drvdata(pdev, NULL);
439 spi_master_put(master);
440 err_out:
441 return err;
442 }
443
444 static int rb4xx_spi_remove(struct platform_device *pdev)
445 {
446 struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
447
448 iounmap(rbspi->base);
449 platform_set_drvdata(pdev, NULL);
450 spi_master_put(rbspi->master);
451
452 return 0;
453 }
454
455 static struct platform_driver rb4xx_spi_drv = {
456 .probe = rb4xx_spi_probe,
457 .remove = rb4xx_spi_remove,
458 .driver = {
459 .name = DRV_NAME,
460 .owner = THIS_MODULE,
461 },
462 };
463
464 static int __init rb4xx_spi_init(void)
465 {
466 return platform_driver_register(&rb4xx_spi_drv);
467 }
468 subsys_initcall(rb4xx_spi_init);
469
470 static void __exit rb4xx_spi_exit(void)
471 {
472 platform_driver_unregister(&rb4xx_spi_drv);
473 }
474
475 module_exit(rb4xx_spi_exit);
476
477 MODULE_DESCRIPTION(DRV_DESC);
478 MODULE_VERSION(DRV_VERSION);
479 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
480 MODULE_LICENSE("GPL v2");