[ar71xx] ag71xx: introduce SoC specific fuctions for DDR flush and PLL setup
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / include / asm-mips / mach-ar71xx / ar71xx.h
1 /*
2 * Atheros AR71xx SoC specific definitions
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __ASM_MACH_AR71XX_H
15 #define __ASM_MACH_AR71XX_H
16
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/io.h>
20 #include <linux/bitops.h>
21
22 #ifndef __ASSEMBLER__
23
24 #define AR71XX_PCI_MEM_BASE 0x10000000
25 #define AR71XX_PCI_MEM_SIZE 0x08000000
26 #define AR71XX_APB_BASE 0x18000000
27 #define AR71XX_GE0_BASE 0x19000000
28 #define AR71XX_GE0_SIZE 0x01000000
29 #define AR71XX_GE1_BASE 0x1a000000
30 #define AR71XX_GE1_SIZE 0x01000000
31 #define AR71XX_EHCI_BASE 0x1b000000
32 #define AR71XX_EHCI_SIZE 0x01000000
33 #define AR71XX_OHCI_BASE 0x1c000000
34 #define AR71XX_OHCI_SIZE 0x01000000
35 #define AR71XX_SPI_BASE 0x1f000000
36 #define AR71XX_SPI_SIZE 0x01000000
37
38 #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
39 #define AR71XX_DDR_CTRL_SIZE 0x10000
40 #define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000)
41 #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
42 #define AR71XX_UART_SIZE 0x10000
43 #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
44 #define AR71XX_USB_CTRL_SIZE 0x10000
45 #define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000)
46 #define AR71XX_GPIO_SIZE 0x10000
47 #define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000)
48 #define AR71XX_PLL_SIZE 0x10000
49 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
50 #define AR71XX_RESET_SIZE 0x10000
51 #define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
52 #define AR71XX_MII_SIZE 0x10000
53 #define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000)
54 #define AR71XX_SLIC_SIZE 0x10000
55 #define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000)
56 #define AR71XX_DMA_SIZE 0x10000
57 #define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000)
58 #define AR71XX_STEREO_SIZE 0x10000
59
60 #define AR71XX_CPU_IRQ_BASE 0
61 #define AR71XX_MISC_IRQ_BASE 8
62 #define AR71XX_MISC_IRQ_COUNT 8
63 #define AR71XX_GPIO_IRQ_BASE 16
64 #define AR71XX_GPIO_IRQ_COUNT 16
65 #define AR71XX_PCI_IRQ_BASE 32
66 #define AR71XX_PCI_IRQ_COUNT 4
67
68 #define AR71XX_CPU_IRQ_PCI (AR71XX_CPU_IRQ_BASE + 2)
69 #define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3)
70 #define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4)
71 #define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5)
72 #define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6)
73 #define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7)
74
75 #define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0)
76 #define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1)
77 #define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2)
78 #define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3)
79 #define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4)
80 #define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5)
81 #define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6)
82 #define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7)
83
84 #define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x))
85
86 #define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0)
87 #define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1)
88 #define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2)
89 #define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 3)
90
91 extern u32 ar71xx_ahb_freq;
92 extern u32 ar71xx_cpu_freq;
93 extern u32 ar71xx_ddr_freq;
94
95 enum ar71xx_soc_type {
96 AR71XX_SOC_UNKNOWN,
97 AR71XX_SOC_AR7130,
98 AR71XX_SOC_AR7141,
99 AR71XX_SOC_AR7161,
100 AR71XX_SOC_AR9130,
101 AR71XX_SOC_AR9132
102 };
103
104 extern enum ar71xx_soc_type ar71xx_soc;
105
106 /*
107 * PLL block
108 */
109 #define AR71XX_PLL_REG_CPU_CONFIG 0x00
110 #define AR71XX_PLL_REG_SEC_CONFIG 0x04
111 #define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10
112 #define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14
113
114 #define AR71XX_PLL_DIV_SHIFT 3
115 #define AR71XX_PLL_DIV_MASK 0x1f
116 #define AR71XX_CPU_DIV_SHIFT 16
117 #define AR71XX_CPU_DIV_MASK 0x3
118 #define AR71XX_DDR_DIV_SHIFT 18
119 #define AR71XX_DDR_DIV_MASK 0x3
120 #define AR71XX_AHB_DIV_SHIFT 20
121 #define AR71XX_AHB_DIV_MASK 0x7
122
123 #define AR71XX_ETH0_PLL_SHIFT 17
124 #define AR71XX_ETH1_PLL_SHIFT 19
125
126 #define AR91XX_PLL_REG_CPU_CONFIG 0x00
127 #define AR91XX_PLL_REG_ETH_CONFIG 0x04
128 #define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14
129 #define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18
130
131 #define AR91XX_PLL_DIV_SHIFT 0
132 #define AR91XX_PLL_DIV_MASK 0x3ff
133 #define AR91XX_DDR_DIV_SHIFT 22
134 #define AR91XX_DDR_DIV_MASK 0x3
135 #define AR91XX_AHB_DIV_SHIFT 19
136 #define AR91XX_AHB_DIV_MASK 0x1
137
138 #define AR91XX_ETH0_PLL_SHIFT 20
139 #define AR91XX_ETH1_PLL_SHIFT 22
140
141 extern void __iomem *ar71xx_pll_base;
142
143 static inline void ar71xx_pll_wr(unsigned reg, u32 val)
144 {
145 __raw_writel(val, ar71xx_pll_base + reg);
146 }
147
148 static inline u32 ar71xx_pll_rr(unsigned reg)
149 {
150 return __raw_readl(ar71xx_pll_base + reg);
151 }
152
153 /*
154 * USB_CONFIG block
155 */
156 #define USB_CTRL_REG_FLADJ 0x00
157 #define USB_CTRL_REG_CONFIG 0x04
158
159 extern void __iomem *ar71xx_usb_ctrl_base;
160
161 static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val)
162 {
163 __raw_writel(val, ar71xx_usb_ctrl_base + reg);
164 }
165
166 static inline u32 ar71xx_usb_ctrl_rr(unsigned reg)
167 {
168 return __raw_readl(ar71xx_usb_ctrl_base + reg);
169 }
170
171 extern void ar71xx_add_device_usb(void) __init;
172
173 /*
174 * GPIO block
175 */
176 #define GPIO_REG_OE 0x00
177 #define GPIO_REG_IN 0x04
178 #define GPIO_REG_OUT 0x08
179 #define GPIO_REG_SET 0x0c
180 #define GPIO_REG_CLEAR 0x10
181 #define GPIO_REG_INT_MODE 0x14
182 #define GPIO_REG_INT_TYPE 0x18
183 #define GPIO_REG_INT_POLARITY 0x1c
184 #define GPIO_REG_INT_PENDING 0x20
185 #define GPIO_REG_INT_ENABLE 0x24
186 #define GPIO_REG_FUNC 0x28
187
188 #define GPIO_FUNC_STEREO_EN BIT(17)
189 #define GPIO_FUNC_SLIC_EN BIT(16)
190 #define GPIO_FUNC_SPI_CS1_EN BIT(15)
191 #define GPIO_FUNC_SPI_CS0_EN BIT(14)
192 #define GPIO_FUNC_SPI_EN BIT(13)
193 #define GPIO_FUNC_UART_EN BIT(8)
194 #define GPIO_FUNC_USB_OC_EN BIT(4)
195 #define GPIO_FUNC_USB_CLK_EN BIT(0)
196
197 #define AR71XX_GPIO_COUNT 16
198
199 extern void __iomem *ar71xx_gpio_base;
200
201 static inline void ar71xx_gpio_wr(unsigned reg, u32 value)
202 {
203 __raw_writel(value, ar71xx_gpio_base + reg);
204 }
205
206 static inline u32 ar71xx_gpio_rr(unsigned reg)
207 {
208 return __raw_readl(ar71xx_gpio_base + reg);
209 }
210
211 extern void ar71xx_gpio_init(void) __init;
212 extern void ar71xx_gpio_function_enable(u32 mask);
213 extern void ar71xx_gpio_function_disable(u32 mask);
214
215 /*
216 * DDR_CTRL block
217 */
218 #define AR71XX_DDR_REG_PCI_WIN0 0x7c
219 #define AR71XX_DDR_REG_PCI_WIN1 0x80
220 #define AR71XX_DDR_REG_PCI_WIN2 0x84
221 #define AR71XX_DDR_REG_PCI_WIN3 0x88
222 #define AR71XX_DDR_REG_PCI_WIN4 0x8c
223 #define AR71XX_DDR_REG_PCI_WIN5 0x90
224 #define AR71XX_DDR_REG_PCI_WIN6 0x94
225 #define AR71XX_DDR_REG_PCI_WIN7 0x98
226 #define AR71XX_DDR_REG_FLUSH_GE0 0x9c
227 #define AR71XX_DDR_REG_FLUSH_GE1 0xa0
228 #define AR71XX_DDR_REG_FLUSH_USB 0xa4
229 #define AR71XX_DDR_REG_FLUSH_PCI 0xa8
230
231 #define AR91XX_DDR_REG_FLUSH_GE0 0x7c
232 #define AR91XX_DDR_REG_FLUSH_GE1 0x80
233 #define AR91XX_DDR_REG_FLUSH_USB 0x84
234 #define AR91XX_DDR_REG_FLUSH_WMAC 0x88
235
236 #define PCI_WIN0_OFFS 0x10000000
237 #define PCI_WIN1_OFFS 0x11000000
238 #define PCI_WIN2_OFFS 0x12000000
239 #define PCI_WIN3_OFFS 0x13000000
240 #define PCI_WIN4_OFFS 0x14000000
241 #define PCI_WIN5_OFFS 0x15000000
242 #define PCI_WIN6_OFFS 0x16000000
243 #define PCI_WIN7_OFFS 0x07000000
244
245 extern void __iomem *ar71xx_ddr_base;
246
247 static inline void ar71xx_ddr_wr(unsigned reg, u32 val)
248 {
249 __raw_writel(val, ar71xx_ddr_base + reg);
250 }
251
252 static inline u32 ar71xx_ddr_rr(unsigned reg)
253 {
254 return __raw_readl(ar71xx_ddr_base + reg);
255 }
256
257 extern void ar71xx_ddr_flush(u32 reg);
258
259 /*
260 * PCI block
261 */
262 #define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000)
263 #define AR71XX_PCI_CFG_SIZE 0x100
264
265 #define PCI_REG_CRP_AD_CBE 0x00
266 #define PCI_REG_CRP_WRDATA 0x04
267 #define PCI_REG_CRP_RDDATA 0x08
268 #define PCI_REG_CFG_AD 0x0c
269 #define PCI_REG_CFG_CBE 0x10
270 #define PCI_REG_CFG_WRDATA 0x14
271 #define PCI_REG_CFG_RDDATA 0x18
272 #define PCI_REG_PCI_ERR 0x1c
273 #define PCI_REG_PCI_ERR_ADDR 0x20
274 #define PCI_REG_AHB_ERR 0x24
275 #define PCI_REG_AHB_ERR_ADDR 0x28
276
277 #define PCI_CRP_CMD_WRITE 0x00010000
278 #define PCI_CRP_CMD_READ 0x00000000
279 #define PCI_CFG_CMD_READ 0x0000000a
280 #define PCI_CFG_CMD_WRITE 0x0000000b
281
282 #define PCI_IDSEL_ADL_START 17
283
284 /*
285 * RESET block
286 */
287 #define RESET_REG_TIMER 0x00
288 #define RESET_REG_TIMER_RELOAD 0x04
289 #define RESET_REG_WDOG_CTRL 0x08
290 #define RESET_REG_WDOG 0x0c
291 #define RESET_REG_MISC_INT_STATUS 0x10
292 #define RESET_REG_MISC_INT_ENABLE 0x14
293 #define RESET_REG_PCI_INT_STATUS 0x18
294 #define RESET_REG_PCI_INT_ENABLE 0x1c
295 #define RESET_REG_GLOBAL_INT_STATUS 0x20
296 #define RESET_REG_RESET_MODULE 0x24
297 #define RESET_REG_PERFC_CTRL 0x2c
298 #define RESET_REG_PERFC0 0x30
299 #define RESET_REG_PERFC1 0x34
300 #define RESET_REG_REV_ID 0x90
301
302 #define WDOG_CTRL_LAST_RESET BIT(31)
303 #define WDOG_CTRL_ACTION_MASK 3
304 #define WDOG_CTRL_ACTION_NONE 0 /* no action */
305 #define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */
306 #define WDOG_CTRL_ACTION_NMI 2 /* NMI */
307 #define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */
308
309 #define MISC_INT_DMA BIT(7)
310 #define MISC_INT_OHCI BIT(6)
311 #define MISC_INT_PERFC BIT(5)
312 #define MISC_INT_WDOG BIT(4)
313 #define MISC_INT_UART BIT(3)
314 #define MISC_INT_GPIO BIT(2)
315 #define MISC_INT_ERROR BIT(1)
316 #define MISC_INT_TIMER BIT(0)
317
318 #define PCI_INT_CORE BIT(4)
319 #define PCI_INT_DEV2 BIT(2)
320 #define PCI_INT_DEV1 BIT(1)
321 #define PCI_INT_DEV0 BIT(0)
322
323 #define RESET_MODULE_EXTERNAL BIT(28)
324 #define RESET_MODULE_FULL_CHIP BIT(24)
325 #define RESET_MODULE_CPU_NMI BIT(21)
326 #define RESET_MODULE_CPU_COLD BIT(20)
327 #define RESET_MODULE_DMA BIT(19)
328 #define RESET_MODULE_SLIC BIT(18)
329 #define RESET_MODULE_STEREO BIT(17)
330 #define RESET_MODULE_DDR BIT(16)
331 #define RESET_MODULE_GE1_MAC BIT(13)
332 #define RESET_MODULE_GE1_PHY BIT(12)
333 #define RESET_MODULE_USBSUS_OVERRIDE BIT(10)
334 #define RESET_MODULE_GE0_MAC BIT(9)
335 #define RESET_MODULE_GE0_PHY BIT(8)
336 #define RESET_MODULE_USB_OHCI_DLL BIT(6)
337 #define RESET_MODULE_USB_HOST BIT(5)
338 #define RESET_MODULE_USB_PHY BIT(4)
339 #define RESET_MODULE_PCI_BUS BIT(1)
340 #define RESET_MODULE_PCI_CORE BIT(0)
341
342 #define REV_ID_MASK 0xff
343 #define REV_ID_CHIP_MASK 0xf3
344 #define REV_ID_CHIP_AR7130 0xa0
345 #define REV_ID_CHIP_AR7141 0xa1
346 #define REV_ID_CHIP_AR7161 0xa2
347 #define REV_ID_CHIP_AR9130 0xb0
348 #define REV_ID_CHIP_AR9132 0xb1
349
350 #define REV_ID_REVISION_MASK 0x3
351 #define REV_ID_REVISION_SHIFT 2
352
353 extern void __iomem *ar71xx_reset_base;
354
355 static inline void ar71xx_reset_wr(unsigned reg, u32 val)
356 {
357 __raw_writel(val, ar71xx_reset_base + reg);
358 }
359
360 static inline u32 ar71xx_reset_rr(unsigned reg)
361 {
362 return __raw_readl(ar71xx_reset_base + reg);
363 }
364
365 extern void ar71xx_device_stop(u32 mask);
366 extern void ar71xx_device_start(u32 mask);
367
368 /*
369 * SPI block
370 */
371 #define SPI_REG_FS 0x00 /* Function Select */
372 #define SPI_REG_CTRL 0x04 /* SPI Control */
373 #define SPI_REG_IOC 0x08 /* SPI I/O Control */
374 #define SPI_REG_RDS 0x0c /* Read Data Shift */
375
376 #define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */
377
378 #define SPI_CTRL_RD BIT(6) /* Remap Disable */
379 #define SPI_CTRL_DIV_MASK 0x3f
380
381 #define SPI_IOC_DO BIT(0) /* Data Out pin */
382 #define SPI_IOC_CLK BIT(8) /* CLK pin */
383 #define SPI_IOC_CS(n) BIT(16 + (n))
384 #define SPI_IOC_CS0 SPI_IOC_CS(0)
385 #define SPI_IOC_CS1 SPI_IOC_CS(1)
386 #define SPI_IOC_CS2 SPI_IOC_CS(2)
387 #define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2)
388
389 /*
390 * MII_CTRL block
391 */
392 #define MII_REG_MII0_CTRL 0x00
393 #define MII_REG_MII1_CTRL 0x04
394
395 #define MII0_CTRL_IF_GMII 0
396 #define MII0_CTRL_IF_MII 1
397 #define MII0_CTRL_IF_RGMII 2
398 #define MII0_CTRL_IF_RMII 3
399
400 #define MII1_CTRL_IF_RGMII 0
401 #define MII1_CTRL_IF_RMII 1
402
403 #endif /* __ASSEMBLER__ */
404
405 #endif /* __ASM_MACH_AR71XX_H */