[ar71xx] add initial support for 2.6.29
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / patches-2.6.29 / 902-mips_clocksource_init_war.patch
1 --- a/arch/mips/kernel/cevt-r4k.c
2 +++ b/arch/mips/kernel/cevt-r4k.c
3 @@ -15,6 +15,22 @@
4 #include <asm/cevt-r4k.h>
5
6 /*
7 + * Compare interrupt can be routed and latched outside the core,
8 + * so a single execution hazard barrier may not be enough to give
9 + * it time to clear as seen in the Cause register. 4 time the
10 + * pipeline depth seems reasonably conservative, and empirically
11 + * works better in configurations with high CPU/bus clock ratios.
12 + */
13 +
14 +#define compare_change_hazard() \
15 + do { \
16 + irq_disable_hazard(); \
17 + irq_disable_hazard(); \
18 + irq_disable_hazard(); \
19 + irq_disable_hazard(); \
20 + } while (0)
21 +
22 +/*
23 * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
24 * of these routines with SMTC-specific variants.
25 */
26 @@ -30,6 +46,7 @@ static int mips_next_event(unsigned long
27 cnt = read_c0_count();
28 cnt += delta;
29 write_c0_compare(cnt);
30 + compare_change_hazard();
31 res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
32 return res;
33 }
34 @@ -99,22 +116,6 @@ static int c0_compare_int_pending(void)
35 return (read_c0_cause() >> cp0_compare_irq) & 0x100;
36 }
37
38 -/*
39 - * Compare interrupt can be routed and latched outside the core,
40 - * so a single execution hazard barrier may not be enough to give
41 - * it time to clear as seen in the Cause register. 4 time the
42 - * pipeline depth seems reasonably conservative, and empirically
43 - * works better in configurations with high CPU/bus clock ratios.
44 - */
45 -
46 -#define compare_change_hazard() \
47 - do { \
48 - irq_disable_hazard(); \
49 - irq_disable_hazard(); \
50 - irq_disable_hazard(); \
51 - irq_disable_hazard(); \
52 - } while (0)
53 -
54 int c0_compare_int_usable(void)
55 {
56 unsigned int delta;