target/linux/ar71xx/patches-3.10/609-MIPS-ath79-ap136-fixes.patch

   1 --- a/arch/mips/ath79/mach-ap136.c
   2 +++ b/arch/mips/ath79/mach-ap136.c
   3 @@ -18,23 +18,29 @@
   4   *
   5   */
   6
   7 -#include <linux/pci.h>
   8 -#include <linux/ath9k_platform.h>
   9 +#include <linux/platform_device.h>
  10 +#include <linux/ar8216_platform.h>
  11
  12 -#include "machtypes.h"
  13 +#include <asm/mach-ath79/ar71xx_regs.h>
  14 +
  15 +#include "common.h"
  16 +#include "pci.h"
  17 +#include "dev-ap9x-pci.h"
  18  #include "dev-gpio-buttons.h"
  19 +#include "dev-eth.h"
  20  #include "dev-leds-gpio.h"
  21 -#include "dev-spi.h"
  22 +#include "dev-m25p80.h"
  23 +#include "dev-nfc.h"
  24  #include "dev-usb.h"
  25  #include "dev-wmac.h"
  26 -#include "pci.h"
  27 +#include "machtypes.h"
  28
  29 -#define AP136_GPIO_LED_STATUS_RED      14
  30 -#define AP136_GPIO_LED_STATUS_GREEN    19
  31  #define AP136_GPIO_LED_USB             4
  32 -#define AP136_GPIO_LED_WLAN_2G         13
  33  #define AP136_GPIO_LED_WLAN_5G         12
  34 +#define AP136_GPIO_LED_WLAN_2G         13
  35 +#define AP136_GPIO_LED_STATUS_RED      14
  36  #define AP136_GPIO_LED_WPS_RED         15
  37 +#define AP136_GPIO_LED_STATUS_GREEN    19
  38  #define AP136_GPIO_LED_WPS_GREEN       20
  39
  40  #define AP136_GPIO_BTN_WPS             16
  41 @@ -43,37 +49,39 @@
  42  #define AP136_KEYS_POLL_INTERVAL       20      /* msecs */
  43  #define AP136_KEYS_DEBOUNCE_INTERVAL   (3 * AP136_KEYS_POLL_INTERVAL)
  44
  45 -#define AP136_WMAC_CALDATA_OFFSET 0x1000
  46 -#define AP136_PCIE_CALDATA_OFFSET 0x5000
  47 +#define AP136_MAC0_OFFSET              0
  48 +#define AP136_MAC1_OFFSET              6
  49 +#define AP136_WMAC_CALDATA_OFFSET      0x1000
  50 +#define AP136_PCIE_CALDATA_OFFSET      0x5000
  51
  52  static struct gpio_led ap136_leds_gpio[] __initdata = {
  53         {
  54 -               .name           = "qca:green:status",
  55 +               .name           = "ap136:green:status",
  56                 .gpio           = AP136_GPIO_LED_STATUS_GREEN,
  57                 .active_low     = 1,
  58         },
  59         {
  60 -               .name           = "qca:red:status",
  61 +               .name           = "ap136:red:status",
  62                 .gpio           = AP136_GPIO_LED_STATUS_RED,
  63                 .active_low     = 1,
  64         },
  65         {
  66 -               .name           = "qca:green:wps",
  67 +               .name           = "ap136:green:wps",
  68                 .gpio           = AP136_GPIO_LED_WPS_GREEN,
  69                 .active_low     = 1,
  70         },
  71         {
  72 -               .name           = "qca:red:wps",
  73 +               .name           = "ap136:red:wps",
  74                 .gpio           = AP136_GPIO_LED_WPS_RED,
  75                 .active_low     = 1,
  76         },
  77         {
  78 -               .name           = "qca:red:wlan-2g",
  79 +               .name           = "ap136:red:wlan-2g",
  80                 .gpio           = AP136_GPIO_LED_WLAN_2G,
  81                 .active_low     = 1,
  82         },
  83         {
  84 -               .name           = "qca:red:usb",
  85 +               .name           = "ap136:red:usb",
  86                 .gpio           = AP136_GPIO_LED_USB,
  87                 .active_low     = 1,
  88         }
  89 @@ -98,65 +106,169 @@ static struct gpio_keys_button ap136_gpi
  90         },
  91  };
  92
  93 -static struct ath79_spi_controller_data ap136_spi0_data = {
  94 -       .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
  95 -       .cs_line = 0,
  96 +static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg;
  97 +static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg;
  98 +
  99 +static struct ar8327_platform_data ap136_ar8327_data = {
 100 +       .pad0_cfg = &ap136_ar8327_pad0_cfg,
 101 +       .pad6_cfg = &ap136_ar8327_pad6_cfg,
 102 +       .port0_cfg = {
 103 +               .force_link = 1,
 104 +               .speed = AR8327_PORT_SPEED_1000,
 105 +               .duplex = 1,
 106 +               .txpause = 1,
 107 +               .rxpause = 1,
 108 +       },
 109 +       .port6_cfg = {
 110 +               .force_link = 1,
 111 +               .speed = AR8327_PORT_SPEED_1000,
 112 +               .duplex = 1,
 113 +               .txpause = 1,
 114 +               .rxpause = 1,
 115 +       },
 116  };
 117
 118 -static struct spi_board_info ap136_spi_info[] = {
 119 +static struct mdio_board_info ap136_mdio0_info[] = {
 120         {
 121 -               .bus_num        = 0,
 122 -               .chip_select    = 0,
 123 -               .max_speed_hz   = 25000000,
 124 -               .modalias       = "mx25l6405d",
 125 -               .controller_data = &ap136_spi0_data,
 126 -       }
 127 +               .bus_id = "ag71xx-mdio.0",
 128 +               .phy_addr = 0,
 129 +               .platform_data = &ap136_ar8327_data,
 130 +       },
 131  };
 132
 133 -static struct ath79_spi_platform_data ap136_spi_data = {
 134 -       .bus_num        = 0,
 135 -       .num_chipselect = 1,
 136 -};
 137 +static void __init ap136_gmac_setup(void)
 138 +{
 139 +       void __iomem *base;
 140 +       u32 t;
 141
 142 -#ifdef CONFIG_PCI
 143 -static struct ath9k_platform_data ap136_ath9k_data;
 144 +       base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
 145
 146 -static int ap136_pci_plat_dev_init(struct pci_dev *dev)
 147 -{
 148 -       if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
 149 -               dev->dev.platform_data = &ap136_ath9k_data;
 150 +       t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
 151
 152 -       return 0;
 153 -}
 154 +       t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
 155 +       t |= QCA955X_ETH_CFG_RGMII_EN;
 156
 157 -static void __init ap136_pci_init(u8 *eeprom)
 158 -{
 159 -       memcpy(ap136_ath9k_data.eeprom_data, eeprom,
 160 -              sizeof(ap136_ath9k_data.eeprom_data));
 161 +       __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
 162
 163 -       ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
 164 -       ath79_register_pci();
 165 +       iounmap(base);
 166  }
 167 -#else
 168 -static inline void ap136_pci_init(void) {}
 169 -#endif /* CONFIG_PCI */
 170
 171 -static void __init ap136_setup(void)
 172 +static void __init ap136_common_setup(void)
 173  {
 174         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 175
 176 +       ath79_register_m25p80(NULL);
 177 +
 178         ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
 179                                  ap136_leds_gpio);
 180         ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
 181                                         ARRAY_SIZE(ap136_gpio_keys),
 182                                         ap136_gpio_keys);
 183 -       ath79_register_spi(&ap136_spi_data, ap136_spi_info,
 184 -                          ARRAY_SIZE(ap136_spi_info));
 185 +
 186         ath79_register_usb();
 187 -       ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
 188 -       ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
 189 +       ath79_register_nfc();
 190 +
 191 +       ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
 192 +
 193 +       ap136_gmac_setup();
 194 +
 195 +       ath79_register_mdio(0, 0x0);
 196 +
 197 +       ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
 198 +
 199 +       mdiobus_register_board_info(ap136_mdio0_info,
 200 +                                   ARRAY_SIZE(ap136_mdio0_info));
 201 +
 202 +       /* GMAC0 is connected to the RMGII interface */
 203 +       ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 204 +       ath79_eth0_data.phy_mask = BIT(0);
 205 +       ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 206 +
 207 +       ath79_register_eth(0);
 208 +
 209 +       /* GMAC1 is connected tot eh SGMII interface */
 210 +       ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
 211 +       ath79_eth1_data.speed = SPEED_1000;
 212 +       ath79_eth1_data.duplex = DUPLEX_FULL;
 213 +
 214 +       ath79_register_eth(1);
 215 +}
 216 +
 217 +static void __init ap136_010_setup(void)
 218 +{
 219 +       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 220 +
 221 +       /* GMAC0 of the AR8327 switch is connected to GMAC0 via RGMII */
 222 +       ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_RGMII;
 223 +       ap136_ar8327_pad0_cfg.txclk_delay_en = true;
 224 +       ap136_ar8327_pad0_cfg.rxclk_delay_en = true;
 225 +       ap136_ar8327_pad0_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
 226 +       ap136_ar8327_pad0_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
 227 +
 228 +       /* GMAC6 of the AR8327 switch is connected to GMAC1 via SGMII */
 229 +       ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_SGMII;
 230 +       ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
 231 +       ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL0;
 232 +
 233 +       ath79_eth0_pll_data.pll_1000 = 0xa6000000;
 234 +       ath79_eth1_pll_data.pll_1000 = 0x03000101;
 235 +
 236 +       ap136_common_setup();
 237 +       ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
 238  }
 239
 240  MIPS_MACHINE(ATH79_MACH_AP136_010, "AP136-010",
 241              "Atheros AP136-010 reference board",
 242 -            ap136_setup);
 243 +            ap136_010_setup);
 244 +
 245 +static void __init ap136_020_common_setup(void)
 246 +{
 247 +       /* GMAC0 of the AR8327 switch is connected to GMAC1 via SGMII */
 248 +       ap136_ar8327_pad0_cfg.mode = AR8327_PAD_MAC_SGMII;
 249 +       ap136_ar8327_pad0_cfg.sgmii_delay_en = true;
 250 +
 251 +       /* GMAC6 of the AR8327 switch is connected to GMAC0 via RGMII */
 252 +       ap136_ar8327_pad6_cfg.mode = AR8327_PAD_MAC_RGMII;
 253 +       ap136_ar8327_pad6_cfg.txclk_delay_en = true;
 254 +       ap136_ar8327_pad6_cfg.rxclk_delay_en = true;
 255 +       ap136_ar8327_pad6_cfg.txclk_delay_sel = AR8327_CLK_DELAY_SEL1;
 256 +       ap136_ar8327_pad6_cfg.rxclk_delay_sel = AR8327_CLK_DELAY_SEL2;
 257 +
 258 +       ath79_eth0_pll_data.pll_1000 = 0x56000000;
 259 +       ath79_eth1_pll_data.pll_1000 = 0x03000101;
 260 +
 261 +       ap136_common_setup();
 262 +}
 263 +
 264 +static void __init ap136_020_setup(void)
 265 +{
 266 +       u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 267 +
 268 +       ap136_020_common_setup();
 269 +       ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
 270 +}
 271 +
 272 +MIPS_MACHINE(ATH79_MACH_AP136_020, "AP136-020",
 273 +            "Atheros AP136-020 reference board",
 274 +            ap136_020_setup);
 275 +
 276 +/*
 277 + * AP135-020 is similar to AP136-020, any future AP135 specific init
 278 + * code can be added here.
 279 + */
 280 +static void __init ap135_020_setup(void)
 281 +{
 282 +       ap136_leds_gpio[0].name = "ap135:green:status";
 283 +       ap136_leds_gpio[1].name = "ap135:red:status";
 284 +       ap136_leds_gpio[2].name = "ap135:green:wps";
 285 +       ap136_leds_gpio[3].name = "ap135:red:wps";
 286 +       ap136_leds_gpio[4].name = "ap135:red:wlan-2g";
 287 +       ap136_leds_gpio[5].name = "ap135:red:usb";
 288 +
 289 +       ap136_020_common_setup();
 290 +       ath79_register_pci();
 291 +}
 292 +
 293 +MIPS_MACHINE(ATH79_MACH_AP135_020, "AP135-020",
 294 +            "Atheros AP135-020 reference board",
 295 +            ap135_020_setup);
 296 --- a/arch/mips/ath79/machtypes.h
 297 +++ b/arch/mips/ath79/machtypes.h
 298 @@ -18,7 +18,9 @@ enum ath79_mach_type {
 299         ATH79_MACH_GENERIC = 0,
 300         ATH79_MACH_AP121,               /* Atheros AP121 reference board */
 301         ATH79_MACH_AP121_MINI,          /* Atheros AP121-MINI reference board */
 302 +       ATH79_MACH_AP135_020,           /* Atheros AP135-020 reference board */
 303         ATH79_MACH_AP136_010,           /* Atheros AP136-010 reference board */
 304 +       ATH79_MACH_AP136_020,           /* Atheros AP136-020 reference board */
 305         ATH79_MACH_AP81,                /* Atheros AP81 reference board */
 306         ATH79_MACH_DB120,               /* Atheros DB120 reference board */
 307         ATH79_MACH_PB44,                /* Atheros PB44 reference board */
 308 --- a/arch/mips/ath79/Kconfig
 309 +++ b/arch/mips/ath79/Kconfig
 310 @@ -16,16 +16,17 @@ config ATH79_MACH_AP121
 311           Atheros AP121 reference board.
 312
 313  config ATH79_MACH_AP136
 314 -       bool "Atheros AP136 reference board"
 315 +       bool "Atheros AP136/AP135 reference board"
 316         select SOC_QCA955X
 317         select ATH79_DEV_GPIO_BUTTONS
 318         select ATH79_DEV_LEDS_GPIO
 319 +       select ATH79_DEV_NFC
 320         select ATH79_DEV_SPI
 321         select ATH79_DEV_USB
 322         select ATH79_DEV_WMAC
 323         help
 324           Say 'Y' here if you want your kernel to support the
 325 -         Atheros AP136 reference board.
 326 +         Atheros AP136 or AP135 reference boards.
 327
 328  config ATH79_MACH_AP81
 329         bool "Atheros AP81 reference board"