target/linux/ar71xx/patches-3.18/735-MIPS-ath79-add-support-for-QCA956x-SoC.patch

   1 --- a/arch/mips/ath79/Kconfig
   2 +++ b/arch/mips/ath79/Kconfig
   3 @@ -1213,6 +1213,12 @@ config SOC_QCA955X
   4         select PCI_AR724X if PCI
   5         def_bool n
   6
   7 +config SOC_QCA956X
   8 +       select USB_ARCH_HAS_EHCI
   9 +       select HW_HAS_PCI
  10 +       select PCI_AR724X if PCI
  11 +       def_bool n
  12 +
  13  config ATH79_DEV_M25P80
  14         select ATH79_DEV_SPI
  15         def_bool n
  16 @@ -1250,7 +1256,7 @@ config ATH79_DEV_USB
  17         def_bool n
  18
  19  config ATH79_DEV_WMAC
  20 -       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
  21 +       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X || SOC_QCA956X)
  22         def_bool n
  23
  24  config ATH79_NVRAM
  25 --- a/arch/mips/ath79/clock.c
  26 +++ b/arch/mips/ath79/clock.c
  27 @@ -520,6 +520,100 @@ static void __init qca955x_clocks_init(v
  28         clk_add_alias("uart", NULL, "ref", NULL);
  29  }
  30
  31 +static void __init qca956x_clocks_init(void)
  32 +{
  33 +       unsigned long ref_rate;
  34 +       unsigned long cpu_rate;
  35 +       unsigned long ddr_rate;
  36 +       unsigned long ahb_rate;
  37 +       u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv;
  38 +       u32 cpu_pll, ddr_pll;
  39 +       u32 bootstrap;
  40 +
  41 +       bootstrap = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
  42 +       if (bootstrap & QCA956X_BOOTSTRAP_REF_CLK_40)
  43 +               ref_rate = 40 * 1000 * 1000;
  44 +       else
  45 +               ref_rate = 25 * 1000 * 1000;
  46 +
  47 +       pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG_REG);
  48 +       out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  49 +                 QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
  50 +       ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  51 +                 QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
  52 +
  53 +       pll = ath79_pll_rr(QCA956X_PLL_CPU_CONFIG1_REG);
  54 +       nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
  55 +              QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
  56 +       hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
  57 +              QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
  58 +       lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
  59 +              QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
  60 +
  61 +       cpu_pll = nint * ref_rate / ref_div;
  62 +       cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
  63 +       cpu_pll += (hfrac >> 13) * ref_rate / ref_div;
  64 +       cpu_pll /= (1 << out_div);
  65 +
  66 +       pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG_REG);
  67 +       out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  68 +                 QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
  69 +       ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  70 +                 QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
  71 +       pll = ath79_pll_rr(QCA956X_PLL_DDR_CONFIG1_REG);
  72 +       nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
  73 +              QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
  74 +       hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
  75 +              QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
  76 +       lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
  77 +              QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
  78 +
  79 +       ddr_pll = nint * ref_rate / ref_div;
  80 +       ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
  81 +       ddr_pll += (hfrac >> 13) * ref_rate / ref_div;
  82 +       ddr_pll /= (1 << out_div);
  83 +
  84 +       clk_ctrl = ath79_pll_rr(QCA956X_PLL_CLK_CTRL_REG);
  85 +
  86 +       postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  87 +                 QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  88 +
  89 +       if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
  90 +               cpu_rate = ref_rate;
  91 +       else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL)
  92 +               cpu_rate = ddr_pll / (postdiv + 1);
  93 +       else
  94 +               cpu_rate = cpu_pll / (postdiv + 1);
  95 +
  96 +       postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
  97 +                 QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
  98 +
  99 +       if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
 100 +               ddr_rate = ref_rate;
 101 +       else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL)
 102 +               ddr_rate = cpu_pll / (postdiv + 1);
 103 +       else
 104 +               ddr_rate = ddr_pll / (postdiv + 1);
 105 +
 106 +       postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 107 +                 QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
 108 +
 109 +       if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
 110 +               ahb_rate = ref_rate;
 111 +       else if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 112 +               ahb_rate = ddr_pll / (postdiv + 1);
 113 +       else
 114 +               ahb_rate = cpu_pll / (postdiv + 1);
 115 +
 116 +       ath79_add_sys_clkdev("ref", ref_rate);
 117 +       ath79_add_sys_clkdev("cpu", cpu_rate);
 118 +       ath79_add_sys_clkdev("ddr", ddr_rate);
 119 +       ath79_add_sys_clkdev("ahb", ahb_rate);
 120 +
 121 +       clk_add_alias("wdt", NULL, "ref", NULL);
 122 +       clk_add_alias("uart", NULL, "ref", NULL);
 123 +}
 124 +
 125  void __init ath79_clocks_init(void)
 126  {
 127         if (soc_is_ar71xx())
 128 @@ -536,6 +630,8 @@ void __init ath79_clocks_init(void)
 129                 qca953x_clocks_init();
 130         else if (soc_is_qca955x())
 131                 qca955x_clocks_init();
 132 +       else if (soc_is_qca956x())
 133 +               qca956x_clocks_init();
 134         else
 135                 BUG();
 136  }
 137 --- a/arch/mips/ath79/common.c
 138 +++ b/arch/mips/ath79/common.c
 139 @@ -77,6 +77,8 @@ void ath79_device_reset_set(u32 mask)
 140                 reg = QCA953X_RESET_REG_RESET_MODULE;
 141         else if (soc_is_qca955x())
 142                 reg = QCA955X_RESET_REG_RESET_MODULE;
 143 +       else if (soc_is_qca956x())
 144 +               reg = QCA956X_RESET_REG_RESET_MODULE;
 145         else
 146                 panic("Reset register not defined for this SOC");
 147
 148 @@ -107,6 +109,8 @@ void ath79_device_reset_clear(u32 mask)
 149                 reg = QCA953X_RESET_REG_RESET_MODULE;
 150         else if (soc_is_qca955x())
 151                 reg = QCA955X_RESET_REG_RESET_MODULE;
 152 +       else if (soc_is_qca956x())
 153 +               reg = QCA956X_RESET_REG_RESET_MODULE;
 154         else
 155                 panic("Reset register not defined for this SOC");
 156
 157 --- a/arch/mips/ath79/dev-common.c
 158 +++ b/arch/mips/ath79/dev-common.c
 159 @@ -94,7 +94,8 @@ void __init ath79_register_uart(void)
 160             soc_is_ar913x() ||
 161             soc_is_ar934x() ||
 162             soc_is_qca953x() ||
 163 -           soc_is_qca955x()) {
 164 +           soc_is_qca955x() ||
 165 +           soc_is_qca956x()) {
 166                 ath79_uart_data[0].uartclk = uart_clk_rate;
 167                 platform_device_register(&ath79_uart_device);
 168         } else if (soc_is_ar933x()) {
 169 --- a/arch/mips/ath79/dev-usb.c
 170 +++ b/arch/mips/ath79/dev-usb.c
 171 @@ -296,6 +296,19 @@ static void __init qca955x_usb_setup(voi
 172                            &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
 173  }
 174
 175 +static void __init qca956x_usb_setup(void)
 176 +{
 177 +       ath79_usb_register("ehci-platform", 0,
 178 +                          QCA956X_EHCI0_BASE, QCA956X_EHCI_SIZE,
 179 +                          ATH79_IP3_IRQ(0),
 180 +                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
 181 +
 182 +       ath79_usb_register("ehci-platform", 1,
 183 +                          QCA956X_EHCI1_BASE, QCA956X_EHCI_SIZE,
 184 +                          ATH79_IP3_IRQ(1),
 185 +                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
 186 +}
 187 +
 188  void __init ath79_register_usb(void)
 189  {
 190         if (soc_is_ar71xx())
 191 @@ -314,6 +327,8 @@ void __init ath79_register_usb(void)
 192                 qca953x_usb_setup();
 193         else if (soc_is_qca955x())
 194                 qca955x_usb_setup();
 195 +       else if (soc_is_qca9561())
 196 +               qca956x_usb_setup();
 197         else
 198                 BUG();
 199  }
 200 --- a/arch/mips/ath79/dev-wmac.c
 201 +++ b/arch/mips/ath79/dev-wmac.c
 202 @@ -189,6 +189,24 @@ static void qca955x_wmac_setup(void)
 203                 ath79_wmac_data.is_clk_25mhz = true;
 204  }
 205
 206 +static void qca956x_wmac_setup(void)
 207 +{
 208 +       u32 t;
 209 +
 210 +       ath79_wmac_device.name = "qca956x_wmac";
 211 +
 212 +       ath79_wmac_resources[0].start = QCA956X_WMAC_BASE;
 213 +       ath79_wmac_resources[0].end = QCA956X_WMAC_BASE + QCA956X_WMAC_SIZE - 1;
 214 +       ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
 215 +       ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
 216 +
 217 +       t = ath79_reset_rr(QCA956X_RESET_REG_BOOTSTRAP);
 218 +       if (t & QCA956X_BOOTSTRAP_REF_CLK_40)
 219 +               ath79_wmac_data.is_clk_25mhz = false;
 220 +       else
 221 +               ath79_wmac_data.is_clk_25mhz = true;
 222 +}
 223 +
 224  static bool __init
 225  ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
 226  {
 227 @@ -392,6 +410,8 @@ void __init ath79_register_wmac(u8 *cal_
 228                 qca953x_wmac_setup();
 229         else if (soc_is_qca955x())
 230                 qca955x_wmac_setup();
 231 +       else if (soc_is_qca956x())
 232 +               qca956x_wmac_setup();
 233         else
 234                 BUG();
 235
 236 --- a/arch/mips/ath79/early_printk.c
 237 +++ b/arch/mips/ath79/early_printk.c
 238 @@ -118,6 +118,8 @@ static void prom_putchar_init(void)
 239         case REV_ID_MAJOR_QCA9533_V2:
 240         case REV_ID_MAJOR_QCA9556:
 241         case REV_ID_MAJOR_QCA9558:
 242 +       case REV_ID_MAJOR_TP9343:
 243 +       case REV_ID_MAJOR_QCA9561:
 244                 _prom_putchar = prom_putchar_ar71xx;
 245                 break;
 246
 247 --- a/arch/mips/ath79/gpio.c
 248 +++ b/arch/mips/ath79/gpio.c
 249 @@ -148,7 +148,8 @@ static void __iomem *ath79_gpio_get_func
 250             soc_is_ar913x() ||
 251             soc_is_ar933x())
 252                 reg = AR71XX_GPIO_REG_FUNC;
 253 -       else if (soc_is_ar934x() || soc_is_qca953x())
 254 +       else if (soc_is_ar934x() ||
 255 +                soc_is_qca953x() || soc_is_qca956x())
 256                 reg = AR934X_GPIO_REG_FUNC;
 257         else
 258                 BUG();
 259 @@ -228,12 +229,15 @@ void __init ath79_gpio_init(void)
 260                 ath79_gpio_count = QCA953X_GPIO_COUNT;
 261         else if (soc_is_qca955x())
 262                 ath79_gpio_count = QCA955X_GPIO_COUNT;
 263 +       else if (soc_is_qca956x())
 264 +               ath79_gpio_count = QCA956X_GPIO_COUNT;
 265         else
 266                 BUG();
 267
 268         ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 269         ath79_gpio_chip.ngpio = ath79_gpio_count;
 270 -       if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
 271 +       if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x() ||
 272 +           soc_is_qca956x()) {
 273                 ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
 274                 ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
 275         }
 276 --- a/arch/mips/ath79/irq.c
 277 +++ b/arch/mips/ath79/irq.c
 278 @@ -107,7 +107,8 @@ static void __init ath79_misc_irq_init(v
 279                  soc_is_ar933x() ||
 280                  soc_is_ar934x() ||
 281                  soc_is_qca953x() ||
 282 -                soc_is_qca955x())
 283 +                soc_is_qca955x() ||
 284 +                soc_is_qca956x())
 285                 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
 286         else
 287                 BUG();
 288 @@ -268,6 +269,97 @@ static void qca955x_irq_init(void)
 289         irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
 290  }
 291
 292 +static void qca956x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
 293 +{
 294 +       u32 status;
 295 +
 296 +       disable_irq_nosync(irq);
 297 +
 298 +       status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
 299 +       status &= QCA956X_EXT_INT_PCIE_RC1_ALL | QCA956X_EXT_INT_WMAC_ALL;
 300 +
 301 +       if (status == 0) {
 302 +               spurious_interrupt();
 303 +               goto enable;
 304 +       }
 305 +
 306 +       if (status & QCA956X_EXT_INT_PCIE_RC1_ALL) {
 307 +               /* TODO: flush DDR? */
 308 +               generic_handle_irq(ATH79_IP2_IRQ(0));
 309 +       }
 310 +
 311 +       if (status & QCA956X_EXT_INT_WMAC_ALL) {
 312 +               /* TODO: flsuh DDR? */
 313 +               generic_handle_irq(ATH79_IP2_IRQ(1));
 314 +       }
 315 +
 316 +enable:
 317 +       enable_irq(irq);
 318 +}
 319 +
 320 +static void qca956x_ip3_irq_dispatch(unsigned int irq, struct irq_desc *desc)
 321 +{
 322 +       u32 status;
 323 +
 324 +       disable_irq_nosync(irq);
 325 +
 326 +       status = ath79_reset_rr(QCA956X_RESET_REG_EXT_INT_STATUS);
 327 +       status &= QCA956X_EXT_INT_PCIE_RC2_ALL |
 328 +                 QCA956X_EXT_INT_USB1 | QCA956X_EXT_INT_USB2;
 329 +
 330 +       if (status == 0) {
 331 +               spurious_interrupt();
 332 +               goto enable;
 333 +       }
 334 +
 335 +       if (status & QCA956X_EXT_INT_USB1) {
 336 +               /* TODO: flush DDR? */
 337 +               generic_handle_irq(ATH79_IP3_IRQ(0));
 338 +       }
 339 +
 340 +       if (status & QCA956X_EXT_INT_USB2) {
 341 +               /* TODO: flush DDR? */
 342 +               generic_handle_irq(ATH79_IP3_IRQ(1));
 343 +       }
 344 +
 345 +       if (status & QCA956X_EXT_INT_PCIE_RC2_ALL) {
 346 +               /* TODO: flush DDR? */
 347 +               generic_handle_irq(ATH79_IP3_IRQ(2));
 348 +       }
 349 +
 350 +enable:
 351 +       enable_irq(irq);
 352 +}
 353 +
 354 +static void qca956x_enable_timer_cb(void) {
 355 +       u32 misc;
 356 +
 357 +       misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 358 +       misc |= MISC_INT_MIPS_SI_TIMERINT_MASK;
 359 +       ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);
 360 +}
 361 +
 362 +static void qca956x_irq_init(void)
 363 +{
 364 +       int i;
 365 +
 366 +       for (i = ATH79_IP2_IRQ_BASE;
 367 +            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 368 +               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 369 +
 370 +       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
 371 +
 372 +       for (i = ATH79_IP3_IRQ_BASE;
 373 +            i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
 374 +               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 375 +
 376 +       irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
 377 +
 378 +       /* QCA956x timer init workaround has to be applied right before setting
 379 +        * up the clock. Else, there will be no jiffies */
 380 +       late_time_init = &qca956x_enable_timer_cb;
 381 +}
 382 +
 383  asmlinkage void plat_irq_dispatch(void)
 384  {
 385         unsigned long pending;
 386 @@ -397,6 +489,9 @@ void __init arch_init_irq(void)
 387         } else if (soc_is_qca955x()) {
 388                 ath79_ip2_handler = ath79_default_ip2_handler;
 389                 ath79_ip3_handler = ath79_default_ip3_handler;
 390 +       } else if (soc_is_qca956x()) {
 391 +               ath79_ip2_handler = ath79_default_ip2_handler;
 392 +               ath79_ip3_handler = ath79_default_ip3_handler;
 393         } else {
 394                 BUG();
 395         }
 396 @@ -411,4 +506,6 @@ void __init arch_init_irq(void)
 397                 qca953x_irq_init();
 398         else if (soc_is_qca955x())
 399                 qca955x_irq_init();
 400 +       else if (soc_is_qca956x())
 401 +               qca956x_irq_init();
 402  }
 403 --- a/arch/mips/ath79/pci.c
 404 +++ b/arch/mips/ath79/pci.c
 405 @@ -68,6 +68,21 @@ static const struct ath79_pci_irq qca955
 406         },
 407  };
 408
 409 +static const struct ath79_pci_irq qca956x_pci_irq_map[] __initconst = {
 410 +       {
 411 +               .bus    = 0,
 412 +               .slot   = 0,
 413 +               .pin    = 1,
 414 +               .irq    = ATH79_PCI_IRQ(0),
 415 +       },
 416 +       {
 417 +               .bus    = 1,
 418 +               .slot   = 0,
 419 +               .pin    = 1,
 420 +               .irq    = ATH79_PCI_IRQ(1),
 421 +       },
 422 +};
 423 +
 424  int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
 425  {
 426         int irq = -1;
 427 @@ -86,6 +101,9 @@ int __init pcibios_map_irq(const struct
 428                 } else if (soc_is_qca955x()) {
 429                         ath79_pci_irq_map = qca955x_pci_irq_map;
 430                         ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
 431 +               } else if (soc_is_qca9561()) {
 432 +                       ath79_pci_irq_map = qca956x_pci_irq_map;
 433 +                       ath79_pci_nr_irqs = ARRAY_SIZE(qca956x_pci_irq_map);
 434                 } else {
 435                         pr_crit("pci %s: invalid irq map\n",
 436                                 pci_name((struct pci_dev *) dev));
 437 @@ -303,6 +321,15 @@ int __init ath79_register_pci(void)
 438                                                  QCA955X_PCI_MEM_SIZE,
 439                                                  1,
 440                                                  ATH79_IP3_IRQ(2));
 441 +       } else if (soc_is_qca9561()) {
 442 +               pdev = ath79_register_pci_ar724x(0,
 443 +                                                QCA956X_PCI_CFG_BASE1,
 444 +                                                QCA956X_PCI_CTRL_BASE1,
 445 +                                                QCA956X_PCI_CRP_BASE1,
 446 +                                                QCA956X_PCI_MEM_BASE1,
 447 +                                                QCA956X_PCI_MEM_SIZE,
 448 +                                                1,
 449 +                                                ATH79_IP3_IRQ(2));
 450         } else {
 451                 /* No PCI support */
 452                 return -ENODEV;
 453 --- a/arch/mips/ath79/setup.c
 454 +++ b/arch/mips/ath79/setup.c
 455 @@ -175,14 +175,29 @@ static void __init ath79_detect_sys_type
 456                 rev = id & QCA955X_REV_ID_REVISION_MASK;
 457                 break;
 458
 459 +       case REV_ID_MAJOR_TP9343:
 460 +               ath79_soc = ATH79_SOC_TP9343;
 461 +               chip = "9343";
 462 +               rev = id & QCA956X_REV_ID_REVISION_MASK;
 463 +               break;
 464 +
 465 +       case REV_ID_MAJOR_QCA9561:
 466 +               ath79_soc = ATH79_SOC_QCA9561;
 467 +               chip = "9561";
 468 +               rev = id & QCA956X_REV_ID_REVISION_MASK;
 469 +               break;
 470 +
 471         default:
 472                 panic("ath79: unknown SoC, id:0x%08x", id);
 473         }
 474
 475         ath79_soc_rev = rev;
 476
 477 -       if (soc_is_qca953x() || soc_is_qca955x())
 478 -               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
 479 +       if (soc_is_qca953x() || soc_is_qca955x() || soc_is_qca9561())
 480 +               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
 481 +                       chip, ver, rev);
 482 +       else if (soc_is_tp9343())
 483 +               sprintf(ath79_sys_type, "Qualcomm Atheros TP%s rev %u",
 484                         chip, rev);
 485         else
 486                 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
 487 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 488 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 489 @@ -143,6 +143,23 @@
 490  #define QCA955X_NFC_BASE       0x1b800200
 491  #define QCA955X_NFC_SIZE       0xb8
 492
 493 +#define QCA956X_PCI_MEM_BASE1  0x12000000
 494 +#define QCA956X_PCI_MEM_SIZE   0x02000000
 495 +#define QCA956X_PCI_CFG_BASE1  0x16000000
 496 +#define QCA956X_PCI_CFG_SIZE   0x1000
 497 +#define QCA956X_PCI_CRP_BASE1  (AR71XX_APB_BASE + 0x00250000)
 498 +#define QCA956X_PCI_CRP_SIZE   0x1000
 499 +#define QCA956X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
 500 +#define QCA956X_PCI_CTRL_SIZE  0x100
 501 +
 502 +#define QCA956X_WMAC_BASE      (AR71XX_APB_BASE + 0x00100000)
 503 +#define QCA956X_WMAC_SIZE      0x20000
 504 +#define QCA956X_EHCI0_BASE     0x1b000000
 505 +#define QCA956X_EHCI1_BASE     0x1b400000
 506 +#define QCA956X_EHCI_SIZE      0x200
 507 +#define QCA956X_GMAC_BASE      (AR71XX_APB_BASE + 0x00070000)
 508 +#define QCA956X_GMAC_SIZE      0x64
 509 +
 510  #define AR9300_OTP_BASE                0x14000
 511  #define AR9300_OTP_STATUS      0x15f18
 512  #define AR9300_OTP_STATUS_TYPE         0x7
 513 @@ -375,6 +392,49 @@
 514  #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL                BIT(21)
 515  #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL                BIT(24)
 516
 517 +#define QCA956X_PLL_CPU_CONFIG_REG                     0x00
 518 +#define QCA956X_PLL_CPU_CONFIG1_REG                    0x04
 519 +#define QCA956X_PLL_DDR_CONFIG_REG                     0x08
 520 +#define QCA956X_PLL_DDR_CONFIG1_REG                    0x0c
 521 +#define QCA956X_PLL_CLK_CTRL_REG                       0x10
 522 +
 523 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT            12
 524 +#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK             0x1f
 525 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT            19
 526 +#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK             0x7
 527 +
 528 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT          0
 529 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK           0x1f
 530 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT          5
 531 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK           0x3fff
 532 +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT             18
 533 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK              0x1ff
 534 +
 535 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT            16
 536 +#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK             0x1f
 537 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT            23
 538 +#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK             0x7
 539 +
 540 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT          0
 541 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK           0x1f
 542 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT          5
 543 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK           0x3fff
 544 +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT             18
 545 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK              0x1ff
 546 +
 547 +#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS            BIT(2)
 548 +#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS            BIT(3)
 549 +#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS            BIT(4)
 550 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT                5
 551 +#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK         0x1f
 552 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT                10
 553 +#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK         0x1f
 554 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT                15
 555 +#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK         0x1f
 556 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL    BIT(20)
 557 +#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL    BIT(21)
 558 +#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL                BIT(24)
 559 +
 560  /*
 561   * USB_CONFIG block
 562   */
 563 @@ -422,6 +482,11 @@
 564  #define QCA955X_RESET_REG_BOOTSTRAP            0xb0
 565  #define QCA955X_RESET_REG_EXT_INT_STATUS       0xac
 566
 567 +#define QCA956X_RESET_REG_RESET_MODULE         0x1c
 568 +#define QCA956X_RESET_REG_BOOTSTRAP            0xb0
 569 +#define QCA956X_RESET_REG_EXT_INT_STATUS       0xac
 570 +
 571 +#define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
 572  #define MISC_INT_ETHSW                 BIT(12)
 573  #define MISC_INT_TIMER4                        BIT(10)
 574  #define MISC_INT_TIMER3                        BIT(9)
 575 @@ -596,6 +661,8 @@
 576
 577  #define QCA955X_BOOTSTRAP_REF_CLK_40   BIT(4)
 578
 579 +#define QCA956X_BOOTSTRAP_REF_CLK_40   BIT(2)
 580 +
 581  #define AR934X_PCIE_WMAC_INT_WMAC_MISC         BIT(0)
 582  #define AR934X_PCIE_WMAC_INT_WMAC_TX           BIT(1)
 583  #define AR934X_PCIE_WMAC_INT_WMAC_RXLP         BIT(2)
 584 @@ -663,6 +730,37 @@
 585          QCA955X_EXT_INT_PCIE_RC2_INT1 | QCA955X_EXT_INT_PCIE_RC2_INT2 | \
 586          QCA955X_EXT_INT_PCIE_RC2_INT3)
 587
 588 +#define QCA956X_EXT_INT_WMAC_MISC              BIT(0)
 589 +#define QCA956X_EXT_INT_WMAC_TX                        BIT(1)
 590 +#define QCA956X_EXT_INT_WMAC_RXLP              BIT(2)
 591 +#define QCA956X_EXT_INT_WMAC_RXHP              BIT(3)
 592 +#define QCA956X_EXT_INT_PCIE_RC1               BIT(4)
 593 +#define QCA956X_EXT_INT_PCIE_RC1_INT0          BIT(5)
 594 +#define QCA956X_EXT_INT_PCIE_RC1_INT1          BIT(6)
 595 +#define QCA956X_EXT_INT_PCIE_RC1_INT2          BIT(7)
 596 +#define QCA956X_EXT_INT_PCIE_RC1_INT3          BIT(8)
 597 +#define QCA956X_EXT_INT_PCIE_RC2               BIT(12)
 598 +#define QCA956X_EXT_INT_PCIE_RC2_INT0          BIT(13)
 599 +#define QCA956X_EXT_INT_PCIE_RC2_INT1          BIT(14)
 600 +#define QCA956X_EXT_INT_PCIE_RC2_INT2          BIT(15)
 601 +#define QCA956X_EXT_INT_PCIE_RC2_INT3          BIT(16)
 602 +#define QCA956X_EXT_INT_USB1                   BIT(24)
 603 +#define QCA956X_EXT_INT_USB2                   BIT(28)
 604 +
 605 +#define QCA956X_EXT_INT_WMAC_ALL \
 606 +       (QCA956X_EXT_INT_WMAC_MISC | QCA956X_EXT_INT_WMAC_TX | \
 607 +        QCA956X_EXT_INT_WMAC_RXLP | QCA956X_EXT_INT_WMAC_RXHP)
 608 +
 609 +#define QCA956X_EXT_INT_PCIE_RC1_ALL \
 610 +       (QCA956X_EXT_INT_PCIE_RC1 | QCA956X_EXT_INT_PCIE_RC1_INT0 | \
 611 +        QCA956X_EXT_INT_PCIE_RC1_INT1 | QCA956X_EXT_INT_PCIE_RC1_INT2 | \
 612 +        QCA956X_EXT_INT_PCIE_RC1_INT3)
 613 +
 614 +#define QCA956X_EXT_INT_PCIE_RC2_ALL \
 615 +       (QCA956X_EXT_INT_PCIE_RC2 | QCA956X_EXT_INT_PCIE_RC2_INT0 | \
 616 +        QCA956X_EXT_INT_PCIE_RC2_INT1 | QCA956X_EXT_INT_PCIE_RC2_INT2 | \
 617 +        QCA956X_EXT_INT_PCIE_RC2_INT3)
 618 +
 619  #define REV_ID_MAJOR_MASK              0xfff0
 620  #define REV_ID_MAJOR_AR71XX            0x00a0
 621  #define REV_ID_MAJOR_AR913X            0x00b0
 622 @@ -678,6 +776,8 @@
 623  #define REV_ID_MAJOR_QCA9533_V2                0x0160
 624  #define REV_ID_MAJOR_QCA9556           0x0130
 625  #define REV_ID_MAJOR_QCA9558           0x1130
 626 +#define REV_ID_MAJOR_TP9343            0x0150
 627 +#define REV_ID_MAJOR_QCA9561           0x1150
 628
 629  #define AR71XX_REV_ID_MINOR_MASK       0x3
 630  #define AR71XX_REV_ID_MINOR_AR7130     0x0
 631 @@ -702,6 +802,8 @@
 632
 633  #define QCA955X_REV_ID_REVISION_MASK   0xf
 634
 635 +#define QCA956X_REV_ID_REVISION_MASK   0xf
 636 +
 637  /*
 638   * SPI block
 639   */
 640 @@ -766,6 +868,19 @@
 641  #define QCA953X_GPIO_OUT_MUX_LED_LINK4         44
 642  #define QCA953X_GPIO_OUT_MUX_LED_LINK5         45
 643
 644 +#define QCA956X_GPIO_REG_OUT_FUNC0     0x2c
 645 +#define QCA956X_GPIO_REG_OUT_FUNC1     0x30
 646 +#define QCA956X_GPIO_REG_OUT_FUNC2     0x34
 647 +#define QCA956X_GPIO_REG_OUT_FUNC3     0x38
 648 +#define QCA956X_GPIO_REG_OUT_FUNC4     0x3c
 649 +#define QCA956X_GPIO_REG_OUT_FUNC5     0x40
 650 +#define QCA956X_GPIO_REG_IN_ENABLE0    0x44
 651 +#define QCA956X_GPIO_REG_IN_ENABLE3    0x50
 652 +#define QCA956X_GPIO_REG_FUNC          0x6c
 653 +
 654 +#define QCA956X_GPIO_OUT_MUX_GE0_MDO   32
 655 +#define QCA956X_GPIO_OUT_MUX_GE0_MDC   33
 656 +
 657  #define AR71XX_GPIO_COUNT              16
 658  #define AR7240_GPIO_COUNT              18
 659  #define AR7241_GPIO_COUNT              20
 660 @@ -774,6 +889,7 @@
 661  #define AR934X_GPIO_COUNT              23
 662  #define QCA953X_GPIO_COUNT             18
 663  #define QCA955X_GPIO_COUNT             24
 664 +#define QCA956X_GPIO_COUNT             23
 665
 666  /*
 667   * SRIF block
 668 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 669 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
 670 @@ -35,6 +35,8 @@ enum ath79_soc_type {
 671         ATH79_SOC_QCA9533,
 672         ATH79_SOC_QCA9556,
 673         ATH79_SOC_QCA9558,
 674 +       ATH79_SOC_TP9343,
 675 +       ATH79_SOC_QCA9561,
 676  };
 677
 678  extern enum ath79_soc_type ath79_soc;
 679 @@ -126,6 +128,21 @@ static inline int soc_is_qca955x(void)
 680         return soc_is_qca9556() || soc_is_qca9558();
 681  }
 682
 683 +static inline int soc_is_tp9343(void)
 684 +{
 685 +       return ath79_soc == ATH79_SOC_TP9343;
 686 +}
 687 +
 688 +static inline int soc_is_qca9561(void)
 689 +{
 690 +       return ath79_soc == ATH79_SOC_QCA9561;
 691 +}
 692 +
 693 +static inline int soc_is_qca956x(void)
 694 +{
 695 +       return soc_is_tp9343() || soc_is_qca9561();
 696 +}
 697 +
 698  extern void __iomem *ath79_ddr_base;
 699  extern void __iomem *ath79_gpio_base;
 700  extern void __iomem *ath79_pll_base;