ar71xx: add initial support for 3.2
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / patches-3.2 / 306-spi-rb4xx-3.2-fixes.patch
1 --- a/drivers/spi/spi-rb4xx.c
2 +++ b/drivers/spi/spi-rb4xx.c
3 @@ -12,7 +12,10 @@
4 *
5 */
6
7 +#include <linux/clk.h>
8 +#include <linux/err.h>
9 #include <linux/kernel.h>
10 +#include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/spinlock.h>
14 @@ -20,7 +23,8 @@
15 #include <linux/platform_device.h>
16 #include <linux/spi/spi.h>
17
18 -#include <asm/mach-ar71xx/ar71xx.h>
19 +#include <asm/mach-ath79/ar71xx_regs.h>
20 +#include <asm/mach-ath79/ath79.h>
21
22 #define DRV_NAME "rb4xx-spi"
23 #define DRV_DESC "Mikrotik RB4xx SPI controller driver"
24 @@ -41,13 +45,16 @@ struct rb4xx_spi {
25 unsigned spi_ctrl_flash;
26 unsigned spi_ctrl_fread;
27
28 + struct clk *ahb_clk;
29 + unsigned long ahb_freq;
30 +
31 spinlock_t lock;
32 struct list_head queue;
33 int busy:1;
34 int cs_wait;
35 };
36
37 -static unsigned spi_clk_low = SPI_IOC_CS1;
38 +static unsigned spi_clk_low = AR71XX_SPI_IOC_CS1;
39
40 #ifdef RB4XX_SPI_DEBUG
41 static inline void do_spi_delay(void)
42 @@ -60,10 +67,11 @@ static inline void do_spi_delay(void) {
43
44 static inline void do_spi_init(struct spi_device *spi)
45 {
46 - unsigned cs = SPI_IOC_CS0 | SPI_IOC_CS1;
47 + unsigned cs = AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1;
48
49 if (!(spi->mode & SPI_CS_HIGH))
50 - cs ^= (spi->chip_select == 2) ? SPI_IOC_CS1 : SPI_IOC_CS0;
51 + cs ^= (spi->chip_select == 2) ? AR71XX_SPI_IOC_CS1 :
52 + AR71XX_SPI_IOC_CS0;
53
54 spi_clk_low = cs;
55 }
56 @@ -71,17 +79,18 @@ static inline void do_spi_init(struct sp
57 static inline void do_spi_finish(void __iomem *base)
58 {
59 do_spi_delay();
60 - __raw_writel(SPI_IOC_CS0 | SPI_IOC_CS1, base + SPI_REG_IOC);
61 + __raw_writel(AR71XX_SPI_IOC_CS0 | AR71XX_SPI_IOC_CS1,
62 + base + AR71XX_SPI_REG_IOC);
63 }
64
65 static inline void do_spi_clk(void __iomem *base, int bit)
66 {
67 - unsigned bval = spi_clk_low | ((bit & 1) ? SPI_IOC_DO : 0);
68 + unsigned bval = spi_clk_low | ((bit & 1) ? AR71XX_SPI_IOC_DO : 0);
69
70 do_spi_delay();
71 - __raw_writel(bval, base + SPI_REG_IOC);
72 + __raw_writel(bval, base + AR71XX_SPI_REG_IOC);
73 do_spi_delay();
74 - __raw_writel(bval | SPI_IOC_CLK, base + SPI_REG_IOC);
75 + __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
76 }
77
78 static void do_spi_byte(void __iomem *base, unsigned char byte)
79 @@ -97,19 +106,19 @@ static void do_spi_byte(void __iomem *ba
80
81 pr_debug("spi_byte sent 0x%02x got 0x%02x\n",
82 (unsigned)byte,
83 - (unsigned char)__raw_readl(base + SPI_REG_RDS));
84 + (unsigned char)__raw_readl(base + AR71XX_SPI_REG_RDS));
85 }
86
87 static inline void do_spi_clk_fast(void __iomem *base, unsigned bit1,
88 unsigned bit2)
89 {
90 unsigned bval = (spi_clk_low |
91 - ((bit1 & 1) ? SPI_IOC_DO : 0) |
92 - ((bit2 & 1) ? SPI_IOC_CS2 : 0));
93 + ((bit1 & 1) ? AR71XX_SPI_IOC_DO : 0) |
94 + ((bit2 & 1) ? AR71XX_SPI_IOC_CS2 : 0));
95 do_spi_delay();
96 - __raw_writel(bval, base + SPI_REG_IOC);
97 + __raw_writel(bval, base + AR71XX_SPI_REG_IOC);
98 do_spi_delay();
99 - __raw_writel(bval | SPI_IOC_CLK, base + SPI_REG_IOC);
100 + __raw_writel(bval | AR71XX_SPI_IOC_CLK, base + AR71XX_SPI_REG_IOC);
101 }
102
103 static void do_spi_byte_fast(void __iomem *base, unsigned char byte)
104 @@ -121,7 +130,7 @@ static void do_spi_byte_fast(void __iome
105
106 pr_debug("spi_byte_fast sent 0x%02x got 0x%02x\n",
107 (unsigned)byte,
108 - (unsigned char) __raw_readl(base + SPI_REG_RDS));
109 + (unsigned char) __raw_readl(base + AR71XX_SPI_REG_RDS));
110 }
111
112 static int rb4xx_spi_txrx(void __iomem *base, struct spi_transfer *t)
113 @@ -150,9 +159,9 @@ static int rb4xx_spi_txrx(void __iomem *
114 do_spi_byte(base, sdata);
115
116 if (rx_ptr) {
117 - rx_ptr[i] = __raw_readl(base + SPI_REG_RDS) & 0xff;
118 + rx_ptr[i] = __raw_readl(base + AR71XX_SPI_REG_RDS) & 0xff;
119 } else if (rxv_ptr) {
120 - unsigned char c = __raw_readl(base + SPI_REG_RDS);
121 + unsigned char c = __raw_readl(base + AR71XX_SPI_REG_RDS);
122 if (rxv_ptr[i] != c)
123 return i;
124 }
125 @@ -201,9 +210,9 @@ static int rb4xx_spi_read_fast(struct rb
126 if (t->tx_buf && !t->verify)
127 return -1;
128
129 - __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS);
130 - __raw_writel(rbspi->spi_ctrl_fread, base + SPI_REG_CTRL);
131 - __raw_writel(0, base + SPI_REG_FS);
132 + __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
133 + __raw_writel(rbspi->spi_ctrl_fread, base + AR71XX_SPI_REG_CTRL);
134 + __raw_writel(0, base + AR71XX_SPI_REG_FS);
135
136 if (t->rx_buf) {
137 memcpy(t->rx_buf, (const void *)addr, t->len);
138 @@ -216,9 +225,9 @@ static int rb4xx_spi_read_fast(struct rb
139 m->actual_length += t->len;
140
141 if (rbspi->spi_ctrl_flash != rbspi->spi_ctrl_fread) {
142 - __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS);
143 - __raw_writel(rbspi->spi_ctrl_flash, base + SPI_REG_CTRL);
144 - __raw_writel(0, base + SPI_REG_FS);
145 + __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
146 + __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL);
147 + __raw_writel(0, base + AR71XX_SPI_REG_FS);
148 }
149
150 return 0;
151 @@ -237,8 +246,8 @@ static int rb4xx_spi_msg(struct rb4xx_sp
152 if (rb4xx_spi_read_fast(rbspi, m) == 0)
153 return -1;
154
155 - __raw_writel(SPI_FS_GPIO, base + SPI_REG_FS);
156 - __raw_writel(SPI_CTRL_FASTEST, base + SPI_REG_CTRL);
157 + __raw_writel(AR71XX_SPI_FS_GPIO, base + AR71XX_SPI_REG_FS);
158 + __raw_writel(SPI_CTRL_FASTEST, base + AR71XX_SPI_REG_CTRL);
159 do_spi_init(m->spi);
160
161 list_for_each_entry(t, &m->transfers, transfer_list) {
162 @@ -262,8 +271,8 @@ static int rb4xx_spi_msg(struct rb4xx_sp
163 }
164
165 do_spi_finish(base);
166 - __raw_writel(rbspi->spi_ctrl_flash, base + SPI_REG_CTRL);
167 - __raw_writel(0, base + SPI_REG_FS);
168 + __raw_writel(rbspi->spi_ctrl_flash, base + AR71XX_SPI_REG_CTRL);
169 + __raw_writel(0, base + AR71XX_SPI_REG_FS);
170 return -1;
171 }
172
173 @@ -352,11 +361,12 @@ static int rb4xx_spi_setup(struct spi_de
174 return 0;
175 }
176
177 -static unsigned get_spi_ctrl(unsigned hz_max, const char *name)
178 +static unsigned get_spi_ctrl(struct rb4xx_spi *rbspi, unsigned hz_max,
179 + const char *name)
180 {
181 unsigned div;
182
183 - div = (ar71xx_ahb_freq - 1) / (2 * hz_max);
184 + div = (rbspi->ahb_freq - 1) / (2 * hz_max);
185
186 /*
187 * CPU has a bug at (div == 0) - first bit read is random
188 @@ -365,7 +375,7 @@ static unsigned get_spi_ctrl(unsigned hz
189 ++div;
190
191 if (name) {
192 - unsigned ahb_khz = (ar71xx_ahb_freq + 500) / 1000;
193 + unsigned ahb_khz = (rbspi->ahb_freq + 500) / 1000;
194 unsigned div_real = 2 * (div + 1);
195 pr_debug("rb4xx: %s SPI clock %u kHz (AHB %u kHz / %u)\n",
196 name,
197 @@ -396,23 +406,40 @@ static int rb4xx_spi_probe(struct platfo
198 master->transfer = rb4xx_spi_transfer;
199
200 rbspi = spi_master_get_devdata(master);
201 +
202 + rbspi->ahb_clk = clk_get(&pdev->dev, "AHB");
203 + if (IS_ERR(rbspi->ahb_clk)) {
204 + err = PTR_ERR(rbspi->ahb_clk);
205 + goto err_put_master;
206 + }
207 +
208 + err = clk_enable(rbspi->ahb_clk);
209 + if (err)
210 + goto err_clk_put;
211 +
212 + rbspi->ahb_freq = clk_get_rate(rbspi->ahb_clk);
213 + if (!rbspi->ahb_freq) {
214 + err = -EINVAL;
215 + goto err_clk_disable;
216 + }
217 +
218 platform_set_drvdata(pdev, rbspi);
219
220 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
221 if (r == NULL) {
222 err = -ENOENT;
223 - goto err_put_master;
224 + goto err_clk_disable;
225 }
226
227 rbspi->base = ioremap(r->start, r->end - r->start + 1);
228 if (!rbspi->base) {
229 err = -ENXIO;
230 - goto err_put_master;
231 + goto err_clk_disable;
232 }
233
234 rbspi->master = master;
235 - rbspi->spi_ctrl_flash = get_spi_ctrl(SPI_FLASH_HZ, "FLASH");
236 - rbspi->spi_ctrl_fread = get_spi_ctrl(SPI_CPLD_HZ, "CPLD");
237 + rbspi->spi_ctrl_flash = get_spi_ctrl(rbspi, SPI_FLASH_HZ, "FLASH");
238 + rbspi->spi_ctrl_fread = get_spi_ctrl(rbspi, SPI_CPLD_HZ, "CPLD");
239 rbspi->cs_wait = -1;
240
241 spin_lock_init(&rbspi->lock);
242 @@ -428,6 +455,10 @@ static int rb4xx_spi_probe(struct platfo
243
244 err_iounmap:
245 iounmap(rbspi->base);
246 +err_clk_disable:
247 + clk_disable(rbspi->ahb_clk);
248 +err_clk_put:
249 + clk_put(rbspi->ahb_clk);
250 err_put_master:
251 platform_set_drvdata(pdev, NULL);
252 spi_master_put(master);
253 @@ -440,6 +471,8 @@ static int rb4xx_spi_remove(struct platf
254 struct rb4xx_spi *rbspi = platform_get_drvdata(pdev);
255
256 iounmap(rbspi->base);
257 + clk_disable(rbspi->ahb_clk);
258 + clk_put(rbspi->ahb_clk);
259 platform_set_drvdata(pdev, NULL);
260 spi_master_put(rbspi->master);
261