ar71xx: add preliminary support for Mikrotik RB2011L
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / patches-3.3 / 104-MIPS-ath79-rename-pci-ath724x.c-to-make-it-reflect-t.patch
1 From 36dfdaa097ee1b12139187dc89cfa23fbb92b53b Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Wed, 14 Mar 2012 10:29:25 +0100
4 Subject: [PATCH 09/47] MIPS: ath79: rename pci-ath724x.c to make it reflect the real SoC name
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
10 Acked-by: René Bolldorf <xsecute@googlemail.com>
11 Cc: linux-mips@linux-mips.org
12 Patchwork: https://patchwork.linux-mips.org/patch/3489/
13 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
14 ---
15 arch/mips/pci/Makefile | 2 +-
16 arch/mips/pci/pci-ar724x.c | 139 +++++++++++++++++++++++++++++++++++++++++++
17 arch/mips/pci/pci-ath724x.c | 139 -------------------------------------------
18 3 files changed, 140 insertions(+), 140 deletions(-)
19 create mode 100644 arch/mips/pci/pci-ar724x.c
20 delete mode 100644 arch/mips/pci/pci-ath724x.c
21
22 --- a/arch/mips/pci/Makefile
23 +++ b/arch/mips/pci/Makefile
24 @@ -19,7 +19,7 @@ obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o
25 obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \
26 ops-bcm63xx.o
27 obj-$(CONFIG_MIPS_ALCHEMY) += pci-alchemy.o
28 -obj-$(CONFIG_SOC_AR724X) += pci-ath724x.o
29 +obj-$(CONFIG_SOC_AR724X) += pci-ar724x.o
30
31 #
32 # These are still pretty much in the old state, watch, go blind.
33 --- /dev/null
34 +++ b/arch/mips/pci/pci-ar724x.c
35 @@ -0,0 +1,139 @@
36 +/*
37 + * Atheros 724x PCI support
38 + *
39 + * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
40 + *
41 + * This program is free software; you can redistribute it and/or modify it
42 + * under the terms of the GNU General Public License version 2 as published
43 + * by the Free Software Foundation.
44 + */
45 +
46 +#include <linux/pci.h>
47 +#include <asm/mach-ath79/pci.h>
48 +
49 +#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
50 +#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
51 +
52 +#define ATH724X_PCI_DEV_BASE 0x14000000
53 +#define ATH724X_PCI_MEM_BASE 0x10000000
54 +#define ATH724X_PCI_MEM_SIZE 0x08000000
55 +
56 +static DEFINE_SPINLOCK(ath724x_pci_lock);
57 +
58 +static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
59 + int size, uint32_t *value)
60 +{
61 + unsigned long flags, addr, tval, mask;
62 +
63 + if (devfn)
64 + return PCIBIOS_DEVICE_NOT_FOUND;
65 +
66 + if (where & (size - 1))
67 + return PCIBIOS_BAD_REGISTER_NUMBER;
68 +
69 + spin_lock_irqsave(&ath724x_pci_lock, flags);
70 +
71 + switch (size) {
72 + case 1:
73 + addr = where & ~3;
74 + mask = 0xff000000 >> ((where % 4) * 8);
75 + tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
76 + tval = tval & ~mask;
77 + *value = (tval >> ((4 - (where % 4))*8));
78 + break;
79 + case 2:
80 + addr = where & ~3;
81 + mask = 0xffff0000 >> ((where % 4)*8);
82 + tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
83 + tval = tval & ~mask;
84 + *value = (tval >> ((4 - (where % 4))*8));
85 + break;
86 + case 4:
87 + *value = reg_read(ATH724X_PCI_DEV_BASE + where);
88 + break;
89 + default:
90 + spin_unlock_irqrestore(&ath724x_pci_lock, flags);
91 +
92 + return PCIBIOS_BAD_REGISTER_NUMBER;
93 + }
94 +
95 + spin_unlock_irqrestore(&ath724x_pci_lock, flags);
96 +
97 + return PCIBIOS_SUCCESSFUL;
98 +}
99 +
100 +static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
101 + int size, uint32_t value)
102 +{
103 + unsigned long flags, tval, addr, mask;
104 +
105 + if (devfn)
106 + return PCIBIOS_DEVICE_NOT_FOUND;
107 +
108 + if (where & (size - 1))
109 + return PCIBIOS_BAD_REGISTER_NUMBER;
110 +
111 + spin_lock_irqsave(&ath724x_pci_lock, flags);
112 +
113 + switch (size) {
114 + case 1:
115 + addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
116 + mask = 0xff000000 >> ((where % 4)*8);
117 + tval = reg_read(addr);
118 + tval = tval & ~mask;
119 + tval |= (value << ((4 - (where % 4))*8)) & mask;
120 + reg_write(addr, tval);
121 + break;
122 + case 2:
123 + addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
124 + mask = 0xffff0000 >> ((where % 4)*8);
125 + tval = reg_read(addr);
126 + tval = tval & ~mask;
127 + tval |= (value << ((4 - (where % 4))*8)) & mask;
128 + reg_write(addr, tval);
129 + break;
130 + case 4:
131 + reg_write((ATH724X_PCI_DEV_BASE + where), value);
132 + break;
133 + default:
134 + spin_unlock_irqrestore(&ath724x_pci_lock, flags);
135 +
136 + return PCIBIOS_BAD_REGISTER_NUMBER;
137 + }
138 +
139 + spin_unlock_irqrestore(&ath724x_pci_lock, flags);
140 +
141 + return PCIBIOS_SUCCESSFUL;
142 +}
143 +
144 +static struct pci_ops ath724x_pci_ops = {
145 + .read = ath724x_pci_read,
146 + .write = ath724x_pci_write,
147 +};
148 +
149 +static struct resource ath724x_io_resource = {
150 + .name = "PCI IO space",
151 + .start = 0,
152 + .end = 0,
153 + .flags = IORESOURCE_IO,
154 +};
155 +
156 +static struct resource ath724x_mem_resource = {
157 + .name = "PCI memory space",
158 + .start = ATH724X_PCI_MEM_BASE,
159 + .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
160 + .flags = IORESOURCE_MEM,
161 +};
162 +
163 +static struct pci_controller ath724x_pci_controller = {
164 + .pci_ops = &ath724x_pci_ops,
165 + .io_resource = &ath724x_io_resource,
166 + .mem_resource = &ath724x_mem_resource,
167 +};
168 +
169 +int __init ath724x_pcibios_init(void)
170 +{
171 + register_pci_controller(&ath724x_pci_controller);
172 +
173 + return PCIBIOS_SUCCESSFUL;
174 +}
175 --- a/arch/mips/pci/pci-ath724x.c
176 +++ /dev/null
177 @@ -1,139 +0,0 @@
178 -/*
179 - * Atheros 724x PCI support
180 - *
181 - * Copyright (C) 2011 René Bolldorf <xsecute@googlemail.com>
182 - *
183 - * This program is free software; you can redistribute it and/or modify it
184 - * under the terms of the GNU General Public License version 2 as published
185 - * by the Free Software Foundation.
186 - */
187 -
188 -#include <linux/pci.h>
189 -#include <asm/mach-ath79/pci.h>
190 -
191 -#define reg_read(_phys) (*(unsigned int *) KSEG1ADDR(_phys))
192 -#define reg_write(_phys, _val) ((*(unsigned int *) KSEG1ADDR(_phys)) = (_val))
193 -
194 -#define ATH724X_PCI_DEV_BASE 0x14000000
195 -#define ATH724X_PCI_MEM_BASE 0x10000000
196 -#define ATH724X_PCI_MEM_SIZE 0x08000000
197 -
198 -static DEFINE_SPINLOCK(ath724x_pci_lock);
199 -
200 -static int ath724x_pci_read(struct pci_bus *bus, unsigned int devfn, int where,
201 - int size, uint32_t *value)
202 -{
203 - unsigned long flags, addr, tval, mask;
204 -
205 - if (devfn)
206 - return PCIBIOS_DEVICE_NOT_FOUND;
207 -
208 - if (where & (size - 1))
209 - return PCIBIOS_BAD_REGISTER_NUMBER;
210 -
211 - spin_lock_irqsave(&ath724x_pci_lock, flags);
212 -
213 - switch (size) {
214 - case 1:
215 - addr = where & ~3;
216 - mask = 0xff000000 >> ((where % 4) * 8);
217 - tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
218 - tval = tval & ~mask;
219 - *value = (tval >> ((4 - (where % 4))*8));
220 - break;
221 - case 2:
222 - addr = where & ~3;
223 - mask = 0xffff0000 >> ((where % 4)*8);
224 - tval = reg_read(ATH724X_PCI_DEV_BASE + addr);
225 - tval = tval & ~mask;
226 - *value = (tval >> ((4 - (where % 4))*8));
227 - break;
228 - case 4:
229 - *value = reg_read(ATH724X_PCI_DEV_BASE + where);
230 - break;
231 - default:
232 - spin_unlock_irqrestore(&ath724x_pci_lock, flags);
233 -
234 - return PCIBIOS_BAD_REGISTER_NUMBER;
235 - }
236 -
237 - spin_unlock_irqrestore(&ath724x_pci_lock, flags);
238 -
239 - return PCIBIOS_SUCCESSFUL;
240 -}
241 -
242 -static int ath724x_pci_write(struct pci_bus *bus, unsigned int devfn, int where,
243 - int size, uint32_t value)
244 -{
245 - unsigned long flags, tval, addr, mask;
246 -
247 - if (devfn)
248 - return PCIBIOS_DEVICE_NOT_FOUND;
249 -
250 - if (where & (size - 1))
251 - return PCIBIOS_BAD_REGISTER_NUMBER;
252 -
253 - spin_lock_irqsave(&ath724x_pci_lock, flags);
254 -
255 - switch (size) {
256 - case 1:
257 - addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
258 - mask = 0xff000000 >> ((where % 4)*8);
259 - tval = reg_read(addr);
260 - tval = tval & ~mask;
261 - tval |= (value << ((4 - (where % 4))*8)) & mask;
262 - reg_write(addr, tval);
263 - break;
264 - case 2:
265 - addr = (ATH724X_PCI_DEV_BASE + where) & ~3;
266 - mask = 0xffff0000 >> ((where % 4)*8);
267 - tval = reg_read(addr);
268 - tval = tval & ~mask;
269 - tval |= (value << ((4 - (where % 4))*8)) & mask;
270 - reg_write(addr, tval);
271 - break;
272 - case 4:
273 - reg_write((ATH724X_PCI_DEV_BASE + where), value);
274 - break;
275 - default:
276 - spin_unlock_irqrestore(&ath724x_pci_lock, flags);
277 -
278 - return PCIBIOS_BAD_REGISTER_NUMBER;
279 - }
280 -
281 - spin_unlock_irqrestore(&ath724x_pci_lock, flags);
282 -
283 - return PCIBIOS_SUCCESSFUL;
284 -}
285 -
286 -static struct pci_ops ath724x_pci_ops = {
287 - .read = ath724x_pci_read,
288 - .write = ath724x_pci_write,
289 -};
290 -
291 -static struct resource ath724x_io_resource = {
292 - .name = "PCI IO space",
293 - .start = 0,
294 - .end = 0,
295 - .flags = IORESOURCE_IO,
296 -};
297 -
298 -static struct resource ath724x_mem_resource = {
299 - .name = "PCI memory space",
300 - .start = ATH724X_PCI_MEM_BASE,
301 - .end = ATH724X_PCI_MEM_BASE + ATH724X_PCI_MEM_SIZE - 1,
302 - .flags = IORESOURCE_MEM,
303 -};
304 -
305 -static struct pci_controller ath724x_pci_controller = {
306 - .pci_ops = &ath724x_pci_ops,
307 - .io_resource = &ath724x_io_resource,
308 - .mem_resource = &ath724x_mem_resource,
309 -};
310 -
311 -int __init ath724x_pcibios_init(void)
312 -{
313 - register_pci_controller(&ath724x_pci_controller);
314 -
315 - return PCIBIOS_SUCCESSFUL;
316 -}