target/linux/ar71xx/patches-3.3/116-MIPS-ath79-add-support-for-the-PCI-host-controller-o.patch

   1 From 9f6d46372cf2a493eaeeffbefe0a796379f838fa Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Tue, 22 Nov 2011 22:54:32 +0100
   4 Subject: [PATCH 16/35] MIPS: ath79: add support for the PCI host controller of the AR71XX SoCs
   5
   6 The Atheros AR71XX SoCs have a built-in PCI Host Controller.
   7 This patch adds a driver for that, and modifies the relevant
   8 files in order to allow to register the PCI controller from
   9 board specific setup.
  10
  11 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  12 Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
  13
  14 v2: - add missing pci-ar71xx.c
  15 ---
  16  arch/mips/ath79/Kconfig                |    1 +
  17  arch/mips/include/asm/mach-ath79/pci.h |    6 +
  18  arch/mips/pci/Makefile                 |    1 +
  19  arch/mips/pci/pci-ar71xx.c             |  375 ++++++++++++++++++++++++++++++++
  20  4 files changed, 383 insertions(+), 0 deletions(-)
  21  create mode 100644 arch/mips/pci/pci-ar71xx.c
  22
  23 --- a/arch/mips/ath79/Kconfig
  24 +++ b/arch/mips/ath79/Kconfig
  25 @@ -52,6 +52,7 @@ endmenu
  26  config SOC_AR71XX
  27         select USB_ARCH_HAS_EHCI
  28         select USB_ARCH_HAS_OHCI
  29 +       select HW_HAS_PCI
  30         def_bool n
  31
  32  config SOC_AR724X
  33 --- a/arch/mips/include/asm/mach-ath79/pci.h
  34 +++ b/arch/mips/include/asm/mach-ath79/pci.h
  35 @@ -11,6 +11,12 @@
  36  #ifndef __ASM_MACH_ATH79_PCI_H
  37  #define __ASM_MACH_ATH79_PCI_H
  38
  39 +#if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR71XX)
  40 +int ar71xx_pcibios_init(void);
  41 +#else
  42 +static inline int ar71xx_pcibios_init(void) { return 0 };
  43 +#endif
  44 +
  45  #if defined(CONFIG_PCI) && defined(CONFIG_SOC_AR724X)
  46  int ar724x_pcibios_init(int irq);
  47  #else
  48 --- a/arch/mips/pci/Makefile
  49 +++ b/arch/mips/pci/Makefile
  50 @@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX)         += pci-bcm47xx.o
  51  obj-$(CONFIG_BCM63XX)          += pci-bcm63xx.o fixup-bcm63xx.o \
  52                                         ops-bcm63xx.o
  53  obj-$(CONFIG_MIPS_ALCHEMY)     += pci-alchemy.o
  54 +obj-$(CONFIG_SOC_AR71XX)       += pci-ar71xx.o
  55  obj-$(CONFIG_SOC_AR724X)       += pci-ar724x.o
  56
  57  #
  58 --- /dev/null
  59 +++ b/arch/mips/pci/pci-ar71xx.c
  60 @@ -0,0 +1,375 @@
  61 +/*
  62 + *  Atheros AR71xx PCI host controller driver
  63 + *
  64 + *  Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
  65 + *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  66 + *
  67 + *  Parts of this file are based on Atheros' 2.6.15 BSP
  68 + *
  69 + *  This program is free software; you can redistribute it and/or modify it
  70 + *  under the terms of the GNU General Public License version 2 as published
  71 + *  by the Free Software Foundation.
  72 + */
  73 +
  74 +#include <linux/resource.h>
  75 +#include <linux/types.h>
  76 +#include <linux/delay.h>
  77 +#include <linux/bitops.h>
  78 +#include <linux/pci.h>
  79 +#include <linux/pci_regs.h>
  80 +#include <linux/interrupt.h>
  81 +
  82 +#include <asm/mach-ath79/ar71xx_regs.h>
  83 +#include <asm/mach-ath79/ath79.h>
  84 +#include <asm/mach-ath79/pci.h>
  85 +
  86 +#define AR71XX_PCI_MEM_BASE    0x10000000
  87 +#define AR71XX_PCI_MEM_SIZE    0x08000000
  88 +
  89 +#define AR71XX_PCI_WIN0_OFFS           0x10000000
  90 +#define AR71XX_PCI_WIN1_OFFS           0x11000000
  91 +#define AR71XX_PCI_WIN2_OFFS           0x12000000
  92 +#define AR71XX_PCI_WIN3_OFFS           0x13000000
  93 +#define AR71XX_PCI_WIN4_OFFS           0x14000000
  94 +#define AR71XX_PCI_WIN5_OFFS           0x15000000
  95 +#define AR71XX_PCI_WIN6_OFFS           0x16000000
  96 +#define AR71XX_PCI_WIN7_OFFS           0x07000000
  97 +
  98 +#define AR71XX_PCI_CFG_BASE            \
  99 +       (AR71XX_PCI_MEM_BASE + AR71XX_PCI_WIN7_OFFS + 0x10000)
 100 +#define AR71XX_PCI_CFG_SIZE            0x100
 101 +
 102 +#define AR71XX_PCI_REG_CRP_AD_CBE      0x00
 103 +#define AR71XX_PCI_REG_CRP_WRDATA      0x04
 104 +#define AR71XX_PCI_REG_CRP_RDDATA      0x08
 105 +#define AR71XX_PCI_REG_CFG_AD          0x0c
 106 +#define AR71XX_PCI_REG_CFG_CBE         0x10
 107 +#define AR71XX_PCI_REG_CFG_WRDATA      0x14
 108 +#define AR71XX_PCI_REG_CFG_RDDATA      0x18
 109 +#define AR71XX_PCI_REG_PCI_ERR         0x1c
 110 +#define AR71XX_PCI_REG_PCI_ERR_ADDR    0x20
 111 +#define AR71XX_PCI_REG_AHB_ERR         0x24
 112 +#define AR71XX_PCI_REG_AHB_ERR_ADDR    0x28
 113 +
 114 +#define AR71XX_PCI_CRP_CMD_WRITE       0x00010000
 115 +#define AR71XX_PCI_CRP_CMD_READ                0x00000000
 116 +#define AR71XX_PCI_CFG_CMD_READ                0x0000000a
 117 +#define AR71XX_PCI_CFG_CMD_WRITE       0x0000000b
 118 +
 119 +#define AR71XX_PCI_INT_CORE            BIT(4)
 120 +#define AR71XX_PCI_INT_DEV2            BIT(2)
 121 +#define AR71XX_PCI_INT_DEV1            BIT(1)
 122 +#define AR71XX_PCI_INT_DEV0            BIT(0)
 123 +
 124 +#define AR71XX_PCI_IRQ_COUNT           5
 125 +
 126 +static DEFINE_SPINLOCK(ar71xx_pci_lock);
 127 +static void __iomem *ar71xx_pcicfg_base;
 128 +
 129 +/* Byte lane enable bits */
 130 +static const u8 ar71xx_pci_ble_table[4][4] = {
 131 +       {0x0, 0xf, 0xf, 0xf},
 132 +       {0xe, 0xd, 0xb, 0x7},
 133 +       {0xc, 0xf, 0x3, 0xf},
 134 +       {0xf, 0xf, 0xf, 0xf},
 135 +};
 136 +
 137 +static const u32 ar71xx_pci_read_mask[8] = {
 138 +       0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0
 139 +};
 140 +
 141 +static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
 142 +{
 143 +       u32 t;
 144 +
 145 +       t = ar71xx_pci_ble_table[size & 3][where & 3];
 146 +       BUG_ON(t == 0xf);
 147 +       t <<= (local) ? 20 : 4;
 148 +
 149 +       return t;
 150 +}
 151 +
 152 +static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
 153 +                                     int where)
 154 +{
 155 +       u32 ret;
 156 +
 157 +       if (!bus->number) {
 158 +               /* type 0 */
 159 +               ret = (1 << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
 160 +                     (where & ~3);
 161 +       } else {
 162 +               /* type 1 */
 163 +               ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) |
 164 +                     (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
 165 +       }
 166 +
 167 +       return ret;
 168 +}
 169 +
 170 +static int ar71xx_pci_check_error(int quiet)
 171 +{
 172 +       void __iomem *base = ar71xx_pcicfg_base;
 173 +       u32 pci_err;
 174 +       u32 ahb_err;
 175 +
 176 +       pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3;
 177 +       if (pci_err) {
 178 +               if (!quiet) {
 179 +                       u32 addr;
 180 +
 181 +                       addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR);
 182 +                       pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
 183 +                               "PCI", pci_err, addr);
 184 +               }
 185 +
 186 +               /* clear PCI error status */
 187 +               __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR);
 188 +       }
 189 +
 190 +       ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1;
 191 +       if (ahb_err) {
 192 +               if (!quiet) {
 193 +                       u32 addr;
 194 +
 195 +                       addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR);
 196 +                       pr_crit("ar71xx: %s bus error %d at addr 0x%x\n",
 197 +                               "AHB", ahb_err, addr);
 198 +               }
 199 +
 200 +               /* clear AHB error status */
 201 +               __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR);
 202 +       }
 203 +
 204 +       return !!(ahb_err | pci_err);
 205 +}
 206 +
 207 +static inline void ar71xx_pci_local_write(int where, int size, u32 value)
 208 +{
 209 +       void __iomem *base = ar71xx_pcicfg_base;
 210 +       u32 ad_cbe;
 211 +
 212 +       value = value << (8 * (where & 3));
 213 +
 214 +       ad_cbe = AR71XX_PCI_CRP_CMD_WRITE | (where & ~3);
 215 +       ad_cbe |= ar71xx_pci_get_ble(where, size, 1);
 216 +
 217 +       __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE);
 218 +       __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA);
 219 +}
 220 +
 221 +static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
 222 +                                        unsigned int devfn,
 223 +                                        int where, int size, u32 cmd)
 224 +{
 225 +       void __iomem *base = ar71xx_pcicfg_base;
 226 +       u32 addr;
 227 +
 228 +       addr = ar71xx_pci_bus_addr(bus, devfn, where);
 229 +
 230 +       __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD);
 231 +       __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
 232 +                    base + AR71XX_PCI_REG_CFG_CBE);
 233 +
 234 +       return ar71xx_pci_check_error(1);
 235 +}
 236 +
 237 +static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 238 +                                 int where, int size, u32 *value)
 239 +{
 240 +       void __iomem *base = ar71xx_pcicfg_base;
 241 +       unsigned long flags;
 242 +       u32 data;
 243 +       int err;
 244 +       int ret;
 245 +
 246 +       ret = PCIBIOS_SUCCESSFUL;
 247 +       data = ~0;
 248 +
 249 +       spin_lock_irqsave(&ar71xx_pci_lock, flags);
 250 +
 251 +       err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
 252 +                                    AR71XX_PCI_CFG_CMD_READ);
 253 +       if (err)
 254 +               ret = PCIBIOS_DEVICE_NOT_FOUND;
 255 +       else
 256 +               data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
 257 +
 258 +       spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
 259 +
 260 +       *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
 261 +
 262 +       return ret;
 263 +}
 264 +
 265 +static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 266 +                                  int where, int size, u32 value)
 267 +{
 268 +       void __iomem *base = ar71xx_pcicfg_base;
 269 +       unsigned long flags;
 270 +       int err;
 271 +       int ret;
 272 +
 273 +       value = value << (8 * (where & 3));
 274 +       ret = PCIBIOS_SUCCESSFUL;
 275 +
 276 +       spin_lock_irqsave(&ar71xx_pci_lock, flags);
 277 +
 278 +       err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
 279 +                                    AR71XX_PCI_CFG_CMD_WRITE);
 280 +       if (err)
 281 +               ret = PCIBIOS_DEVICE_NOT_FOUND;
 282 +       else
 283 +               __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
 284 +
 285 +       spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
 286 +
 287 +       return ret;
 288 +}
 289 +
 290 +static struct pci_ops ar71xx_pci_ops = {
 291 +       .read   = ar71xx_pci_read_config,
 292 +       .write  = ar71xx_pci_write_config,
 293 +};
 294 +
 295 +static struct resource ar71xx_pci_io_resource = {
 296 +       .name           = "PCI IO space",
 297 +       .start          = 0,
 298 +       .end            = 0,
 299 +       .flags          = IORESOURCE_IO,
 300 +};
 301 +
 302 +static struct resource ar71xx_pci_mem_resource = {
 303 +       .name           = "PCI memory space",
 304 +       .start          = AR71XX_PCI_MEM_BASE,
 305 +       .end            = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
 306 +       .flags          = IORESOURCE_MEM
 307 +};
 308 +
 309 +static struct pci_controller ar71xx_pci_controller = {
 310 +       .pci_ops        = &ar71xx_pci_ops,
 311 +       .mem_resource   = &ar71xx_pci_mem_resource,
 312 +       .io_resource    = &ar71xx_pci_io_resource,
 313 +};
 314 +
 315 +static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 316 +{
 317 +       void __iomem *base = ath79_reset_base;
 318 +       u32 pending;
 319 +
 320 +       pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
 321 +                 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 322 +
 323 +       if (pending & AR71XX_PCI_INT_DEV0)
 324 +               generic_handle_irq(ATH79_PCI_IRQ(0));
 325 +
 326 +       else if (pending & AR71XX_PCI_INT_DEV1)
 327 +               generic_handle_irq(ATH79_PCI_IRQ(1));
 328 +
 329 +       else if (pending & AR71XX_PCI_INT_DEV2)
 330 +               generic_handle_irq(ATH79_PCI_IRQ(2));
 331 +
 332 +       else if (pending & AR71XX_PCI_INT_CORE)
 333 +               generic_handle_irq(ATH79_PCI_IRQ(4));
 334 +
 335 +       else
 336 +               spurious_interrupt();
 337 +}
 338 +
 339 +static void ar71xx_pci_irq_unmask(struct irq_data *d)
 340 +{
 341 +       unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
 342 +       void __iomem *base = ath79_reset_base;
 343 +       u32 t;
 344 +
 345 +       t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 346 +       __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 347 +
 348 +       /* flush write */
 349 +       __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 350 +}
 351 +
 352 +static void ar71xx_pci_irq_mask(struct irq_data *d)
 353 +{
 354 +       unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
 355 +       void __iomem *base = ath79_reset_base;
 356 +       u32 t;
 357 +
 358 +       t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 359 +       __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 360 +
 361 +       /* flush write */
 362 +       __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 363 +}
 364 +
 365 +static struct irq_chip ar71xx_pci_irq_chip = {
 366 +       .name           = "AR71XX PCI",
 367 +       .irq_mask       = ar71xx_pci_irq_mask,
 368 +       .irq_unmask     = ar71xx_pci_irq_unmask,
 369 +       .irq_mask_ack   = ar71xx_pci_irq_mask,
 370 +};
 371 +
 372 +static __init void ar71xx_pci_irq_init(void)
 373 +{
 374 +       void __iomem *base = ath79_reset_base;
 375 +       int i;
 376 +
 377 +       __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 378 +       __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
 379 +
 380 +       BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
 381 +
 382 +       for (i = ATH79_PCI_IRQ_BASE;
 383 +            i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++)
 384 +               irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
 385 +                                        handle_level_irq);
 386 +
 387 +       irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
 388 +}
 389 +
 390 +static __init void ar71xx_pci_reset(void)
 391 +{
 392 +       void __iomem *ddr_base = ath79_ddr_base;
 393 +
 394 +       ath79_device_reset_set(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
 395 +       mdelay(100);
 396 +
 397 +       ath79_device_reset_clear(AR71XX_RESET_PCI_BUS | AR71XX_RESET_PCI_CORE);
 398 +       mdelay(100);
 399 +
 400 +       __raw_writel(AR71XX_PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0);
 401 +       __raw_writel(AR71XX_PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1);
 402 +       __raw_writel(AR71XX_PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2);
 403 +       __raw_writel(AR71XX_PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3);
 404 +       __raw_writel(AR71XX_PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4);
 405 +       __raw_writel(AR71XX_PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5);
 406 +       __raw_writel(AR71XX_PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6);
 407 +       __raw_writel(AR71XX_PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7);
 408 +
 409 +       mdelay(100);
 410 +}
 411 +
 412 +__init int ar71xx_pcibios_init(void)
 413 +{
 414 +       u32 t;
 415 +
 416 +       ar71xx_pcicfg_base = ioremap(AR71XX_PCI_CFG_BASE, AR71XX_PCI_CFG_SIZE);
 417 +       if (ar71xx_pcicfg_base == NULL)
 418 +               return -ENOMEM;
 419 +
 420 +       ar71xx_pci_reset();
 421 +
 422 +       /* setup COMMAND register */
 423 +       t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
 424 +         | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
 425 +       ar71xx_pci_local_write(PCI_COMMAND, 4, t);
 426 +
 427 +       /* clear bus errors */
 428 +       ar71xx_pci_check_error(1);
 429 +
 430 +       ar71xx_pci_irq_init();
 431 +
 432 +       register_pci_controller(&ar71xx_pci_controller);
 433 +
 434 +       return 0;
 435 +}