ar71xx: add preliminary support for Mikrotik RB2011L
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / patches-3.3 / 121-MIPS-ath79-add-SoC-detection-code-for-AR934X.patch
1 From bf5cb424312f28e51803286a53cb8613bedc5bc8 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Wed, 14 Mar 2012 10:45:21 +0100
4 Subject: [PATCH 26/47] MIPS: ath79: add SoC detection code for AR934X
5
6 Also add 'soc_is_ar934[124x]' helper functions and a Kconfig
7 symbol for the AR934X SoCs.
8
9 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
10 Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
11 Cc: linux-mips@linux-mips.org
12 Cc: mcgrof@infradead.org
13 Patchwork: https://patchwork.linux-mips.org/patch/3506/
14 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
15 ---
16 arch/mips/ath79/Kconfig | 4 ++++
17 arch/mips/ath79/setup.c | 21 ++++++++++++++++++++-
18 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 2 ++
19 arch/mips/include/asm/mach-ath79/ath79.h | 23 +++++++++++++++++++++++
20 4 files changed, 49 insertions(+), 1 deletions(-)
21
22 --- a/arch/mips/ath79/Kconfig
23 +++ b/arch/mips/ath79/Kconfig
24 @@ -69,6 +69,10 @@ config SOC_AR933X
25 select USB_ARCH_HAS_EHCI
26 def_bool n
27
28 +config SOC_AR934X
29 + select USB_ARCH_HAS_EHCI
30 + def_bool n
31 +
32 config ATH79_DEV_GPIO_BUTTONS
33 def_bool n
34
35 --- a/arch/mips/ath79/setup.c
36 +++ b/arch/mips/ath79/setup.c
37 @@ -1,10 +1,11 @@
38 /*
39 * Atheros AR71XX/AR724X/AR913X specific setup
40 *
41 + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
42 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
43 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
44 *
45 - * Parts of this file are based on Atheros' 2.6.15 BSP
46 + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
47 *
48 * This program is free software; you can redistribute it and/or modify it
49 * under the terms of the GNU General Public License version 2 as published
50 @@ -145,6 +146,24 @@ static void __init ath79_detect_sys_type
51 rev = id & AR933X_REV_ID_REVISION_MASK;
52 break;
53
54 + case REV_ID_MAJOR_AR9341:
55 + ath79_soc = ATH79_SOC_AR9341;
56 + chip = "9341";
57 + rev = id & AR934X_REV_ID_REVISION_MASK;
58 + break;
59 +
60 + case REV_ID_MAJOR_AR9342:
61 + ath79_soc = ATH79_SOC_AR9342;
62 + chip = "9342";
63 + rev = id & AR934X_REV_ID_REVISION_MASK;
64 + break;
65 +
66 + case REV_ID_MAJOR_AR9344:
67 + ath79_soc = ATH79_SOC_AR9344;
68 + chip = "9344";
69 + rev = id & AR934X_REV_ID_REVISION_MASK;
70 + break;
71 +
72 default:
73 panic("ath79: unknown SoC, id:0x%08x", id);
74 }
75 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
76 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
77 @@ -271,6 +271,8 @@
78
79 #define AR724X_REV_ID_REVISION_MASK 0x3
80
81 +#define AR934X_REV_ID_REVISION_MASK 0xf
82 +
83 /*
84 * SPI block
85 */
86 --- a/arch/mips/include/asm/mach-ath79/ath79.h
87 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
88 @@ -29,6 +29,9 @@ enum ath79_soc_type {
89 ATH79_SOC_AR9132,
90 ATH79_SOC_AR9330,
91 ATH79_SOC_AR9331,
92 + ATH79_SOC_AR9341,
93 + ATH79_SOC_AR9342,
94 + ATH79_SOC_AR9344,
95 };
96
97 extern enum ath79_soc_type ath79_soc;
98 @@ -75,6 +78,26 @@ static inline int soc_is_ar933x(void)
99 ath79_soc == ATH79_SOC_AR9331);
100 }
101
102 +static inline int soc_is_ar9341(void)
103 +{
104 + return (ath79_soc == ATH79_SOC_AR9341);
105 +}
106 +
107 +static inline int soc_is_ar9342(void)
108 +{
109 + return (ath79_soc == ATH79_SOC_AR9342);
110 +}
111 +
112 +static inline int soc_is_ar9344(void)
113 +{
114 + return (ath79_soc == ATH79_SOC_AR9344);
115 +}
116 +
117 +static inline int soc_is_ar934x(void)
118 +{
119 + return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
120 +}
121 +
122 extern void __iomem *ath79_ddr_base;
123 extern void __iomem *ath79_pll_base;
124 extern void __iomem *ath79_reset_base;