ar71xx: add preliminary support for Mikrotik RB2011L
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / patches-3.3 / 124-MIPS-ath79-rework-IP2-IP3-interrupt-handling.patch
1 From f44c70eb5368c0742a8f401ccf39f2ba7252f5a7 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Wed, 14 Mar 2012 10:45:24 +0100
4 Subject: [PATCH 29/47] MIPS: ath79: rework IP2/IP3 interrupt handling
5
6 The current implementation assumes that flushing the
7 DDR writeback buffer is required for IP2/IP3 interrupts,
8 however this is not true for all SoCs.
9
10 Use SoC specific IP2/IP3 handlers instead of flushing
11 the buffers in the dispatcher code.
12
13 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
14 Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
15 Cc: linux-mips@linux-mips.org
16 Cc: mcgrof@infradead.org
17 Patchwork: https://patchwork.linux-mips.org/patch/3509/
18 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
19 ---
20 arch/mips/ath79/irq.c | 92 ++++++++++++++++++++++++++++++++++++++-----------
21 1 files changed, 72 insertions(+), 20 deletions(-)
22
23 --- a/arch/mips/ath79/irq.c
24 +++ b/arch/mips/ath79/irq.c
25 @@ -1,7 +1,7 @@
26 /*
27 * Atheros AR71xx/AR724x/AR913x specific interrupt handling
28 *
29 - * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
30 + * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
31 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
32 *
33 * Parts of this file are based on Atheros' 2.6.15 BSP
34 @@ -23,8 +23,8 @@
35 #include <asm/mach-ath79/ar71xx_regs.h>
36 #include "common.h"
37
38 -static unsigned int ath79_ip2_flush_reg;
39 -static unsigned int ath79_ip3_flush_reg;
40 +static void (*ath79_ip2_handler)(void);
41 +static void (*ath79_ip3_handler)(void);
42
43 static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
44 {
45 @@ -152,10 +152,8 @@ asmlinkage void plat_irq_dispatch(void)
46 if (pending & STATUSF_IP7)
47 do_IRQ(ATH79_CPU_IRQ_TIMER);
48
49 - else if (pending & STATUSF_IP2) {
50 - ath79_ddr_wb_flush(ath79_ip2_flush_reg);
51 - do_IRQ(ATH79_CPU_IRQ_IP2);
52 - }
53 + else if (pending & STATUSF_IP2)
54 + ath79_ip2_handler();
55
56 else if (pending & STATUSF_IP4)
57 do_IRQ(ATH79_CPU_IRQ_GE0);
58 @@ -163,10 +161,8 @@ asmlinkage void plat_irq_dispatch(void)
59 else if (pending & STATUSF_IP5)
60 do_IRQ(ATH79_CPU_IRQ_GE1);
61
62 - else if (pending & STATUSF_IP3) {
63 - ath79_ddr_wb_flush(ath79_ip3_flush_reg);
64 - do_IRQ(ATH79_CPU_IRQ_USB);
65 - }
66 + else if (pending & STATUSF_IP3)
67 + ath79_ip3_handler();
68
69 else if (pending & STATUSF_IP6)
70 do_IRQ(ATH79_CPU_IRQ_MISC);
71 @@ -175,22 +171,78 @@ asmlinkage void plat_irq_dispatch(void)
72 spurious_interrupt();
73 }
74
75 +/*
76 + * The IP2/IP3 lines are tied to a PCI/WMAC/USB device. Drivers for
77 + * these devices typically allocate coherent DMA memory, however the
78 + * DMA controller may still have some unsynchronized data in the FIFO.
79 + * Issue a flush in the handlers to ensure that the driver sees
80 + * the update.
81 + */
82 +static void ar71xx_ip2_handler(void)
83 +{
84 + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
85 + do_IRQ(ATH79_CPU_IRQ_IP2);
86 +}
87 +
88 +static void ar724x_ip2_handler(void)
89 +{
90 + ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE);
91 + do_IRQ(ATH79_CPU_IRQ_IP2);
92 +}
93 +
94 +static void ar913x_ip2_handler(void)
95 +{
96 + ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC);
97 + do_IRQ(ATH79_CPU_IRQ_IP2);
98 +}
99 +
100 +static void ar933x_ip2_handler(void)
101 +{
102 + ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC);
103 + do_IRQ(ATH79_CPU_IRQ_IP2);
104 +}
105 +
106 +static void ar71xx_ip3_handler(void)
107 +{
108 + ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
109 + do_IRQ(ATH79_CPU_IRQ_USB);
110 +}
111 +
112 +static void ar724x_ip3_handler(void)
113 +{
114 + ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB);
115 + do_IRQ(ATH79_CPU_IRQ_USB);
116 +}
117 +
118 +static void ar913x_ip3_handler(void)
119 +{
120 + ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB);
121 + do_IRQ(ATH79_CPU_IRQ_USB);
122 +}
123 +
124 +static void ar933x_ip3_handler(void)
125 +{
126 + ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB);
127 + do_IRQ(ATH79_CPU_IRQ_USB);
128 +}
129 +
130 void __init arch_init_irq(void)
131 {
132 if (soc_is_ar71xx()) {
133 - ath79_ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
134 - ath79_ip3_flush_reg = AR71XX_DDR_REG_FLUSH_USB;
135 + ath79_ip2_handler = ar71xx_ip2_handler;
136 + ath79_ip3_handler = ar71xx_ip3_handler;
137 } else if (soc_is_ar724x()) {
138 - ath79_ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
139 - ath79_ip3_flush_reg = AR724X_DDR_REG_FLUSH_USB;
140 + ath79_ip2_handler = ar724x_ip2_handler;
141 + ath79_ip3_handler = ar724x_ip3_handler;
142 } else if (soc_is_ar913x()) {
143 - ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC;
144 - ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB;
145 + ath79_ip2_handler = ar913x_ip2_handler;
146 + ath79_ip3_handler = ar913x_ip3_handler;
147 } else if (soc_is_ar933x()) {
148 - ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
149 - ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB;
150 - } else
151 + ath79_ip2_handler = ar933x_ip2_handler;
152 + ath79_ip3_handler = ar933x_ip3_handler;
153 + } else {
154 BUG();
155 + }
156
157 cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
158 mips_cpu_irq_init();