ar71xx: add preliminary support for Mikrotik RB2011L
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / patches-3.3 / 125-MIPS-ath79-add-IRQ-handling-code-for-AR934X.patch
1 From b16fdecf14d24fe213c81409c0c2dca66d5b7bc9 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Wed, 14 Mar 2012 10:45:25 +0100
4 Subject: [PATCH 30/47] MIPS: ath79: add IRQ handling code for AR934X
5
6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
7 Acked-by: Luis R. Rodriguez <mcgrof@qca.qualcomm.com>
8 Cc: linux-mips@linux-mips.org
9 Cc: mcgrof@infradead.org
10 Patchwork: https://patchwork.linux-mips.org/patch/3510/
11 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
12 ---
13 arch/mips/ath79/irq.c | 55 +++++++++++++++++++++++-
14 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 25 +++++++++++
15 arch/mips/include/asm/mach-ath79/irq.h | 6 ++-
16 3 files changed, 83 insertions(+), 3 deletions(-)
17
18 --- a/arch/mips/ath79/irq.c
19 +++ b/arch/mips/ath79/irq.c
20 @@ -1,10 +1,11 @@
21 /*
22 * Atheros AR71xx/AR724x/AR913x specific interrupt handling
23 *
24 + * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
25 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
26 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
27 *
28 - * Parts of this file are based on Atheros' 2.6.15 BSP
29 + * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
30 *
31 * This program is free software; you can redistribute it and/or modify it
32 * under the terms of the GNU General Public License version 2 as published
33 @@ -129,7 +130,7 @@ static void __init ath79_misc_irq_init(v
34
35 if (soc_is_ar71xx() || soc_is_ar913x())
36 ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask;
37 - else if (soc_is_ar724x() || soc_is_ar933x())
38 + else if (soc_is_ar724x() || soc_is_ar933x() || soc_is_ar934x())
39 ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
40 else
41 BUG();
42 @@ -143,6 +144,39 @@ static void __init ath79_misc_irq_init(v
43 irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
44 }
45
46 +static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
47 +{
48 + u32 status;
49 +
50 + disable_irq_nosync(irq);
51 +
52 + status = ath79_reset_rr(AR934X_RESET_REG_PCIE_WMAC_INT_STATUS);
53 +
54 + if (status & AR934X_PCIE_WMAC_INT_PCIE_ALL) {
55 + ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_PCIE);
56 + generic_handle_irq(ATH79_IP2_IRQ(0));
57 + } else if (status & AR934X_PCIE_WMAC_INT_WMAC_ALL) {
58 + ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_WMAC);
59 + generic_handle_irq(ATH79_IP2_IRQ(1));
60 + } else {
61 + spurious_interrupt();
62 + }
63 +
64 + enable_irq(irq);
65 +}
66 +
67 +static void ar934x_ip2_irq_init(void)
68 +{
69 + int i;
70 +
71 + for (i = ATH79_IP2_IRQ_BASE;
72 + i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
73 + irq_set_chip_and_handler(i, &dummy_irq_chip,
74 + handle_level_irq);
75 +
76 + irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
77 +}
78 +
79 asmlinkage void plat_irq_dispatch(void)
80 {
81 unsigned long pending;
82 @@ -202,6 +236,11 @@ static void ar933x_ip2_handler(void)
83 do_IRQ(ATH79_CPU_IRQ_IP2);
84 }
85
86 +static void ar934x_ip2_handler(void)
87 +{
88 + do_IRQ(ATH79_CPU_IRQ_IP2);
89 +}
90 +
91 static void ar71xx_ip3_handler(void)
92 {
93 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
94 @@ -226,6 +265,12 @@ static void ar933x_ip3_handler(void)
95 do_IRQ(ATH79_CPU_IRQ_USB);
96 }
97
98 +static void ar934x_ip3_handler(void)
99 +{
100 + ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
101 + do_IRQ(ATH79_CPU_IRQ_USB);
102 +}
103 +
104 void __init arch_init_irq(void)
105 {
106 if (soc_is_ar71xx()) {
107 @@ -240,6 +285,9 @@ void __init arch_init_irq(void)
108 } else if (soc_is_ar933x()) {
109 ath79_ip2_handler = ar933x_ip2_handler;
110 ath79_ip3_handler = ar933x_ip3_handler;
111 + } else if (soc_is_ar934x()) {
112 + ath79_ip2_handler = ar934x_ip2_handler;
113 + ath79_ip3_handler = ar934x_ip3_handler;
114 } else {
115 BUG();
116 }
117 @@ -247,4 +295,7 @@ void __init arch_init_irq(void)
118 cp0_perfcount_irq = ATH79_MISC_IRQ_PERFC;
119 mips_cpu_irq_init();
120 ath79_misc_irq_init();
121 +
122 + if (soc_is_ar934x())
123 + ar934x_ip2_irq_init();
124 }
125 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
126 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
127 @@ -92,6 +92,12 @@
128 #define AR933X_DDR_REG_FLUSH_USB 0x84
129 #define AR933X_DDR_REG_FLUSH_WMAC 0x88
130
131 +#define AR934X_DDR_REG_FLUSH_GE0 0x9c
132 +#define AR934X_DDR_REG_FLUSH_GE1 0xa0
133 +#define AR934X_DDR_REG_FLUSH_USB 0xa4
134 +#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
135 +#define AR934X_DDR_REG_FLUSH_WMAC 0xac
136 +
137 /*
138 * PLL block
139 */
140 @@ -222,6 +228,7 @@
141 #define AR933X_RESET_REG_BOOTSTRAP 0xac
142
143 #define AR934X_RESET_REG_BOOTSTRAP 0xb0
144 +#define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
145
146 #define MISC_INT_ETHSW BIT(12)
147 #define MISC_INT_TIMER4 BIT(10)
148 @@ -295,6 +302,24 @@
149 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
150 #define AR934X_BOOTSTRAP_DDR1 BIT(0)
151
152 +#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
153 +#define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
154 +#define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
155 +#define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
156 +#define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
157 +#define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
158 +#define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
159 +#define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
160 +#define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
161 +#define AR934X_PCIE_WMAC_INT_WMAC_ALL \
162 + (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
163 + AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
164 +
165 +#define AR934X_PCIE_WMAC_INT_PCIE_ALL \
166 + (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
167 + AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
168 + AR934X_PCIE_WMAC_INT_PCIE_RC3)
169 +
170 #define REV_ID_MAJOR_MASK 0xfff0
171 #define REV_ID_MAJOR_AR71XX 0x00a0
172 #define REV_ID_MAJOR_AR913X 0x00b0
173 --- a/arch/mips/include/asm/mach-ath79/irq.h
174 +++ b/arch/mips/include/asm/mach-ath79/irq.h
175 @@ -10,7 +10,7 @@
176 #define __ASM_MACH_ATH79_IRQ_H
177
178 #define MIPS_CPU_IRQ_BASE 0
179 -#define NR_IRQS 46
180 +#define NR_IRQS 48
181
182 #define ATH79_MISC_IRQ_BASE 8
183 #define ATH79_MISC_IRQ_COUNT 32
184 @@ -19,6 +19,10 @@
185 #define ATH79_PCI_IRQ_COUNT 6
186 #define ATH79_PCI_IRQ(_x) (ATH79_PCI_IRQ_BASE + (_x))
187
188 +#define ATH79_IP2_IRQ_BASE (ATH79_PCI_IRQ_BASE + ATH79_PCI_IRQ_COUNT)
189 +#define ATH79_IP2_IRQ_COUNT 2
190 +#define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
191 +
192 #define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
193 #define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
194 #define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)