ar71xx: fix AR934X_EHCI_SIZE
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / patches-3.3 / 134-MIPS-ath79-add-USB-platform-setup-code-for-AR934X.patch
1 From 635d5a2ac8aa483c3a0635c60bff8ea8978ff6a7 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Sun, 11 Dec 2011 18:34:13 +0100
4 Subject: [PATCH 39/47] MIPS: ath79: add USB platform setup code for AR934X
5
6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
7 ---
8 arch/mips/ath79/dev-usb.c | 28 ++++++++++++++++++++++++
9 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 7 ++++++
10 2 files changed, 35 insertions(+), 0 deletions(-)
11
12 --- a/arch/mips/ath79/dev-usb.c
13 +++ b/arch/mips/ath79/dev-usb.c
14 @@ -193,6 +193,32 @@ static void __init ar933x_usb_setup(void
15 platform_device_register(&ath79_ehci_device);
16 }
17
18 +static void __init ar934x_usb_setup(void)
19 +{
20 + u32 bootstrap;
21 +
22 + bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
23 + if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
24 + return;
25 +
26 + ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
27 + udelay(1000);
28 +
29 + ath79_device_reset_clear(AR934X_RESET_USB_PHY);
30 + udelay(1000);
31 +
32 + ath79_device_reset_clear(AR934X_RESET_USB_PHY_ANALOG);
33 + udelay(1000);
34 +
35 + ath79_device_reset_clear(AR934X_RESET_USB_HOST);
36 + udelay(1000);
37 +
38 + ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE,
39 + AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
40 + ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
41 + platform_device_register(&ath79_ehci_device);
42 +}
43 +
44 void __init ath79_register_usb(void)
45 {
46 if (soc_is_ar71xx())
47 @@ -205,6 +231,8 @@ void __init ath79_register_usb(void)
48 ar913x_usb_setup();
49 else if (soc_is_ar933x())
50 ar933x_usb_setup();
51 + else if (soc_is_ar934x())
52 + ar934x_usb_setup();
53 else
54 BUG();
55 }
56 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
57 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
58 @@ -63,6 +63,8 @@
59
60 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
61 #define AR934X_WMAC_SIZE 0x20000
62 +#define AR934X_EHCI_BASE 0x1b000000
63 +#define AR934X_EHCI_SIZE 0x200
64
65 /*
66 * DDR_CTRL block
67 @@ -288,6 +290,11 @@
68 #define AR933X_RESET_USB_PHY BIT(4)
69 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
70
71 +#define AR934X_RESET_USB_PHY_ANALOG BIT(11)
72 +#define AR934X_RESET_USB_HOST BIT(5)
73 +#define AR934X_RESET_USB_PHY BIT(4)
74 +#define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
75 +
76 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
77
78 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)