target/linux/ar71xx/patches-3.3/153-MIPS-pci-ar71xx-use-dynamically-allocated-PCI-contro.patch

   1 From 6c3ef689e4364dca74eaaecd72384be09e5a6bc8 Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Mon, 25 Jun 2012 09:19:08 +0200
   4 Subject: [PATCH 14/34] MIPS: pci-ar71xx: use dynamically allocated PCI controller structure
   5
   6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
   7 ---
   8  arch/mips/pci/pci-ar71xx.c |   84 +++++++++++++++++++++++++++----------------
   9  1 files changed, 53 insertions(+), 31 deletions(-)
  10
  11 --- a/arch/mips/pci/pci-ar71xx.c
  12 +++ b/arch/mips/pci/pci-ar71xx.c
  13 @@ -20,6 +20,7 @@
  14  #include <linux/interrupt.h>
  15  #include <linux/module.h>
  16  #include <linux/platform_device.h>
  17 +#include <linux/slab.h>
  18
  19  #include <asm/mach-ath79/ar71xx_regs.h>
  20  #include <asm/mach-ath79/ath79.h>
  21 @@ -48,8 +49,12 @@
  22
  23  #define AR71XX_PCI_IRQ_COUNT           5
  24
  25 -static DEFINE_SPINLOCK(ar71xx_pci_lock);
  26 -static void __iomem *ar71xx_pcicfg_base;
  27 +struct ar71xx_pci_controller {
  28 +       void __iomem *cfg_base;
  29 +       spinlock_t lock;
  30 +       int irq;
  31 +       struct pci_controller pci_ctrl;
  32 +};
  33
  34  /* Byte lane enable bits */
  35  static const u8 ar71xx_pci_ble_table[4][4] = {
  36 @@ -92,9 +97,18 @@ static inline u32 ar71xx_pci_bus_addr(st
  37         return ret;
  38  }
  39
  40 -static int ar71xx_pci_check_error(int quiet)
  41 +static inline struct ar71xx_pci_controller *
  42 +pci_bus_to_ar71xx_controller(struct pci_bus *bus)
  43  {
  44 -       void __iomem *base = ar71xx_pcicfg_base;
  45 +       struct pci_controller *hose;
  46 +
  47 +       hose = (struct pci_controller *) bus->sysdata;
  48 +       return container_of(hose, struct ar71xx_pci_controller, pci_ctrl);
  49 +}
  50 +
  51 +static int ar71xx_pci_check_error(struct ar71xx_pci_controller *apc, int quiet)
  52 +{
  53 +       void __iomem *base = apc->cfg_base;
  54         u32 pci_err;
  55         u32 ahb_err;
  56
  57 @@ -129,9 +143,10 @@ static int ar71xx_pci_check_error(int qu
  58         return !!(ahb_err | pci_err);
  59  }
  60
  61 -static inline void ar71xx_pci_local_write(int where, int size, u32 value)
  62 +static inline void ar71xx_pci_local_write(struct ar71xx_pci_controller *apc,
  63 +                                         int where, int size, u32 value)
  64  {
  65 -       void __iomem *base = ar71xx_pcicfg_base;
  66 +       void __iomem *base = apc->cfg_base;
  67         u32 ad_cbe;
  68
  69         value = value << (8 * (where & 3));
  70 @@ -147,7 +162,8 @@ static inline int ar71xx_pci_set_cfgaddr
  71                                          unsigned int devfn,
  72                                          int where, int size, u32 cmd)
  73  {
  74 -       void __iomem *base = ar71xx_pcicfg_base;
  75 +       struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
  76 +       void __iomem *base = apc->cfg_base;
  77         u32 addr;
  78
  79         addr = ar71xx_pci_bus_addr(bus, devfn, where);
  80 @@ -156,13 +172,14 @@ static inline int ar71xx_pci_set_cfgaddr
  81         __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
  82                      base + AR71XX_PCI_REG_CFG_CBE);
  83
  84 -       return ar71xx_pci_check_error(1);
  85 +       return ar71xx_pci_check_error(apc, 1);
  86  }
  87
  88  static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  89                                   int where, int size, u32 *value)
  90  {
  91 -       void __iomem *base = ar71xx_pcicfg_base;
  92 +       struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
  93 +       void __iomem *base = apc->cfg_base;
  94         unsigned long flags;
  95         u32 data;
  96         int err;
  97 @@ -171,7 +188,7 @@ static int ar71xx_pci_read_config(struct
  98         ret = PCIBIOS_SUCCESSFUL;
  99         data = ~0;
 100
 101 -       spin_lock_irqsave(&ar71xx_pci_lock, flags);
 102 +       spin_lock_irqsave(&apc->lock, flags);
 103
 104         err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
 105                                      AR71XX_PCI_CFG_CMD_READ);
 106 @@ -180,7 +197,7 @@ static int ar71xx_pci_read_config(struct
 107         else
 108                 data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA);
 109
 110 -       spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
 111 +       spin_unlock_irqrestore(&apc->lock, flags);
 112
 113         *value = (data >> (8 * (where & 3))) & ar71xx_pci_read_mask[size & 7];
 114
 115 @@ -190,7 +207,8 @@ static int ar71xx_pci_read_config(struct
 116  static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 117                                    int where, int size, u32 value)
 118  {
 119 -       void __iomem *base = ar71xx_pcicfg_base;
 120 +       struct ar71xx_pci_controller *apc = pci_bus_to_ar71xx_controller(bus);
 121 +       void __iomem *base = apc->cfg_base;
 122         unsigned long flags;
 123         int err;
 124         int ret;
 125 @@ -198,7 +216,7 @@ static int ar71xx_pci_write_config(struc
 126         value = value << (8 * (where & 3));
 127         ret = PCIBIOS_SUCCESSFUL;
 128
 129 -       spin_lock_irqsave(&ar71xx_pci_lock, flags);
 130 +       spin_lock_irqsave(&apc->lock, flags);
 131
 132         err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
 133                                      AR71XX_PCI_CFG_CMD_WRITE);
 134 @@ -207,7 +225,7 @@ static int ar71xx_pci_write_config(struc
 135         else
 136                 __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);
 137
 138 -       spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
 139 +       spin_unlock_irqrestore(&apc->lock, flags);
 140
 141         return ret;
 142  }
 143 @@ -231,12 +249,6 @@ static struct resource ar71xx_pci_mem_re
 144         .flags          = IORESOURCE_MEM
 145  };
 146
 147 -static struct pci_controller ar71xx_pci_controller = {
 148 -       .pci_ops        = &ar71xx_pci_ops,
 149 -       .mem_resource   = &ar71xx_pci_mem_resource,
 150 -       .io_resource    = &ar71xx_pci_io_resource,
 151 -};
 152 -
 153  static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 154  {
 155         void __iomem *base = ath79_reset_base;
 156 @@ -294,7 +306,7 @@ static struct irq_chip ar71xx_pci_irq_ch
 157         .irq_mask_ack   = ar71xx_pci_irq_mask,
 158  };
 159
 160 -static __devinit void ar71xx_pci_irq_init(int irq)
 161 +static __devinit void ar71xx_pci_irq_init(struct ar71xx_pci_controller *apc)
 162  {
 163         void __iomem *base = ath79_reset_base;
 164         int i;
 165 @@ -309,7 +321,7 @@ static __devinit void ar71xx_pci_irq_ini
 166                 irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
 167                                          handle_level_irq);
 168
 169 -       irq_set_chained_handler(irq, ar71xx_pci_irq_handler);
 170 +       irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler);
 171  }
 172
 173  static __devinit void ar71xx_pci_reset(void)
 174 @@ -336,20 +348,26 @@ static __devinit void ar71xx_pci_reset(v
 175
 176  static int __devinit ar71xx_pci_probe(struct platform_device *pdev)
 177  {
 178 +       struct ar71xx_pci_controller *apc;
 179         struct resource *res;
 180 -       int irq;
 181         u32 t;
 182
 183 +       apc = kzalloc(sizeof(struct ar71xx_pci_controller), GFP_KERNEL);
 184 +       if (!apc)
 185 +               return -ENOMEM;
 186 +
 187 +       spin_lock_init(&apc->lock);
 188 +
 189         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg_base");
 190         if (!res)
 191                 return -EINVAL;
 192
 193 -       ar71xx_pcicfg_base = devm_request_and_ioremap(&pdev->dev, res);
 194 -       if (!ar71xx_pcicfg_base)
 195 +       apc->cfg_base = devm_request_and_ioremap(&pdev->dev, res);
 196 +       if (!apc->cfg_base)
 197                 return -ENOMEM;
 198
 199 -       irq = platform_get_irq(pdev, 0);
 200 -       if (irq < 0)
 201 +       apc->irq = platform_get_irq(pdev, 0);
 202 +       if (apc->irq < 0)
 203                 return -EINVAL;
 204
 205         ar71xx_pci_reset();
 206 @@ -357,14 +375,18 @@ static int __devinit ar71xx_pci_probe(st
 207         /* setup COMMAND register */
 208         t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
 209           | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
 210 -       ar71xx_pci_local_write(PCI_COMMAND, 4, t);
 211 +       ar71xx_pci_local_write(apc, PCI_COMMAND, 4, t);
 212
 213         /* clear bus errors */
 214 -       ar71xx_pci_check_error(1);
 215 +       ar71xx_pci_check_error(apc, 1);
 216 +
 217 +       ar71xx_pci_irq_init(apc);
 218
 219 -       ar71xx_pci_irq_init(irq);
 220 +       apc->pci_ctrl.pci_ops = &ar71xx_pci_ops;
 221 +       apc->pci_ctrl.mem_resource = &ar71xx_pci_mem_resource;
 222 +       apc->pci_ctrl.io_resource = &ar71xx_pci_io_resource;
 223
 224 -       register_pci_controller(&ar71xx_pci_controller);
 225 +       register_pci_controller(&apc->pci_ctrl);
 226
 227         return 0;
 228  }