ar71xx: add initial support for the QCA955X SoCs
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / patches-3.3 / 170-MIPS-ath79-add-PCI-controller-registration-code-for-.patch
1 From 8bb54348722216a1dd6905d9d031ebdaa3a544a4 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Sun, 24 Jun 2012 23:05:20 +0200
4 Subject: [PATCH 26/34] MIPS: ath79: add PCI controller registration code for the QCA9558 SoC
5
6 ---
7 arch/mips/ath79/Kconfig | 2 +
8 arch/mips/ath79/pci.c | 36 ++++++++++++++++++++++++
9 arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 13 ++++++++
10 3 files changed, 51 insertions(+), 0 deletions(-)
11
12 --- a/arch/mips/ath79/Kconfig
13 +++ b/arch/mips/ath79/Kconfig
14 @@ -90,6 +90,8 @@ config SOC_AR934X
15
16 config SOC_QCA955X
17 select USB_ARCH_HAS_EHCI
18 + select HW_HAS_PCI
19 + select PCI_AR724X if PCI
20 def_bool n
21
22 config PCI_AR724X
23 --- a/arch/mips/ath79/pci.c
24 +++ b/arch/mips/ath79/pci.c
25 @@ -49,6 +49,21 @@ static const struct ath79_pci_irq ar724x
26 }
27 };
28
29 +static const struct ath79_pci_irq qca955x_pci_irq_map[] __initconst = {
30 + {
31 + .bus = 0,
32 + .slot = 0,
33 + .pin = 1,
34 + .irq = ATH79_PCI_IRQ(0),
35 + },
36 + {
37 + .bus = 1,
38 + .slot = 0,
39 + .pin = 1,
40 + .irq = ATH79_PCI_IRQ(1),
41 + },
42 +};
43 +
44 int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin)
45 {
46 int irq = -1;
47 @@ -64,6 +79,9 @@ int __init pcibios_map_irq(const struct
48 soc_is_ar9344()) {
49 ath79_pci_irq_map = ar724x_pci_irq_map;
50 ath79_pci_nr_irqs = ARRAY_SIZE(ar724x_pci_irq_map);
51 + } else if (soc_is_qca955x()) {
52 + ath79_pci_irq_map = qca955x_pci_irq_map;
53 + ath79_pci_nr_irqs = ARRAY_SIZE(qca955x_pci_irq_map);
54 } else {
55 pr_crit("pci %s: invalid irq map\n",
56 pci_name((struct pci_dev *) dev));
57 @@ -215,6 +233,24 @@ int __init ath79_register_pci(void)
58 AR724X_PCI_MEM_SIZE,
59 0,
60 ATH79_IP2_IRQ(0));
61 + } else if (soc_is_qca9558()) {
62 + pdev = ath79_register_pci_ar724x(0,
63 + QCA955X_PCI_CFG_BASE0,
64 + QCA955X_PCI_CTRL_BASE0,
65 + QCA955X_PCI_CRP_BASE0,
66 + QCA955X_PCI_MEM_BASE0,
67 + QCA955X_PCI_MEM_SIZE,
68 + 0,
69 + ATH79_IP2_IRQ(0));
70 +
71 + pdev = ath79_register_pci_ar724x(1,
72 + QCA955X_PCI_CFG_BASE1,
73 + QCA955X_PCI_CTRL_BASE1,
74 + QCA955X_PCI_CRP_BASE1,
75 + QCA955X_PCI_MEM_BASE1,
76 + QCA955X_PCI_MEM_SIZE,
77 + 1,
78 + ATH79_IP3_IRQ(2));
79 } else {
80 /* No PCI support */
81 return -ENODEV;
82 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
83 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
84 @@ -92,6 +92,19 @@
85 #define AR934X_EHCI_BASE 0x1b000000
86 #define AR934X_EHCI_SIZE 0x1000
87
88 +#define QCA955X_PCI_MEM_BASE0 0x10000000
89 +#define QCA955X_PCI_MEM_BASE1 0x12000000
90 +#define QCA955X_PCI_MEM_SIZE 0x02000000
91 +#define QCA955X_PCI_CFG_BASE0 0x14000000
92 +#define QCA955X_PCI_CFG_BASE1 0x16000000
93 +#define QCA955X_PCI_CFG_SIZE 0x1000
94 +#define QCA955X_PCI_CRP_BASE0 (AR71XX_APB_BASE + 0x000c0000)
95 +#define QCA955X_PCI_CRP_BASE1 (AR71XX_APB_BASE + 0x00250000)
96 +#define QCA955X_PCI_CRP_SIZE 0x1000
97 +#define QCA955X_PCI_CTRL_BASE0 (AR71XX_APB_BASE + 0x000f0000)
98 +#define QCA955X_PCI_CTRL_BASE1 (AR71XX_APB_BASE + 0x00280000)
99 +#define QCA955X_PCI_CTRL_SIZE 0x100
100 +
101 #define QCA955X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
102 #define QCA955X_WMAC_SIZE 0x20000
103 #define QCA955X_EHCI0_BASE 0x1b000000