target/linux/ar71xx/patches-3.3/601-MIPS-ath79-add-more-register-defines.patch

   1 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   2 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   3 @@ -21,6 +21,10 @@
   4  #include <linux/bitops.h>
   5
   6  #define AR71XX_APB_BASE                0x18000000
   7 +#define AR71XX_GE0_BASE                0x19000000
   8 +#define AR71XX_GE0_SIZE                0x10000
   9 +#define AR71XX_GE1_BASE                0x1a000000
  10 +#define AR71XX_GE1_SIZE                0x10000
  11  #define AR71XX_EHCI_BASE       0x1b000000
  12  #define AR71XX_EHCI_SIZE       0x1000
  13  #define AR71XX_OHCI_BASE       0x1c000000
  14 @@ -40,6 +44,8 @@
  15  #define AR71XX_PLL_SIZE                0x100
  16  #define AR71XX_RESET_BASE      (AR71XX_APB_BASE + 0x00060000)
  17  #define AR71XX_RESET_SIZE      0x100
  18 +#define AR71XX_MII_BASE                (AR71XX_APB_BASE + 0x00070000)
  19 +#define AR71XX_MII_SIZE                0x100
  20
  21  #define AR71XX_PCI_MEM_BASE    0x10000000
  22  #define AR71XX_PCI_MEM_SIZE    0x07000000
  23 @@ -82,17 +88,23 @@
  24
  25  #define AR933X_UART_BASE       (AR71XX_APB_BASE + 0x00020000)
  26  #define AR933X_UART_SIZE       0x14
  27 +#define AR933X_GMAC_BASE       (AR71XX_APB_BASE + 0x00070000)
  28 +#define AR933X_GMAC_SIZE       0x04
  29  #define AR933X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
  30  #define AR933X_WMAC_SIZE       0x20000
  31  #define AR933X_EHCI_BASE       0x1b000000
  32  #define AR933X_EHCI_SIZE       0x1000
  33
  34 +#define AR934X_GMAC_BASE       (AR71XX_APB_BASE + 0x00070000)
  35 +#define AR934X_GMAC_SIZE       0x14
  36  #define AR934X_WMAC_BASE       (AR71XX_APB_BASE + 0x00100000)
  37  #define AR934X_WMAC_SIZE       0x20000
  38  #define AR934X_EHCI_BASE       0x1b000000
  39  #define AR934X_EHCI_SIZE       0x200
  40  #define AR934X_SRIF_BASE       (AR71XX_APB_BASE + 0x00116000)
  41  #define AR934X_SRIF_SIZE       0x1000
  42 +#define AR934X_NFC_BASE                0x1b000200
  43 +#define AR934X_NFC_SIZE                0xb8
  44
  45  #define QCA955X_PCI_MEM_BASE0  0x10000000
  46  #define QCA955X_PCI_MEM_BASE1  0x12000000
  47 @@ -112,6 +124,10 @@
  48  #define QCA955X_EHCI0_BASE     0x1b000000
  49  #define QCA955X_EHCI1_BASE     0x1b400000
  50  #define QCA955X_EHCI_SIZE      0x200
  51 +#define QCA955X_GMAC_BASE      (AR71XX_APB_BASE + 0x00070000)
  52 +#define QCA955X_GMAC_SIZE      0x40
  53 +#define QCA955X_NFC_BASE       0x1b000200
  54 +#define QCA955X_NFC_SIZE       0xb8
  55
  56  /*
  57   * DDR_CTRL block
  58 @@ -167,6 +183,9 @@
  59  #define AR71XX_AHB_DIV_SHIFT           20
  60  #define AR71XX_AHB_DIV_MASK            0x7
  61
  62 +#define AR71XX_ETH0_PLL_SHIFT          17
  63 +#define AR71XX_ETH1_PLL_SHIFT          19
  64 +
  65  #define AR724X_PLL_REG_CPU_CONFIG      0x00
  66  #define AR724X_PLL_REG_PCIE_CONFIG     0x18
  67
  68 @@ -179,6 +198,8 @@
  69  #define AR724X_DDR_DIV_SHIFT           22
  70  #define AR724X_DDR_DIV_MASK            0x3
  71
  72 +#define AR7242_PLL_REG_ETH0_INT_CLOCK  0x2c
  73 +
  74  #define AR913X_PLL_REG_CPU_CONFIG      0x00
  75  #define AR913X_PLL_REG_ETH_CONFIG      0x04
  76  #define AR913X_PLL_REG_ETH0_INT_CLOCK  0x14
  77 @@ -191,6 +212,9 @@
  78  #define AR913X_AHB_DIV_SHIFT           19
  79  #define AR913X_AHB_DIV_MASK            0x1
  80
  81 +#define AR913X_ETH0_PLL_SHIFT          20
  82 +#define AR913X_ETH1_PLL_SHIFT          22
  83 +
  84  #define AR933X_PLL_CPU_CONFIG_REG      0x00
  85  #define AR933X_PLL_CLOCK_CTRL_REG      0x08
  86
  87 @@ -212,6 +236,8 @@
  88  #define AR934X_PLL_CPU_CONFIG_REG              0x00
  89  #define AR934X_PLL_DDR_CONFIG_REG              0x04
  90  #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG                0x08
  91 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG    0x24
  92 +#define AR934X_PLL_ETH_XMII_CONTROL_REG                0x2c
  93
  94  #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT      0
  95  #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK       0x3f
  96 @@ -244,6 +270,8 @@
  97  #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
  98  #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
  99
 100 +#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL   BIT(6)
 101 +
 102  #define QCA955X_PLL_CPU_CONFIG_REG             0x00
 103  #define QCA955X_PLL_DDR_CONFIG_REG             0x04
 104  #define QCA955X_PLL_CLK_CTRL_REG               0x08
 105 @@ -370,16 +398,50 @@
 106  #define AR913X_RESET_USB_HOST          BIT(5)
 107  #define AR913X_RESET_USB_PHY           BIT(4)
 108
 109 +#define AR933X_RESET_GE1_MDIO          BIT(23)
 110 +#define AR933X_RESET_GE0_MDIO          BIT(22)
 111 +#define AR933X_RESET_GE1_MAC           BIT(13)
 112  #define AR933X_RESET_WMAC              BIT(11)
 113 +#define AR933X_RESET_GE0_MAC           BIT(9)
 114  #define AR933X_RESET_USB_HOST          BIT(5)
 115  #define AR933X_RESET_USB_PHY           BIT(4)
 116  #define AR933X_RESET_USBSUS_OVERRIDE   BIT(3)
 117
 118 +#define AR934X_RESET_HOST              BIT(31)
 119 +#define AR934X_RESET_SLIC              BIT(30)
 120 +#define AR934X_RESET_HDMA              BIT(29)
 121 +#define AR934X_RESET_EXTERNAL          BIT(28)
 122 +#define AR934X_RESET_RTC               BIT(27)
 123 +#define AR934X_RESET_PCIE_EP_INT       BIT(26)
 124 +#define AR934X_RESET_CHKSUM_ACC                BIT(25)
 125 +#define AR934X_RESET_FULL_CHIP         BIT(24)
 126 +#define AR934X_RESET_GE1_MDIO          BIT(23)
 127 +#define AR934X_RESET_GE0_MDIO          BIT(22)
 128 +#define AR934X_RESET_CPU_NMI           BIT(21)
 129 +#define AR934X_RESET_CPU_COLD          BIT(20)
 130 +#define AR934X_RESET_HOST_RESET_INT    BIT(19)
 131 +#define AR934X_RESET_PCIE_EP           BIT(18)
 132 +#define AR934X_RESET_UART1             BIT(17)
 133 +#define AR934X_RESET_DDR               BIT(16)
 134 +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
 135 +#define AR934X_RESET_NANDF             BIT(14)
 136 +#define AR934X_RESET_GE1_MAC           BIT(13)
 137 +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
 138  #define AR934X_RESET_USB_PHY_ANALOG    BIT(11)
 139 +#define AR934X_RESET_HOST_DMA_INT      BIT(10)
 140 +#define AR934X_RESET_GE0_MAC           BIT(9)
 141 +#define AR934X_RESET_ETH_SWITCH                BIT(8)
 142 +#define AR934X_RESET_PCIE_PHY          BIT(7)
 143 +#define AR934X_RESET_PCIE              BIT(6)
 144  #define AR934X_RESET_USB_HOST          BIT(5)
 145  #define AR934X_RESET_USB_PHY           BIT(4)
 146  #define AR934X_RESET_USBSUS_OVERRIDE   BIT(3)
 147 +#define AR934X_RESET_LUT               BIT(2)
 148 +#define AR934X_RESET_MBOX              BIT(1)
 149 +#define AR934X_RESET_I2S               BIT(0)
 150
 151 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN  BIT(18)
 152 +#define AR933X_BOOTSTRAP_EEPBUSY       BIT(4)
 153  #define AR933X_BOOTSTRAP_REF_CLK_40    BIT(0)
 154
 155  #define AR934X_BOOTSTRAP_SW_OPTION8    BIT(23)
 156 @@ -520,6 +582,12 @@
 157  #define AR71XX_GPIO_REG_INT_ENABLE     0x24
 158  #define AR71XX_GPIO_REG_FUNC           0x28
 159
 160 +#define AR934X_GPIO_REG_OUT_FUNC0      0x2c
 161 +#define AR934X_GPIO_REG_OUT_FUNC1      0x30
 162 +#define AR934X_GPIO_REG_OUT_FUNC2      0x34
 163 +#define AR934X_GPIO_REG_OUT_FUNC3      0x38
 164 +#define AR934X_GPIO_REG_OUT_FUNC4      0x3c
 165 +#define AR934X_GPIO_REG_OUT_FUNC5      0x40
 166  #define AR934X_GPIO_REG_FUNC           0x6c
 167
 168  #define AR71XX_GPIO_COUNT              16
 169 @@ -550,4 +618,133 @@
 170  #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
 171  #define AR934X_SRIF_DPLL2_OUTDIV_MASK  0x7
 172
 173 +#define AR71XX_GPIO_FUNC_STEREO_EN             BIT(17)
 174 +#define AR71XX_GPIO_FUNC_SLIC_EN               BIT(16)
 175 +#define AR71XX_GPIO_FUNC_SPI_CS2_EN            BIT(13)
 176 +#define AR71XX_GPIO_FUNC_SPI_CS1_EN            BIT(12)
 177 +#define AR71XX_GPIO_FUNC_UART_EN               BIT(8)
 178 +#define AR71XX_GPIO_FUNC_USB_OC_EN             BIT(4)
 179 +#define AR71XX_GPIO_FUNC_USB_CLK_EN            BIT(0)
 180 +
 181 +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN                BIT(19)
 182 +#define AR724X_GPIO_FUNC_SPI_EN                        BIT(18)
 183 +#define AR724X_GPIO_FUNC_SPI_CS_EN2            BIT(14)
 184 +#define AR724X_GPIO_FUNC_SPI_CS_EN1            BIT(13)
 185 +#define AR724X_GPIO_FUNC_CLK_OBS5_EN           BIT(12)
 186 +#define AR724X_GPIO_FUNC_CLK_OBS4_EN           BIT(11)
 187 +#define AR724X_GPIO_FUNC_CLK_OBS3_EN           BIT(10)
 188 +#define AR724X_GPIO_FUNC_CLK_OBS2_EN           BIT(9)
 189 +#define AR724X_GPIO_FUNC_CLK_OBS1_EN           BIT(8)
 190 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN    BIT(7)
 191 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN    BIT(6)
 192 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN    BIT(5)
 193 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN    BIT(4)
 194 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN    BIT(3)
 195 +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN       BIT(2)
 196 +#define AR724X_GPIO_FUNC_UART_EN               BIT(1)
 197 +#define AR724X_GPIO_FUNC_JTAG_DISABLE          BIT(0)
 198 +
 199 +#define AR913X_GPIO_FUNC_WMAC_LED_EN           BIT(22)
 200 +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN                BIT(21)
 201 +#define AR913X_GPIO_FUNC_I2S_REFCLKEN          BIT(20)
 202 +#define AR913X_GPIO_FUNC_I2S_MCKEN             BIT(19)
 203 +#define AR913X_GPIO_FUNC_I2S1_EN               BIT(18)
 204 +#define AR913X_GPIO_FUNC_I2S0_EN               BIT(17)
 205 +#define AR913X_GPIO_FUNC_SLIC_EN               BIT(16)
 206 +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN                BIT(9)
 207 +#define AR913X_GPIO_FUNC_UART_EN               BIT(8)
 208 +#define AR913X_GPIO_FUNC_USB_CLK_EN            BIT(4)
 209 +
 210 +#define AR933X_GPIO_FUNC_SPDIF2TCK             BIT(31)
 211 +#define AR933X_GPIO_FUNC_SPDIF_EN              BIT(30)
 212 +#define AR933X_GPIO_FUNC_I2SO_22_18_EN         BIT(29)
 213 +#define AR933X_GPIO_FUNC_I2S_MCK_EN            BIT(27)
 214 +#define AR933X_GPIO_FUNC_I2SO_EN               BIT(26)
 215 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL   BIT(25)
 216 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL   BIT(24)
 217 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT    BIT(23)
 218 +#define AR933X_GPIO_FUNC_SPI_EN                        BIT(18)
 219 +#define AR933X_GPIO_FUNC_SPI_CS_EN2            BIT(14)
 220 +#define AR933X_GPIO_FUNC_SPI_CS_EN1            BIT(13)
 221 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN    BIT(7)
 222 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN    BIT(6)
 223 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN    BIT(5)
 224 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN    BIT(4)
 225 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN    BIT(3)
 226 +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN       BIT(2)
 227 +#define AR933X_GPIO_FUNC_UART_EN               BIT(1)
 228 +#define AR933X_GPIO_FUNC_JTAG_DISABLE          BIT(0)
 229 +
 230 +#define AR934X_GPIO_FUNC_DDR_DQOE_EN   BIT(17)
 231 +#define AR934X_GPIO_FUNC_SPI_CS_1_EN   BIT(14)
 232 +#define AR934X_GPIO_FUNC_SPI_CS_0_EN   BIT(13)
 233 +
 234 +#define AR934X_GPIO_OUT_GPIO           0x00
 235 +
 236 +/*
 237 + * MII_CTRL block
 238 + */
 239 +#define AR71XX_MII_REG_MII0_CTRL       0x00
 240 +#define AR71XX_MII_REG_MII1_CTRL       0x04
 241 +
 242 +#define AR71XX_MII_CTRL_IF_MASK                3
 243 +#define AR71XX_MII_CTRL_SPEED_SHIFT    4
 244 +#define AR71XX_MII_CTRL_SPEED_MASK     3
 245 +#define AR71XX_MII_CTRL_SPEED_10       0
 246 +#define AR71XX_MII_CTRL_SPEED_100      1
 247 +#define AR71XX_MII_CTRL_SPEED_1000     2
 248 +
 249 +#define AR71XX_MII0_CTRL_IF_GMII       0
 250 +#define AR71XX_MII0_CTRL_IF_MII                1
 251 +#define AR71XX_MII0_CTRL_IF_RGMII      2
 252 +#define AR71XX_MII0_CTRL_IF_RMII       3
 253 +
 254 +#define AR71XX_MII1_CTRL_IF_RGMII      0
 255 +#define AR71XX_MII1_CTRL_IF_RMII       1
 256 +
 257 +/*
 258 + * AR933X GMAC interface
 259 + */
 260 +#define AR933X_GMAC_REG_ETH_CFG                0x00
 261 +
 262 +#define AR933X_ETH_CFG_RGMII_GE0       BIT(0)
 263 +#define AR933X_ETH_CFG_MII_GE0         BIT(1)
 264 +#define AR933X_ETH_CFG_GMII_GE0                BIT(2)
 265 +#define AR933X_ETH_CFG_MII_GE0_MASTER  BIT(3)
 266 +#define AR933X_ETH_CFG_MII_GE0_SLAVE   BIT(4)
 267 +#define AR933X_ETH_CFG_MII_GE0_ERR_EN  BIT(5)
 268 +#define AR933X_ETH_CFG_SW_PHY_SWAP     BIT(7)
 269 +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP        BIT(8)
 270 +#define AR933X_ETH_CFG_RMII_GE0                BIT(9)
 271 +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
 272 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100        BIT(10)
 273 +
 274 +/*
 275 + * AR934X GMAC Interface
 276 + */
 277 +#define AR934X_GMAC_REG_ETH_CFG                0x00
 278 +
 279 +#define AR934X_ETH_CFG_RGMII_GMAC0     BIT(0)
 280 +#define AR934X_ETH_CFG_MII_GMAC0       BIT(1)
 281 +#define AR934X_ETH_CFG_GMII_GMAC0      BIT(2)
 282 +#define AR934X_ETH_CFG_MII_GMAC0_MASTER        BIT(3)
 283 +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
 284 +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN        BIT(5)
 285 +#define AR934X_ETH_CFG_SW_ONLY_MODE    BIT(6)
 286 +#define AR934X_ETH_CFG_SW_PHY_SWAP     BIT(7)
 287 +#define AR934X_ETH_CFG_SW_APB_ACCESS   BIT(9)
 288 +#define AR934X_ETH_CFG_RMII_GMAC0      BIT(10)
 289 +#define AR933X_ETH_CFG_MII_CNTL_SPEED  BIT(11)
 290 +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
 291 +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST        BIT(13)
 292 +
 293 +/*
 294 + * QCA955X GMAC Interface
 295 + */
 296 +
 297 +#define QCA955X_GMAC_REG_ETH_CFG       0x00
 298 +
 299 +#define QCA955X_ETH_CFG_RGMII_GMAC0    BIT(0)
 300 +#define QCA955X_ETH_CFG_SGMII_GMAC0    BIT(6)
 301 +
 302  #endif /* __ASM_MACH_AR71XX_REGS_H */