1 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
2 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
5 #include <linux/bitops.h>
7 +#define AR71XX_PCI_MEM_BASE 0x10000000
8 +#define AR71XX_PCI_MEM_SIZE 0x08000000
9 #define AR71XX_APB_BASE 0x18000000
10 +#define AR71XX_GE0_BASE 0x19000000
11 +#define AR71XX_GE0_SIZE 0x10000
12 +#define AR71XX_GE1_BASE 0x1a000000
13 +#define AR71XX_GE1_SIZE 0x10000
14 #define AR71XX_EHCI_BASE 0x1b000000
15 #define AR71XX_EHCI_SIZE 0x1000
16 #define AR71XX_OHCI_BASE 0x1c000000
18 #define AR71XX_PLL_SIZE 0x100
19 #define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000)
20 #define AR71XX_RESET_SIZE 0x100
21 +#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000)
22 +#define AR71XX_MII_SIZE 0x100
24 #define AR7240_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
25 #define AR7240_USB_CTRL_SIZE 0x100
28 #define AR933X_UART_BASE (AR71XX_APB_BASE + 0x00020000)
29 #define AR933X_UART_SIZE 0x14
30 +#define AR933X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
31 +#define AR933X_GMAC_SIZE 0x04
32 #define AR933X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
33 #define AR933X_WMAC_SIZE 0x20000
34 #define AR933X_EHCI_BASE 0x1b000000
35 #define AR933X_EHCI_SIZE 0x1000
37 +#define AR934X_GMAC_BASE (AR71XX_APB_BASE + 0x00070000)
38 +#define AR934X_GMAC_SIZE 0x14
39 #define AR934X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
40 #define AR934X_WMAC_SIZE 0x20000
41 #define AR934X_EHCI_BASE 0x1b000000
43 #define AR71XX_AHB_DIV_SHIFT 20
44 #define AR71XX_AHB_DIV_MASK 0x7
46 +#define AR71XX_ETH0_PLL_SHIFT 17
47 +#define AR71XX_ETH1_PLL_SHIFT 19
49 #define AR724X_PLL_REG_CPU_CONFIG 0x00
50 #define AR724X_PLL_REG_PCIE_CONFIG 0x18
53 #define AR724X_DDR_DIV_SHIFT 22
54 #define AR724X_DDR_DIV_MASK 0x3
56 +#define AR7242_PLL_REG_ETH0_INT_CLOCK 0x2c
58 #define AR913X_PLL_REG_CPU_CONFIG 0x00
59 #define AR913X_PLL_REG_ETH_CONFIG 0x04
60 #define AR913X_PLL_REG_ETH0_INT_CLOCK 0x14
62 #define AR913X_AHB_DIV_SHIFT 19
63 #define AR913X_AHB_DIV_MASK 0x1
65 +#define AR913X_ETH0_PLL_SHIFT 20
66 +#define AR913X_ETH1_PLL_SHIFT 22
68 #define AR933X_PLL_CPU_CONFIG_REG 0x00
69 #define AR933X_PLL_CLOCK_CTRL_REG 0x08
72 #define AR934X_PLL_CPU_CONFIG_REG 0x00
73 #define AR934X_PLL_DDR_CONFIG_REG 0x04
74 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
75 +#define AR934X_PLL_ETH_XMII_CONTROL_REG 0x2c
77 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
78 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
80 #define AR913X_RESET_USB_HOST BIT(5)
81 #define AR913X_RESET_USB_PHY BIT(4)
83 +#define AR933X_RESET_GE1_MDIO BIT(23)
84 +#define AR933X_RESET_GE0_MDIO BIT(22)
85 +#define AR933X_RESET_GE1_MAC BIT(13)
86 #define AR933X_RESET_WMAC BIT(11)
87 +#define AR933X_RESET_GE0_MAC BIT(9)
88 #define AR933X_RESET_USB_HOST BIT(5)
89 #define AR933X_RESET_USB_PHY BIT(4)
90 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
92 +#define AR934X_RESET_HOST BIT(31)
93 +#define AR934X_RESET_SLIC BIT(30)
94 +#define AR934X_RESET_HDMA BIT(29)
95 +#define AR934X_RESET_EXTERNAL BIT(28)
96 +#define AR934X_RESET_RTC BIT(27)
97 +#define AR934X_RESET_PCIE_EP_INT BIT(26)
98 +#define AR934X_RESET_CHKSUM_ACC BIT(25)
99 +#define AR934X_RESET_FULL_CHIP BIT(24)
100 +#define AR934X_RESET_GE1_MDIO BIT(23)
101 +#define AR934X_RESET_GE0_MDIO BIT(22)
102 +#define AR934X_RESET_CPU_NMI BIT(21)
103 +#define AR934X_RESET_CPU_COLD BIT(20)
104 +#define AR934X_RESET_HOST_RESET_INT BIT(19)
105 +#define AR934X_RESET_PCIE_EP BIT(18)
106 +#define AR934X_RESET_UART1 BIT(17)
107 +#define AR934X_RESET_DDR BIT(16)
108 +#define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
109 +#define AR934X_RESET_NANDF BIT(14)
110 +#define AR934X_RESET_GE1_MAC BIT(13)
111 +#define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
112 #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
113 +#define AR934X_RESET_HOST_DMA_INT BIT(10)
114 +#define AR934X_RESET_GE0_MAC BIT(9)
115 +#define AR934X_RESET_ETH_SWITCH BIT(8)
116 +#define AR934X_RESET_PCIE_PHY BIT(7)
117 +#define AR934X_RESET_PCIE BIT(6)
118 #define AR934X_RESET_USB_HOST BIT(5)
119 #define AR934X_RESET_USB_PHY BIT(4)
120 #define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
121 +#define AR934X_RESET_LUT BIT(2)
122 +#define AR934X_RESET_MBOX BIT(1)
123 +#define AR934X_RESET_I2S BIT(0)
125 +#define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
126 +#define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
127 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
129 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
130 @@ -399,10 +454,138 @@
131 #define AR71XX_GPIO_REG_INT_ENABLE 0x24
132 #define AR71XX_GPIO_REG_FUNC 0x28
134 +#define AR934X_GPIO_REG_OUT_FUNC0 0x2c
135 +#define AR934X_GPIO_REG_OUT_FUNC1 0x30
136 +#define AR934X_GPIO_REG_OUT_FUNC2 0x34
137 +#define AR934X_GPIO_REG_OUT_FUNC3 0x38
138 +#define AR934X_GPIO_REG_OUT_FUNC4 0x3c
139 +#define AR934X_GPIO_REG_OUT_FUNC5 0x40
140 +#define AR934X_GPIO_REG_FUNC 0x6c
142 #define AR71XX_GPIO_COUNT 16
143 #define AR724X_GPIO_COUNT 18
144 #define AR913X_GPIO_COUNT 22
145 #define AR933X_GPIO_COUNT 30
146 #define AR934X_GPIO_COUNT 23
148 +#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
149 +#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
150 +#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
151 +#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
152 +#define AR71XX_GPIO_FUNC_UART_EN BIT(8)
153 +#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
154 +#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
156 +#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
157 +#define AR724X_GPIO_FUNC_SPI_EN BIT(18)
158 +#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
159 +#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
160 +#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
161 +#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
162 +#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
163 +#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
164 +#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
165 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
166 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
167 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
168 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
169 +#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
170 +#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
171 +#define AR724X_GPIO_FUNC_UART_EN BIT(1)
172 +#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
174 +#define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
175 +#define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
176 +#define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
177 +#define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
178 +#define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
179 +#define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
180 +#define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
181 +#define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
182 +#define AR913X_GPIO_FUNC_UART_EN BIT(8)
183 +#define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
185 +#define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
186 +#define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
187 +#define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
188 +#define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
189 +#define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
190 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
191 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
192 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
193 +#define AR933X_GPIO_FUNC_SPI_EN BIT(18)
194 +#define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
195 +#define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
196 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
197 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
198 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
199 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
200 +#define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
201 +#define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
202 +#define AR933X_GPIO_FUNC_UART_EN BIT(1)
203 +#define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
205 +#define AR934X_GPIO_FUNC_DDR_DQOE_EN BIT(17)
206 +#define AR934X_GPIO_FUNC_SPI_CS_1_EN BIT(14)
207 +#define AR934X_GPIO_FUNC_SPI_CS_0_EN BIT(13)
209 +#define AR934X_GPIO_OUT_GPIO 0x00
214 +#define AR71XX_MII_REG_MII0_CTRL 0x00
215 +#define AR71XX_MII_REG_MII1_CTRL 0x04
217 +#define AR71XX_MII_CTRL_IF_MASK 3
218 +#define AR71XX_MII_CTRL_SPEED_SHIFT 4
219 +#define AR71XX_MII_CTRL_SPEED_MASK 3
220 +#define AR71XX_MII_CTRL_SPEED_10 0
221 +#define AR71XX_MII_CTRL_SPEED_100 1
222 +#define AR71XX_MII_CTRL_SPEED_1000 2
224 +#define AR71XX_MII0_CTRL_IF_GMII 0
225 +#define AR71XX_MII0_CTRL_IF_MII 1
226 +#define AR71XX_MII0_CTRL_IF_RGMII 2
227 +#define AR71XX_MII0_CTRL_IF_RMII 3
229 +#define AR71XX_MII1_CTRL_IF_RGMII 0
230 +#define AR71XX_MII1_CTRL_IF_RMII 1
233 + * AR933X GMAC interface
235 +#define AR933X_GMAC_REG_ETH_CFG 0x00
237 +#define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
238 +#define AR933X_ETH_CFG_MII_GE0 BIT(1)
239 +#define AR933X_ETH_CFG_GMII_GE0 BIT(2)
240 +#define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
241 +#define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
242 +#define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
243 +#define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
244 +#define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
245 +#define AR933X_ETH_CFG_RMII_GE0 BIT(9)
246 +#define AR933X_ETH_CFG_RMII_GE0_SPD_10 0
247 +#define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
250 + * AR934X GMAC Interface
252 +#define AR934X_GMAC_REG_ETH_CFG 0x00
254 +#define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
255 +#define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
256 +#define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
257 +#define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
258 +#define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
259 +#define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
260 +#define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
261 +#define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
262 +#define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
263 +#define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
264 +#define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
265 +#define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
266 +#define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
268 #endif /* __ASM_MACH_AR71XX_REGS_H */
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