1 --- a/arch/mips/ath79/mach-db120.c
2 +++ b/arch/mips/ath79/mach-db120.c
4 * Atheros DB120 reference board support
6 * Copyright (c) 2011 Qualcomm Atheros
7 - * Copyright (c) 2011 Gabor Juhos <juhosg@openwrt.org>
8 + * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
10 * Permission to use, copy, modify, and/or distribute this software for any
11 * purpose with or without fee is hereby granted, provided that the above
15 #include <linux/pci.h>
16 +#include <linux/phy.h>
17 +#include <linux/platform_device.h>
18 #include <linux/ath9k_platform.h>
19 +#include <linux/ar8216_platform.h>
21 -#include "machtypes.h"
22 +#include <asm/mach-ath79/ar71xx_regs.h>
25 +#include "dev-ap9x-pci.h"
27 #include "dev-gpio-buttons.h"
28 #include "dev-leds-gpio.h"
29 +#include "dev-m25p80.h"
34 +#include "machtypes.h"
36 +#define DB120_GPIO_LED_USB 11
37 #define DB120_GPIO_LED_WLAN_5G 12
38 #define DB120_GPIO_LED_WLAN_2G 13
39 #define DB120_GPIO_LED_STATUS 14
41 #define DB120_KEYS_POLL_INTERVAL 20 /* msecs */
42 #define DB120_KEYS_DEBOUNCE_INTERVAL (3 * DB120_KEYS_POLL_INTERVAL)
44 -#define DB120_WMAC_CALDATA_OFFSET 0x1000
45 -#define DB120_PCIE_CALDATA_OFFSET 0x5000
46 +#define DB120_MAC0_OFFSET 0
47 +#define DB120_MAC1_OFFSET 6
48 +#define DB120_WMAC_CALDATA_OFFSET 0x1000
49 +#define DB120_PCIE_CALDATA_OFFSET 0x5000
51 static struct gpio_led db120_leds_gpio[] __initdata = {
53 @@ -63,6 +74,11 @@ static struct gpio_led db120_leds_gpio[]
54 .gpio = DB120_GPIO_LED_WLAN_2G,
58 + .name = "db120:green:usb",
59 + .gpio = DB120_GPIO_LED_USB,
64 static struct gpio_keys_button db120_gpio_keys[] __initdata = {
65 @@ -76,66 +92,99 @@ static struct gpio_keys_button db120_gpi
69 -static struct ath79_spi_controller_data db120_spi0_data = {
70 - .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
72 +static struct ar8327_pad_cfg db120_ar8327_pad0_cfg = {
73 + .mode = AR8327_PAD_MAC_RGMII,
74 + .txclk_delay_en = true,
75 + .rxclk_delay_en = true,
76 + .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
77 + .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
80 -static struct spi_board_info db120_spi_info[] = {
84 - .max_speed_hz = 25000000,
85 - .modalias = "s25sl064a",
86 - .controller_data = &db120_spi0_data,
88 +static struct ar8327_led_cfg db120_ar8327_led_cfg = {
89 + .led_ctrl0 = 0x00000000,
90 + .led_ctrl1 = 0xc737c737,
91 + .led_ctrl2 = 0x00000000,
92 + .led_ctrl3 = 0x00c30c00,
96 -static struct ath79_spi_platform_data db120_spi_data = {
98 - .num_chipselect = 1,
99 +static struct ar8327_platform_data db120_ar8327_data = {
100 + .pad0_cfg = &db120_ar8327_pad0_cfg,
103 + .speed = AR8327_PORT_SPEED_1000,
108 + .led_cfg = &db120_ar8327_led_cfg,
112 -static struct ath9k_platform_data db120_ath9k_data;
113 +static struct mdio_board_info db120_mdio0_info[] = {
115 + .bus_id = "ag71xx-mdio.0",
117 + .platform_data = &db120_ar8327_data,
121 -static int db120_pci_plat_dev_init(struct pci_dev *dev)
122 +static void __init db120_gmac_setup(void)
124 - switch (PCI_SLOT(dev->devfn)) {
126 - dev->dev.platform_data = &db120_ath9k_data;
129 + void __iomem *base;
134 + base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
136 -static void __init db120_pci_init(u8 *eeprom)
138 - memcpy(db120_ath9k_data.eeprom_data, eeprom,
139 - sizeof(db120_ath9k_data.eeprom_data));
140 + t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
141 + t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_MII_GMAC0 |
142 + AR934X_ETH_CFG_GMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE);
143 + t |= AR934X_ETH_CFG_RGMII_GMAC0 | AR934X_ETH_CFG_SW_ONLY_MODE;
145 + __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
147 - ath79_pci_set_plat_dev_init(db120_pci_plat_dev_init);
148 - ath79_register_pci();
152 -static inline void db120_pci_init(void) {}
153 -#endif /* CONFIG_PCI */
155 static void __init db120_setup(void)
157 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
159 + ath79_gpio_output_select(DB120_GPIO_LED_USB, AR934X_GPIO_OUT_GPIO);
160 + ath79_register_m25p80(NULL);
162 ath79_register_leds_gpio(-1, ARRAY_SIZE(db120_leds_gpio),
164 ath79_register_gpio_keys_polled(-1, DB120_KEYS_POLL_INTERVAL,
165 ARRAY_SIZE(db120_gpio_keys),
167 - ath79_register_spi(&db120_spi_data, db120_spi_info,
168 - ARRAY_SIZE(db120_spi_info));
169 ath79_register_usb();
170 ath79_register_wmac(art + DB120_WMAC_CALDATA_OFFSET, NULL);
171 - db120_pci_init(art + DB120_PCIE_CALDATA_OFFSET);
172 + ap91_pci_init(art + DB120_PCIE_CALDATA_OFFSET, NULL);
174 + db120_gmac_setup();
176 + ath79_register_mdio(1, 0x0);
177 + ath79_register_mdio(0, 0x0);
179 + ath79_init_mac(ath79_eth0_data.mac_addr, art + DB120_MAC0_OFFSET, 0);
181 + mdiobus_register_board_info(db120_mdio0_info,
182 + ARRAY_SIZE(db120_mdio0_info));
184 + /* GMAC0 is connected to an AR8327 switch */
185 + ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
186 + ath79_eth0_data.phy_mask = BIT(0);
187 + ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
188 + ath79_eth0_pll_data.pll_1000 = 0x06000000;
189 + ath79_register_eth(0);
191 + /* GMAC1 is connected to the internal switch */
192 + ath79_init_mac(ath79_eth1_data.mac_addr, art + DB120_MAC1_OFFSET, 0);
193 + ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
194 + ath79_eth1_data.speed = SPEED_1000;
195 + ath79_eth1_data.duplex = DUPLEX_FULL;
197 + ath79_register_eth(1);
200 MIPS_MACHINE(ATH79_MACH_DB120, "DB120", "Atheros DB120 reference board",
201 --- a/arch/mips/ath79/Kconfig
202 +++ b/arch/mips/ath79/Kconfig
203 @@ -43,9 +43,11 @@ config ATH79_MACH_AP81
204 config ATH79_MACH_DB120
205 bool "Atheros DB120 reference board"
207 + select ATH79_DEV_AP9X_PCI if PCI
208 + select ATH79_DEV_ETH
209 select ATH79_DEV_GPIO_BUTTONS
210 select ATH79_DEV_LEDS_GPIO
211 - select ATH79_DEV_SPI
212 + select ATH79_DEV_M25P80
214 select ATH79_DEV_WMAC