target/linux/ar71xx/patches-3.3/609-MIPS-ath79-ap136-fixes.patch

   1 --- a/arch/mips/ath79/mach-ap136.c
   2 +++ b/arch/mips/ath79/mach-ap136.c
   3 @@ -1,5 +1,5 @@
   4  /*
   5 - * Qualcomm Atheros AP136 reference board support
   6 + * Atheros AP136 reference board support
   7   *
   8   * Copyright (c) 2012 Qualcomm Atheros
   9   * Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
  10 @@ -18,23 +18,27 @@
  11   *
  12   */
  13
  14 -#include <linux/pci.h>
  15 -#include <linux/ath9k_platform.h>
  16 +#include <linux/platform_device.h>
  17 +#include <linux/ar8216_platform.h>
  18
  19 -#include "machtypes.h"
  20 +#include <asm/mach-ath79/ar71xx_regs.h>
  21 +
  22 +#include "common.h"
  23 +#include "dev-ap9x-pci.h"
  24  #include "dev-gpio-buttons.h"
  25 +#include "dev-eth.h"
  26  #include "dev-leds-gpio.h"
  27 -#include "dev-spi.h"
  28 +#include "dev-m25p80.h"
  29  #include "dev-usb.h"
  30  #include "dev-wmac.h"
  31 -#include "pci.h"
  32 +#include "machtypes.h"
  33
  34 -#define AP136_GPIO_LED_STATUS_RED      14
  35 -#define AP136_GPIO_LED_STATUS_GREEN    19
  36  #define AP136_GPIO_LED_USB             4
  37 -#define AP136_GPIO_LED_WLAN_2G         13
  38  #define AP136_GPIO_LED_WLAN_5G         12
  39 +#define AP136_GPIO_LED_WLAN_2G         13
  40 +#define AP136_GPIO_LED_STATUS_RED      14
  41  #define AP136_GPIO_LED_WPS_RED         15
  42 +#define AP136_GPIO_LED_STATUS_GREEN    19
  43  #define AP136_GPIO_LED_WPS_GREEN       20
  44
  45  #define AP136_GPIO_BTN_WPS             16
  46 @@ -43,8 +47,10 @@
  47  #define AP136_KEYS_POLL_INTERVAL       20      /* msecs */
  48  #define AP136_KEYS_DEBOUNCE_INTERVAL   (3 * AP136_KEYS_POLL_INTERVAL)
  49
  50 -#define AP136_WMAC_CALDATA_OFFSET 0x1000
  51 -#define AP136_PCIE_CALDATA_OFFSET 0x5000
  52 +#define AP136_MAC0_OFFSET              0
  53 +#define AP136_MAC1_OFFSET              6
  54 +#define AP136_WMAC_CALDATA_OFFSET      0x1000
  55 +#define AP136_PCIE_CALDATA_OFFSET      0x5000
  56
  57  static struct gpio_led ap136_leds_gpio[] __initdata = {
  58         {
  59 @@ -98,63 +104,82 @@ static struct gpio_keys_button ap136_gpi
  60         },
  61  };
  62
  63 -static struct ath79_spi_controller_data ap136_spi0_data = {
  64 -       .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
  65 -       .cs_line = 0,
  66 +static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg = {
  67 +       .mode = AR8327_PAD_MAC_RGMII,
  68 +       .txclk_delay_en = true,
  69 +       .rxclk_delay_en = true,
  70 +       .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
  71 +       .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
  72  };
  73
  74 -static struct spi_board_info ap136_spi_info[] = {
  75 -       {
  76 -               .bus_num        = 0,
  77 -               .chip_select    = 0,
  78 -               .max_speed_hz   = 25000000,
  79 -               .modalias       = "mx25l6405d",
  80 -               .controller_data = &ap136_spi0_data,
  81 +static struct ar8327_platform_data ap136_ar8327_data = {
  82 +       .pad0_cfg = &ap136_ar8327_pad0_cfg,
  83 +       .cpuport_cfg = {
  84 +               .force_link = 1,
  85 +               .speed = AR8327_PORT_SPEED_1000,
  86 +               .duplex = 1,
  87 +               .txpause = 1,
  88 +               .rxpause = 1,
  89         }
  90  };
  91
  92 -static struct ath79_spi_platform_data ap136_spi_data = {
  93 -       .bus_num        = 0,
  94 -       .num_chipselect = 1,
  95 +static struct mdio_board_info ap136_mdio0_info[] = {
  96 +       {
  97 +               .bus_id = "ag71xx-mdio.0",
  98 +               .phy_addr = 0,
  99 +               .platform_data = &ap136_ar8327_data,
 100 +       },
 101  };
 102
 103 -#ifdef CONFIG_PCI
 104 -static struct ath9k_platform_data ap136_ath9k_data;
 105 -
 106 -static int ap136_pci_plat_dev_init(struct pci_dev *dev)
 107 +static void __init ap136_gmac_setup(void)
 108  {
 109 -       if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
 110 -               dev->dev.platform_data = &ap136_ath9k_data;
 111 +       void __iomem *base;
 112 +       u32 t;
 113
 114 -       return 0;
 115 -}
 116 +       base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
 117
 118 -static void __init ap136_pci_init(u8 *eeprom)
 119 -{
 120 -       memcpy(ap136_ath9k_data.eeprom_data, eeprom,
 121 -              sizeof(ap136_ath9k_data.eeprom_data));
 122 +       t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
 123 +
 124 +       t &= ~(QCA955X_ETH_CFG_RGMII_GMAC0 | QCA955X_ETH_CFG_SGMII_GMAC0);
 125 +       t |= QCA955X_ETH_CFG_RGMII_GMAC0;
 126
 127 -       ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
 128 -       ath79_register_pci();
 129 +       __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
 130 +
 131 +       iounmap(base);
 132  }
 133 -#else
 134 -static inline void ap136_pci_init(void) {}
 135 -#endif /* CONFIG_PCI */
 136
 137  static void __init ap136_setup(void)
 138  {
 139         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 140
 141 +       ath79_register_m25p80(NULL);
 142 +
 143         ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
 144                                  ap136_leds_gpio);
 145         ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
 146                                         ARRAY_SIZE(ap136_gpio_keys),
 147                                         ap136_gpio_keys);
 148 -       ath79_register_spi(&ap136_spi_data, ap136_spi_info,
 149 -                          ARRAY_SIZE(ap136_spi_info));
 150 +
 151         ath79_register_usb();
 152 -       ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
 153 -       ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
 154 +       ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
 155 +       ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
 156 +
 157 +       ap136_gmac_setup();
 158 +
 159 +       ath79_register_mdio(0, 0x0);
 160 +
 161 +       ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
 162 +
 163 +       mdiobus_register_board_info(ap136_mdio0_info,
 164 +                                   ARRAY_SIZE(ap136_mdio0_info));
 165 +
 166 +       /* GMAC0 is connected to an AR8327 switch */
 167 +       ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
 168 +       ath79_eth0_data.phy_mask = BIT(0);
 169 +       ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 170 +       ath79_eth0_pll_data.pll_1000 = 0x06000000;
 171 +
 172 +       ath79_register_eth(0);
 173  }
 174
 175  MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board",