target/linux/ar71xx/patches-3.6/162-MIPS-ath79-add-clock-setup-for-the-QCA955X-SoCs.patch

   1 From f465a16766a015a31d4e83af1ad62cc718d64f5a Mon Sep 17 00:00:00 2001
   2 From: Gabor Juhos <juhosg@openwrt.org>
   3 Date: Sun, 24 Jun 2012 13:43:08 +0200
   4 Subject: [PATCH 18/34] MIPS: ath79: add clock setup for the QCA955X SoCs
   5
   6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
   7 ---
   8  arch/mips/ath79/clock.c                        |   78 ++++++++++++++++++++++++
   9  arch/mips/include/asm/mach-ath79/ar71xx_regs.h |   39 ++++++++++++
  10  2 files changed, 117 insertions(+), 0 deletions(-)
  11
  12 --- a/arch/mips/ath79/clock.c
  13 +++ b/arch/mips/ath79/clock.c
  14 @@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo
  15         iounmap(dpll_base);
  16  }
  17
  18 +static void __init qca955x_clocks_init(void)
  19 +{
  20 +       u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
  21 +       u32 cpu_pll, ddr_pll;
  22 +       u32 bootstrap;
  23 +
  24 +       bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
  25 +       if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
  26 +               ath79_ref_clk.rate = 40 * 1000 * 1000;
  27 +       else
  28 +               ath79_ref_clk.rate = 25 * 1000 * 1000;
  29 +
  30 +       pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
  31 +       out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  32 +                 QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
  33 +       ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  34 +                 QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
  35 +       nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
  36 +              QCA955X_PLL_CPU_CONFIG_NINT_MASK;
  37 +       frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
  38 +              QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
  39 +
  40 +       cpu_pll = nint * ath79_ref_clk.rate / ref_div;
  41 +       cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
  42 +       cpu_pll /= (1 << out_div);
  43 +
  44 +       pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
  45 +       out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  46 +                 QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
  47 +       ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  48 +                 QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
  49 +       nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
  50 +              QCA955X_PLL_DDR_CONFIG_NINT_MASK;
  51 +       frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
  52 +              QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
  53 +
  54 +       ddr_pll = nint * ath79_ref_clk.rate / ref_div;
  55 +       ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
  56 +       ddr_pll /= (1 << out_div);
  57 +
  58 +       clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
  59 +
  60 +       postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  61 +                 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  62 +
  63 +       if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
  64 +               ath79_cpu_clk.rate = ath79_ref_clk.rate;
  65 +       else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
  66 +               ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
  67 +       else
  68 +               ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
  69 +
  70 +       postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
  71 +                 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
  72 +
  73 +       if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
  74 +               ath79_ddr_clk.rate = ath79_ref_clk.rate;
  75 +       else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
  76 +               ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
  77 +       else
  78 +               ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
  79 +
  80 +       postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
  81 +                 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
  82 +
  83 +       if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
  84 +               ath79_ahb_clk.rate = ath79_ref_clk.rate;
  85 +       else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
  86 +               ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
  87 +       else
  88 +               ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
  89 +
  90 +       ath79_wdt_clk.rate = ath79_ref_clk.rate;
  91 +       ath79_uart_clk.rate = ath79_ref_clk.rate;
  92 +}
  93 +
  94  void __init ath79_clocks_init(void)
  95  {
  96         if (soc_is_ar71xx())
  97 @@ -307,6 +383,8 @@ void __init ath79_clocks_init(void)
  98                 ar933x_clocks_init();
  99         else if (soc_is_ar934x())
 100                 ar934x_clocks_init();
 101 +       else if (soc_is_qca955x())
 102 +               qca955x_clocks_init();
 103         else
 104                 BUG();
 105
 106 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 107 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
 108 @@ -225,6 +225,41 @@
 109  #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
 110  #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
 111
 112 +#define QCA955X_PLL_CPU_CONFIG_REG             0x00
 113 +#define QCA955X_PLL_DDR_CONFIG_REG             0x04
 114 +#define QCA955X_PLL_CLK_CTRL_REG               0x08
 115 +
 116 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
 117 +#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
 118 +#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT      6
 119 +#define QCA955X_PLL_CPU_CONFIG_NINT_MASK       0x3f
 120 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT    12
 121 +#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK     0x1f
 122 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT    19
 123 +#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK     0x3
 124 +
 125 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT     0
 126 +#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK      0x3ff
 127 +#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT      10
 128 +#define QCA955X_PLL_DDR_CONFIG_NINT_MASK       0x3f
 129 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT    16
 130 +#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK     0x1f
 131 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT    23
 132 +#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK     0x7
 133 +
 134 +#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS            BIT(2)
 135 +#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS            BIT(3)
 136 +#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS            BIT(4)
 137 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT                5
 138 +#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK         0x1f
 139 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT                10
 140 +#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK         0x1f
 141 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT                15
 142 +#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK         0x1f
 143 +#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL                BIT(20)
 144 +#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL                BIT(21)
 145 +#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL                BIT(24)
 146 +
 147  /*
 148   * USB_CONFIG block
 149   */
 150 @@ -264,6 +299,8 @@
 151  #define AR934X_RESET_REG_BOOTSTRAP             0xb0
 152  #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS  0xac
 153
 154 +#define QCA955X_RESET_REG_BOOTSTRAP            0xb0
 155 +
 156  #define MISC_INT_ETHSW                 BIT(12)
 157  #define MISC_INT_TIMER4                        BIT(10)
 158  #define MISC_INT_TIMER3                        BIT(9)
 159 @@ -341,6 +378,8 @@
 160  #define AR934X_BOOTSTRAP_SDRAM_DISABLED        BIT(1)
 161  #define AR934X_BOOTSTRAP_DDR1          BIT(0)
 162
 163 +#define QCA955X_BOOTSTRAP_REF_CLK_40   BIT(4)
 164 +
 165  #define AR934X_PCIE_WMAC_INT_WMAC_MISC         BIT(0)
 166  #define AR934X_PCIE_WMAC_INT_WMAC_TX           BIT(1)
 167  #define AR934X_PCIE_WMAC_INT_WMAC_RXLP         BIT(2)