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[openwrt/svn-archive/archive.git] / target / linux / ar71xx / patches-3.8 / 024-ath79-add-ATH79_CPU_IRQ-macro.patch
1 From 7377d32d37490f0804662c76a72b68d45d93966e Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Thu, 7 Feb 2013 19:32:23 +0000
4 Subject: [PATCH] ath79: add ATH79_CPU_IRQ() macro
5
6 commit 7e69c10a8ee1f201c040997c6742c27e915730ad upstream.
7
8 Remove the individual ATH79_CPU_IRQ_* constants and
9 use the new macro instead of those.
10
11 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
12 Patchwork: http://patchwork.linux-mips.org/patch/4929/
13 Signed-off-by: John Crispin <blogic@openwrt.org>
14 ---
15 arch/mips/ath79/dev-usb.c | 12 ++++++------
16 arch/mips/ath79/dev-wmac.c | 8 ++++----
17 arch/mips/ath79/irq.c | 32 ++++++++++++++++----------------
18 arch/mips/ath79/pci.c | 6 +++---
19 arch/mips/include/asm/mach-ath79/irq.h | 9 ++-------
20 5 files changed, 31 insertions(+), 36 deletions(-)
21
22 --- a/arch/mips/ath79/dev-usb.c
23 +++ b/arch/mips/ath79/dev-usb.c
24 @@ -111,7 +111,7 @@ static void __init ath79_usb_setup(void)
25 platform_device_register(&ath79_ohci_device);
26
27 ath79_usb_init_resource(ath79_ehci_resources, AR71XX_EHCI_BASE,
28 - AR71XX_EHCI_SIZE, ATH79_CPU_IRQ_USB);
29 + AR71XX_EHCI_SIZE, ATH79_CPU_IRQ(3));
30 ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v1;
31 platform_device_register(&ath79_ehci_device);
32 }
33 @@ -136,7 +136,7 @@ static void __init ar7240_usb_setup(void
34 iounmap(usb_ctrl_base);
35
36 ath79_usb_init_resource(ath79_ohci_resources, AR7240_OHCI_BASE,
37 - AR7240_OHCI_SIZE, ATH79_CPU_IRQ_USB);
38 + AR7240_OHCI_SIZE, ATH79_CPU_IRQ(3));
39 platform_device_register(&ath79_ohci_device);
40 }
41
42 @@ -152,7 +152,7 @@ static void __init ar724x_usb_setup(void
43 mdelay(10);
44
45 ath79_usb_init_resource(ath79_ehci_resources, AR724X_EHCI_BASE,
46 - AR724X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
47 + AR724X_EHCI_SIZE, ATH79_CPU_IRQ(3));
48 ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
49 platform_device_register(&ath79_ehci_device);
50 }
51 @@ -169,7 +169,7 @@ static void __init ar913x_usb_setup(void
52 mdelay(10);
53
54 ath79_usb_init_resource(ath79_ehci_resources, AR913X_EHCI_BASE,
55 - AR913X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
56 + AR913X_EHCI_SIZE, ATH79_CPU_IRQ(3));
57 ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
58 platform_device_register(&ath79_ehci_device);
59 }
60 @@ -186,7 +186,7 @@ static void __init ar933x_usb_setup(void
61 mdelay(10);
62
63 ath79_usb_init_resource(ath79_ehci_resources, AR933X_EHCI_BASE,
64 - AR933X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
65 + AR933X_EHCI_SIZE, ATH79_CPU_IRQ(3));
66 ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
67 platform_device_register(&ath79_ehci_device);
68 }
69 @@ -212,7 +212,7 @@ static void __init ar934x_usb_setup(void
70 udelay(1000);
71
72 ath79_usb_init_resource(ath79_ehci_resources, AR934X_EHCI_BASE,
73 - AR934X_EHCI_SIZE, ATH79_CPU_IRQ_USB);
74 + AR934X_EHCI_SIZE, ATH79_CPU_IRQ(3));
75 ath79_ehci_device.dev.platform_data = &ath79_ehci_pdata_v2;
76 platform_device_register(&ath79_ehci_device);
77 }
78 --- a/arch/mips/ath79/dev-wmac.c
79 +++ b/arch/mips/ath79/dev-wmac.c
80 @@ -55,8 +55,8 @@ static void __init ar913x_wmac_setup(voi
81
82 ath79_wmac_resources[0].start = AR913X_WMAC_BASE;
83 ath79_wmac_resources[0].end = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1;
84 - ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
85 - ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
86 + ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
87 + ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
88 }
89
90
91 @@ -83,8 +83,8 @@ static void __init ar933x_wmac_setup(voi
92
93 ath79_wmac_resources[0].start = AR933X_WMAC_BASE;
94 ath79_wmac_resources[0].end = AR933X_WMAC_BASE + AR933X_WMAC_SIZE - 1;
95 - ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
96 - ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
97 + ath79_wmac_resources[1].start = ATH79_CPU_IRQ(2);
98 + ath79_wmac_resources[1].end = ATH79_CPU_IRQ(2);
99
100 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
101 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
102 --- a/arch/mips/ath79/irq.c
103 +++ b/arch/mips/ath79/irq.c
104 @@ -114,7 +114,7 @@ static void __init ath79_misc_irq_init(v
105 handle_level_irq);
106 }
107
108 - irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
109 + irq_set_chained_handler(ATH79_CPU_IRQ(6), ath79_misc_irq_handler);
110 }
111
112 static void ar934x_ip2_irq_dispatch(unsigned int irq, struct irq_desc *desc)
113 @@ -147,7 +147,7 @@ static void ar934x_ip2_irq_init(void)
114 irq_set_chip_and_handler(i, &dummy_irq_chip,
115 handle_level_irq);
116
117 - irq_set_chained_handler(ATH79_CPU_IRQ_IP2, ar934x_ip2_irq_dispatch);
118 + irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
119 }
120
121 asmlinkage void plat_irq_dispatch(void)
122 @@ -157,22 +157,22 @@ asmlinkage void plat_irq_dispatch(void)
123 pending = read_c0_status() & read_c0_cause() & ST0_IM;
124
125 if (pending & STATUSF_IP7)
126 - do_IRQ(ATH79_CPU_IRQ_TIMER);
127 + do_IRQ(ATH79_CPU_IRQ(7));
128
129 else if (pending & STATUSF_IP2)
130 ath79_ip2_handler();
131
132 else if (pending & STATUSF_IP4)
133 - do_IRQ(ATH79_CPU_IRQ_GE0);
134 + do_IRQ(ATH79_CPU_IRQ(4));
135
136 else if (pending & STATUSF_IP5)
137 - do_IRQ(ATH79_CPU_IRQ_GE1);
138 + do_IRQ(ATH79_CPU_IRQ(5));
139
140 else if (pending & STATUSF_IP3)
141 ath79_ip3_handler();
142
143 else if (pending & STATUSF_IP6)
144 - do_IRQ(ATH79_CPU_IRQ_MISC);
145 + do_IRQ(ATH79_CPU_IRQ(6));
146
147 else
148 spurious_interrupt();
149 @@ -188,60 +188,60 @@ asmlinkage void plat_irq_dispatch(void)
150 static void ar71xx_ip2_handler(void)
151 {
152 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_PCI);
153 - do_IRQ(ATH79_CPU_IRQ_IP2);
154 + do_IRQ(ATH79_CPU_IRQ(2));
155 }
156
157 static void ar724x_ip2_handler(void)
158 {
159 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_PCIE);
160 - do_IRQ(ATH79_CPU_IRQ_IP2);
161 + do_IRQ(ATH79_CPU_IRQ(2));
162 }
163
164 static void ar913x_ip2_handler(void)
165 {
166 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_WMAC);
167 - do_IRQ(ATH79_CPU_IRQ_IP2);
168 + do_IRQ(ATH79_CPU_IRQ(2));
169 }
170
171 static void ar933x_ip2_handler(void)
172 {
173 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_WMAC);
174 - do_IRQ(ATH79_CPU_IRQ_IP2);
175 + do_IRQ(ATH79_CPU_IRQ(2));
176 }
177
178 static void ar934x_ip2_handler(void)
179 {
180 - do_IRQ(ATH79_CPU_IRQ_IP2);
181 + do_IRQ(ATH79_CPU_IRQ(2));
182 }
183
184 static void ar71xx_ip3_handler(void)
185 {
186 ath79_ddr_wb_flush(AR71XX_DDR_REG_FLUSH_USB);
187 - do_IRQ(ATH79_CPU_IRQ_USB);
188 + do_IRQ(ATH79_CPU_IRQ(3));
189 }
190
191 static void ar724x_ip3_handler(void)
192 {
193 ath79_ddr_wb_flush(AR724X_DDR_REG_FLUSH_USB);
194 - do_IRQ(ATH79_CPU_IRQ_USB);
195 + do_IRQ(ATH79_CPU_IRQ(3));
196 }
197
198 static void ar913x_ip3_handler(void)
199 {
200 ath79_ddr_wb_flush(AR913X_DDR_REG_FLUSH_USB);
201 - do_IRQ(ATH79_CPU_IRQ_USB);
202 + do_IRQ(ATH79_CPU_IRQ(3));
203 }
204
205 static void ar933x_ip3_handler(void)
206 {
207 ath79_ddr_wb_flush(AR933X_DDR_REG_FLUSH_USB);
208 - do_IRQ(ATH79_CPU_IRQ_USB);
209 + do_IRQ(ATH79_CPU_IRQ(3));
210 }
211
212 static void ar934x_ip3_handler(void)
213 {
214 ath79_ddr_wb_flush(AR934X_DDR_REG_FLUSH_USB);
215 - do_IRQ(ATH79_CPU_IRQ_USB);
216 + do_IRQ(ATH79_CPU_IRQ(3));
217 }
218
219 void __init arch_init_irq(void)
220 --- a/arch/mips/ath79/pci.c
221 +++ b/arch/mips/ath79/pci.c
222 @@ -127,8 +127,8 @@ ath79_register_pci_ar71xx(void)
223 res[0].end = AR71XX_PCI_CFG_BASE + AR71XX_PCI_CFG_SIZE - 1;
224
225 res[1].flags = IORESOURCE_IRQ;
226 - res[1].start = ATH79_CPU_IRQ_IP2;
227 - res[1].end = ATH79_CPU_IRQ_IP2;
228 + res[1].start = ATH79_CPU_IRQ(2);
229 + res[1].end = ATH79_CPU_IRQ(2);
230
231 res[2].name = "io_base";
232 res[2].flags = IORESOURCE_IO;
233 @@ -208,7 +208,7 @@ int __init ath79_register_pci(void)
234 AR724X_PCI_MEM_BASE,
235 AR724X_PCI_MEM_SIZE,
236 0,
237 - ATH79_CPU_IRQ_IP2);
238 + ATH79_CPU_IRQ(2));
239 } else if (soc_is_ar9342() ||
240 soc_is_ar9344()) {
241 u32 bootstrap;
242 --- a/arch/mips/include/asm/mach-ath79/irq.h
243 +++ b/arch/mips/include/asm/mach-ath79/irq.h
244 @@ -12,6 +12,8 @@
245 #define MIPS_CPU_IRQ_BASE 0
246 #define NR_IRQS 48
247
248 +#define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x))
249 +
250 #define ATH79_MISC_IRQ_BASE 8
251 #define ATH79_MISC_IRQ_COUNT 32
252 #define ATH79_MISC_IRQ(_x) (ATH79_MISC_IRQ_BASE + (_x))
253 @@ -24,13 +26,6 @@
254 #define ATH79_IP2_IRQ_COUNT 2
255 #define ATH79_IP2_IRQ(_x) (ATH79_IP2_IRQ_BASE + (_x))
256
257 -#define ATH79_CPU_IRQ_IP2 (MIPS_CPU_IRQ_BASE + 2)
258 -#define ATH79_CPU_IRQ_USB (MIPS_CPU_IRQ_BASE + 3)
259 -#define ATH79_CPU_IRQ_GE0 (MIPS_CPU_IRQ_BASE + 4)
260 -#define ATH79_CPU_IRQ_GE1 (MIPS_CPU_IRQ_BASE + 5)
261 -#define ATH79_CPU_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6)
262 -#define ATH79_CPU_IRQ_TIMER (MIPS_CPU_IRQ_BASE + 7)
263 -
264 #define ATH79_MISC_IRQ_TIMER (ATH79_MISC_IRQ_BASE + 0)
265 #define ATH79_MISC_IRQ_ERROR (ATH79_MISC_IRQ_BASE + 1)
266 #define ATH79_MISC_IRQ_GPIO (ATH79_MISC_IRQ_BASE + 2)
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